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Searched refs:REG_PIO_READ64 (Results 1 – 4 of 4) sorted by relevance

/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_fflp.c153 REG_PIO_READ64(handle, fflp_fzc_offset[i], &value); in npi_fflp_dump_regs()
165 REG_PIO_READ64(handle, fflp_reg_offset[i], &value); in npi_fflp_dump_regs()
194 REG_PIO_READ64(handle, offset, &value); in npi_fflp_vlan_tbl_dump()
772 REG_PIO_READ64(handle, data_reg, &fcram_ptr->value[subarea]); in npi_fflp_fcram_entry_read()
820 REG_PIO_READ64(handle, data_reg, &hdr.value); in npi_fflp_fcram_entry_invalidate()
944 REG_PIO_READ64(handle, data_reg, data); in npi_fflp_fcram_subarea_read()
1022 REG_PIO_READ64(handle, offset, &sel.value); in npi_fflp_cfg_fcram_partition_enable()
1058 REG_PIO_READ64(handle, offset, &sel.value); in npi_fflp_cfg_fcram_partition_disable()
1077 REG_PIO_READ64(handle, offset, &fflp_cfg.value); in npi_fflp_cfg_cam_errorcheck_disable()
1098 REG_PIO_READ64(handle, offset, &fflp_cfg.value); in npi_fflp_cfg_cam_errorcheck_enable()
[all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhpi_pfc.c187 REG_PIO_READ64(handle, offset, &configp->value); in hpi_pfc_get_config()
352 REG_PIO_READ64(handle, offset, (uint64_t *)&vlan_tbl_entry.value); in hpi_pfc_cfg_vlan_table_entry_clear()
375 REG_PIO_READ64(handle, offset, (uint64_t *)&vlan_tbl_entry.value); in hpi_pfc_cfg_vlan_table_entry_set()
417 REG_PIO_READ64(handle, offset, &logp->value); in hpi_pfc_get_vlan_parity_log()
562 REG_PIO_READ64(handle, offset, &l3_config.value); in hpi_pfc_get_l3_class_config()
658 REG_PIO_READ64(handle, offset, &logp->value); in hpi_pfc_get_tcam_parity_log()
669 REG_PIO_READ64(handle, offset, &autoinitp->value); in hpi_pfc_get_tcam_auto_init()
683 REG_PIO_READ64(handle, offset, &tcp.value); in hpi_pfc_set_tcp_control_discard()
704 REG_PIO_READ64(handle, offset, &tcp.value); in hpi_pfc_set_tcp_control_fin()
724 REG_PIO_READ64(handle, offset, &tcp.value); in hpi_pfc_set_tcp_control_syn()
[all …]
H A Dhxge_pfc.h50 #define REG_PIO_READ64(handle, offset, val_p) \ macro
64 REG_PIO_READ64(handle, PFC_TCAM_CTRL, val_p)
76 REG_PIO_READ64(handle, PFC_TCAM_KEY0, val_p)
78 REG_PIO_READ64(handle, PFC_TCAM_KEY1, val_p)
80 REG_PIO_READ64(handle, PFC_TCAM_MASK0, val_p)
82 REG_PIO_READ64(handle, PFC_TCAM_MASK1, val_p)
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_fflp_hw.h1097 #define REG_PIO_READ64(handle, offset, val_p) \ macro
1105 REG_PIO_READ64(handle, FFLP_TCAM_CTL_REG, val_p)
1126 REG_PIO_READ64(handle, FFLP_TCAM_KEY_0_REG, val_p)
1128 REG_PIO_READ64(handle, FFLP_TCAM_KEY_1_REG, val_p)
1130 REG_PIO_READ64(handle, FFLP_TCAM_KEY_2_REG, val_p)
1132 REG_PIO_READ64(handle, FFLP_TCAM_KEY_3_REG, val_p)
1134 REG_PIO_READ64(handle, FFLP_TCAM_MASK_0_REG, val_p)
1136 REG_PIO_READ64(handle, FFLP_TCAM_MASK_1_REG, val_p)
1138 REG_PIO_READ64(handle, FFLP_TCAM_MASK_2_REG, val_p)
1140 REG_PIO_READ64(handle, FFLP_TCAM_MASK_3_REG, val_p)