1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __TESTING__ 37 #define __TESTING__ 38 39 struct CfcLoadErrorTestParams 40 { 41 u8 testType; 42 u8 errorBits; 43 __le16 reserved1; 44 __le32 cid; 45 __le32 tid; 46 __le32 reserved2; 47 u8 reserved3[96]; 48 }; 49 50 51 struct EngineIsolationTestDmaRequestParams 52 { 53 __le32 dmaParams0; 54 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_DLENGTH_MASK 0xFFFF 55 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_DLENGTH_SHIFT 0 56 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_STINDEX_MASK 0x1FF 57 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_STINDEX_SHIFT 16 58 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_STHINT_MASK 0x3 59 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_STHINT_SHIFT 25 60 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_TPHVALID_MASK 0x7 61 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_TPHVALID_SHIFT 27 62 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ENDIANITY_MASK 0x3 63 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ENDIANITY_SHIFT 30 64 __le32 dmaParams1; 65 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ATC_MASK 0x7 66 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ATC_SHIFT 0 67 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_NOSNOOP_MASK 0x1 68 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_NOSNOOP_SHIFT 3 69 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_RELAXEDORDERING_MASK 0x1 70 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_RELAXEDORDERING_SHIFT 4 71 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRTYPE_MASK 0x1 72 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRTYPE_SHIFT 5 73 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_DONETYPE_MASK 0x1 74 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_DONETYPE_SHIFT 6 75 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_WAITFOREOP_MASK 0x1 76 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_WAITFOREOP_SHIFT 7 77 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_VQID_MASK 0x1F 78 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_VQID_SHIFT 8 79 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_LAST_MASK 0x7 80 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_LAST_SHIFT 13 81 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_OFID_MASK 0xFFFF 82 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_OFID_SHIFT 16 83 __le32 dmaParams2; 84 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRLO_MASK 0xFFFFFFFF 85 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRLO_SHIFT 0 86 __le32 dmaParams3; 87 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRHI_MASK 0xFFFFFFFF 88 #define ENGINEISOLATIONTESTDMAREQUESTPARAMS_ADDRHI_SHIFT 0 89 u8 immediateCount /* user should ensure that rest of the paramters agree (if needed) with the number of immediate dwords specified here */; 90 u8 unusedPad8; 91 __le16 unusedPad16; 92 __le32 unusedPad; 93 __le32 immediateDataValues[16]; 94 }; 95 96 97 enum EngineIsolationTestGrcAccessType 98 { 99 GRC_ACCESS_READ=1, 100 GRC_ACCESS_WRITE=2, 101 MAX_ENGINEISOLATIONTESTGRCACCESSTYPE 102 }; 103 104 105 struct EngineIsolationTestRequestParamsGrc 106 { 107 __le32 reg00Value /* Value to write to register, or value read back from register */; 108 u8 requestType; 109 u8 unused8; 110 __le16 opaqueFid; 111 __le32 regField; 112 #define ENGINEISOLATIONTESTREQUESTPARAMSGRC_REG00ADDR_MASK 0x7FFFFF 113 #define ENGINEISOLATIONTESTREQUESTPARAMSGRC_REG00ADDR_SHIFT 0 114 #define ENGINEISOLATIONTESTREQUESTPARAMSGRC_UNUSED9_MASK 0x1FF 115 #define ENGINEISOLATIONTESTREQUESTPARAMSGRC_UNUSED9_SHIFT 23 116 __le32 unused32; 117 __le32 unusedPad[22]; 118 }; 119 120 struct EngineIsolationTestRequestParamsSdmDma 121 { 122 __le32 hdrFields; 123 #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_LENGTH_MASK 0xFFF /* (hdr) dma hdr length */ 124 #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_LENGTH_SHIFT 0 125 #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_SRC_MASK 0xF /* (hdr) dma src (type) */ 126 #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_SRC_SHIFT 12 127 #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_DST_MASK 0xF /* (hdr) dma dst (type) */ 128 #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_DST_SHIFT 16 129 #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_UNUSED_MASK 0xFFF /* (hdr) dma dst (type) */ 130 #define ENGINEISOLATIONTESTREQUESTPARAMSSDMDMA_UNUSED_SHIFT 20 131 __le16 address /* (hdr) Short address in DMA hdr */; 132 __le16 unused16; 133 struct EngineIsolationTestDmaRequestParams dmaParams; 134 __le32 unused128[2]; 135 }; 136 137 struct EngineIsolationTestRequestParamsPrmDma 138 { 139 __le32 hdr0; 140 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PB_MASK 0x1 /* (hdr) pbFlag */ 141 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PB_SHIFT 0 142 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DIF_MASK 0x1 /* (hdr) difFlag */ 143 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DIF_SHIFT 1 144 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_TR_MASK 0x1 /* (hdr) tr flag */ 145 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_TR_SHIFT 2 146 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_LDRENQTRIG_MASK 0x1 /* (hdr) ldrEnqTrigFlag */ 147 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_LDRENQTRIG_SHIFT 3 148 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_LDRDONETRIG_MASK 0x1 /* (hdr) ldrDoneTrigFlag */ 149 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_LDRDONETRIG_SHIFT 4 150 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_WAITYEVENT_MASK 0x1 /* (hdr) waitYeventFlag */ 151 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_WAITYEVENT_SHIFT 5 152 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_WAITUEVENT_MASK 0x1 /* (hdr) waitUeventFlag */ 153 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_WAITUEVENT_SHIFT 6 154 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PTUMODE_MASK 0x1 /* (hdr) ptuMode */ 155 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PTUMODE_SHIFT 7 156 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_CMDLENGTH_MASK 0xFF /* (hdr) cmd length */ 157 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_CMDLENGTH_SHIFT 8 158 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_SRC_MASK 0x7 /* (hdr) src */ 159 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_SRC_SHIFT 16 160 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DST_MASK 0x1 /* (hdr) dst */ 161 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DST_SHIFT 19 162 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBNUMREL_MASK 0x3FF /* (hdr) brbNumRel */ 163 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBNUMREL_SHIFT 20 164 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBSRCREADREL_MASK 0x3 /* (hdr) brbSrcReadRel */ 165 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBSRCREADREL_SHIFT 30 166 __le32 hdr1; 167 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_SLENGTH_MASK 0xFF /* (hdr) slength */ 168 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_SLENGTH_SHIFT 0 169 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_INSERTPAD_MASK 0x1 /* (hdr) insertPad */ 170 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_INSERTPAD_SHIFT 8 171 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_REQTYPE_MASK 0x3 /* (hdr) reqType */ 172 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_REQTYPE_SHIFT 9 173 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_UNUSED5_MASK 0x1F 174 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_UNUSED5_SHIFT 11 175 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBOFFSET_MASK 0xFFFF /* (hdr) brbOffset */ 176 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBOFFSET_SHIFT 16 177 __le32 hdr2; 178 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBDEBUG_MASK 0xFFFF /* (hdr) brbDebug */ 179 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBDEBUG_SHIFT 0 180 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBSTARTBLK_MASK 0xFFFF /* (hdr) brbStartBlk */ 181 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_BRBSTARTBLK_SHIFT 16 182 __le32 dmaParamsPrmSpecific; 183 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DISCARD_MASK 0x1 184 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_DISCARD_SHIFT 0 185 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PADCL_MASK 0x1 186 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_PADCL_SHIFT 1 187 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_UNUSED30_MASK 0x3FFFFFFF 188 #define ENGINEISOLATIONTESTREQUESTPARAMSPRMDMA_UNUSED30_SHIFT 2 189 struct EngineIsolationTestDmaRequestParams dmaParams; 190 }; 191 192 union EngineIsolationTestSpecific 193 { 194 struct EngineIsolationTestRequestParamsGrc grcAccess; 195 struct EngineIsolationTestRequestParamsSdmDma sdmDma; 196 struct EngineIsolationTestRequestParamsPrmDma prmDma; 197 }; 198 199 struct EngineIsolationTestRequestParams 200 { 201 u8 testType; 202 u8 status /* user should set to idle, and then keep checking as long as status remains busy */; 203 __le16 unused16; 204 __le32 unused32; 205 union EngineIsolationTestSpecific testSpecific; 206 }; 207 208 209 210 211 212 213 enum EngineIsolationTestStatusType 214 { 215 TEST_STATUS_IDLE=0, 216 TEST_STATUS_BUSY=1, 217 TEST_STATUS_SUCCESS=2, 218 TEST_STATUS_FAILURE=255, 219 MAX_ENGINEISOLATIONTESTSTATUSTYPE 220 }; 221 222 223 enum EngineIsolationTestType 224 { 225 TEST_TYPE_SDM_GRC_ACCESS=1, 226 TEST_TYPE_SDM_DMA=2, 227 TEST_TYPE_PRM_DMA=3, 228 MAX_ENGINEISOLATIONTESTTYPE 229 }; 230 231 232 struct IntegTestDataHdr 233 { 234 u8 opcode; 235 u8 enable; 236 u8 reserved[6]; 237 }; 238 239 struct LatencyMeasurementParams 240 { 241 __le32 numMeasurements /* Number of measurements to conduct. Will be rounded down to nearest power of 2 */; 242 __le32 meanMeasurement /* Average time of all measurements in 40ns units */; 243 __le32 minMeasurement /* Minimum time taken in 40ns units */; 244 __le32 maxMeasurement /* Maximum time taken in 40ns units */; 245 __le32 delay /* Time to wait between measurements in us */; 246 __le32 addrLo /* DMA address. Will be set by first PF to load */; 247 __le32 addrHi /* DMA address. Will be set by first PF to load */; 248 u8 pfId /* PF id. Will be set by first PF to load */; 249 u8 done /* Bit indicating measurement is done */; 250 u8 error /* Bit indicating there was an error during the measurement */; 251 u8 reserved; 252 __le32 reserved1[20]; 253 }; 254 255 struct PramParityErrorTestParams 256 { 257 __le32 done; 258 __le32 reserved; 259 u8 reserved1[104]; 260 }; 261 262 struct PqTxQueuePciAccess 263 { 264 __le32 pause; 265 __le16 queueId; 266 __le16 reserved0; 267 u8 reserved1[104]; 268 }; 269 270 struct PfcTestParams 271 { 272 u8 pause; 273 u8 portId; 274 u8 tcPauseBitmap; 275 u8 reserved0[5]; 276 u8 reserved1[104]; 277 }; 278 279 struct QmInterfacesTestParams 280 { 281 __le16 connection_icid; 282 __le16 connection_fid; 283 __le32 counter; 284 __le32 dataValid; 285 __le32 incomingCid; 286 u8 reserved[96]; 287 }; 288 289 struct SflowTestParams 290 { 291 u8 header[32]; 292 u8 headerSize; 293 u8 sendFactor; 294 u8 reserved[6]; 295 u8 reserved1[72]; 296 }; 297 298 struct IntegTestEdpmIntfEnParams 299 { 300 u8 releaseExistInQm; 301 u8 existInQmReleased; 302 u8 setXoffState; 303 u8 setXonState; 304 u8 reserved[4]; 305 u8 reserved1[104]; 306 }; 307 308 struct VfcStressTestParams 309 { 310 __le32 done; 311 __le32 status; 312 __le32 last_index; 313 __le32 mac_filter_cnt; 314 __le32 vlan_filter_cnt; 315 __le32 pair_filter_cnt; 316 u8 reserved[88]; 317 }; 318 319 struct UnmaskSdmTestParams 320 { 321 u8 sdmUnmaskIntIndex /* SDM aggregative interrupt index to unmask */; 322 u8 reserved[111]; 323 }; 324 325 struct QcnRlTestParams 326 { 327 __le32 done; 328 __le32 status; 329 u8 rl_id; 330 u8 cmd; 331 __le16 val; 332 __le32 repeat_cnt; 333 __le32 repeat_interval_us; 334 __le16 force_dcqcn_alpha; 335 __le16 reserved; 336 __le32 reserved1[22]; 337 }; 338 339 union IntegTestDataParams 340 { 341 struct LatencyMeasurementParams latencyMeasurementParams; 342 struct PramParityErrorTestParams pramParityErrorTestParams; 343 struct PqTxQueuePciAccess pqTxQueuePciAccess; 344 struct PfcTestParams pfcTestParams; 345 struct QmInterfacesTestParams qmInterfacesTestParams; 346 struct SflowTestParams sFlowTestParams; 347 struct CfcLoadErrorTestParams cfcLoadErrorTestParams; 348 struct IntegTestEdpmIntfEnParams edpmIntfEnTestParams; 349 struct EngineIsolationTestRequestParams engineIsolationTestParams; 350 struct VfcStressTestParams vfcStressTestParams; 351 struct UnmaskSdmTestParams unmaskSdmTestParams; 352 struct QcnRlTestParams qcnRlTestParams; 353 }; 354 355 struct IntegTestData 356 { 357 struct IntegTestDataHdr hdr; 358 union IntegTestDataParams params; 359 }; 360 361 362 363 364 365 enum IntegTestOpcodeEnum 366 { 367 PRAM_PARITY_ERROR_RECOVERY=0, 368 SDM_TCFC_AC_TEST=1, 369 XY_LOADER_PCI_ERRORS_TEST=2, 370 MU_LOADER_PCI_ERRORS_TEST=3, 371 TM_LOADER_PCI_ERRORS_TEST=4, 372 XY_LOADER_CFC_ERRORS_TEST=5, 373 MU_LOADER_CFC_ERRORS_TEST=6, 374 TM_LOADER_CFC_ERRORS_TEST=7, 375 X_QM_PAUSE_TX_PQ_ERRORS_TEST=8, 376 X_QM_UNPAUSE_TX_PQ_ERRORS_TEST=9, 377 X_QM_QUEUES_PCI_ACCESS_TEST=10, 378 RECORDING_HANDLER_TEST=12, 379 PFC_TX_TEST=13, 380 PFC_RX_PRS_TEST=14, 381 PFC_RX_NIG_TEST=15, 382 QM_INTERFACES_TEST=16, 383 PROP_HEADER_TEST=17, 384 S_FLOW_TEST=18, 385 CFC_ERRORS_TEST=19, 386 M_ENGINE_ISOLATION_TEST=20, 387 VFC_STRESS_TEST=30, 388 SDM_AGG_INT_UNMASK_TEST=31, 389 CDU_VALIDATION_TEST=32, 390 QCN_RL_TEST=33, 391 LATENCY_MEASURMENT_TEST=34, 392 MAX_INTEGTESTOPCODEENUM 393 }; 394 395 396 397 398 399 400 enum QcnRlTestCmdType 401 { 402 QCN_RL_TEST_CNM /* Simulite CNM arriveal. CNM interval and amount can be configurated. */, 403 QCN_RL_TEST_PKT, 404 QCN_RL_TEST_TIMER, 405 QCN_RL_UNMASK_INTERRUPT, 406 MAX_QCNRLTESTCMDTYPE 407 }; 408 409 410 411 412 413 414 415 enum VfcStressTestStatusType 416 { 417 VFC_STRESS_SUCCSES=0, 418 VFC_STRESS_INIT, 419 VFC_STRESS_MAC_SEARCH, 420 VFC_STRESS_VLAN_SEARCH, 421 VFC_STRESS_PAIR_SEARCH, 422 VFC_STRESS_CLEAN, 423 VFC_STRESS_MAC_NOT_FOUND, 424 VFC_STRESS_MAC_NOT_SET_MTT, 425 VFC_STRESS_MAC_NOT_SET_STT, 426 VFC_STRESS_VLAN_NOT_FOUND, 427 VFC_STRESS_VLAN_NOT_SET, 428 VFC_STRESS_PAIR_NOT_FOUND, 429 VFC_STRESS_PAIR_NOT_SET, 430 VFC_STRESS_VLAN_CNT_NON_ZERO, 431 VFC_STRESS_VFC_CNT_NON_ZERO, 432 VFC_STRESS_VLAN_MOVE_FAIL, 433 MAX_VFCSTRESSTESTSTATUSTYPE 434 }; 435 436 #endif /* __TESTING__ */ 437