1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef _PCICS_REG_DRIVER_H 37 #define _PCICS_REG_DRIVER_H 38 39 /* offset of configuration space in the pci core register */ 40 #ifndef __EXTRACT__LINUX__ 41 #define PCICFG_OFFSET 0x2000 42 #endif 43 #define PCICFG_VENDOR_ID_OFFSET 0x00 44 #define PCICFG_DEVICE_ID_OFFSET 0x02 45 #define PCICFG_COMMAND_OFFSET 0x04 46 #define PCICFG_COMMAND_IO_SPACE (1<<0) 47 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 48 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 49 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 50 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 51 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 52 #define PCICFG_COMMAND_PERR_ENA (1<<6) 53 #define PCICFG_COMMAND_STEPPING (1<<7) 54 #define PCICFG_COMMAND_SERR_ENA (1<<8) 55 #define PCICFG_COMMAND_FAST_B2B (1<<9) 56 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 57 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 58 #define PCICFG_STATUS_OFFSET 0x06 59 #define PCICFG_REVISION_ID_OFFSET 0x08 60 #define PCICFG_REVESION_ID_MASK 0xff 61 #define PCICFG_REVESION_ID_ERROR_VAL 0xff 62 #define PCICFG_CACHE_LINE_SIZE 0x0c 63 #define PCICFG_LATENCY_TIMER 0x0d 64 #define PCICFG_HEADER_TYPE 0x0e 65 #define PCICFG_HEADER_TYPE_NORMAL 0 66 #define PCICFG_HEADER_TYPE_BRIDGE 1 67 #define PCICFG_HEADER_TYPE_CARDBUS 2 68 #define PCICFG_BAR_1_LOW 0x10 69 #define PCICFG_BAR_1_HIGH 0x14 70 #define PCICFG_BAR_2_LOW 0x18 71 #define PCICFG_BAR_2_HIGH 0x1c 72 #define PCICFG_BAR_3_LOW 0x20 73 #define PCICFG_BAR_3_HIGH 0x24 74 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 75 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 76 #define PCICFG_INT_LINE 0x3c 77 #define PCICFG_INT_PIN 0x3d 78 #define PCICFG_PM_CAPABILITY 0x48 79 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 80 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 81 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 82 #define PCICFG_PM_CAPABILITY_DSI (1<<21) 83 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 84 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 85 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 86 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 87 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 88 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 89 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 90 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 91 #define PCICFG_PM_CSR_OFFSET 0x4c 92 #define PCICFG_PM_CSR_STATE (0x3<<0) 93 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 94 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 95 #define PCICFG_MSI_CAP_ID_OFFSET 0x58 96 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 97 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 98 #define PCICFG_MSI_CONTROL_MENA (0x7<<20) 99 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 100 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 101 #define PCICFG_GRC_ADDRESS 0x78 102 #define PCICFG_GRC_DATA 0x80 103 #define PCICFG_ME_REGISTER 0x98 104 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 105 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 106 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 107 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 108 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 109 110 #define PCICFG_DEVICE_CONTROL 0xb4 111 #define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21) 112 #define PCICFG_DEVICE_STATUS 0xb6 113 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 114 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 115 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 116 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 117 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 118 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 119 #define PCICFG_LINK_CONTROL 0xbc 120 #define PCICFG_DEVICE_STATUS_CONTROL_2 (0xd4) 121 #define PCICFG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE (1<<6) 122 123 /* config_2 offset */ 124 #define GRC_CONFIG_2_SIZE_REG 0x408 125 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 126 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 127 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 128 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 129 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 130 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 131 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 132 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 133 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 134 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 135 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 136 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 137 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 138 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 139 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 140 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 141 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 142 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 143 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 144 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 145 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 146 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 147 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 148 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 149 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 150 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 151 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 152 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 153 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 154 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 155 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 156 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 157 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 158 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 159 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 160 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 161 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 162 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 163 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 164 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 165 166 /* config_3 offset */ 167 #define GRC_CONFIG_3_SIZE_REG 0x40c 168 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 169 #define PCI_CONFIG_3_FORCE_PME (1L<<24) 170 #define PCI_CONFIG_3_PME_STATUS (1L<<25) 171 #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 172 #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 173 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 174 #define PCI_CONFIG_3_PCI_POWER (1L<<31) 175 176 #define GRC_REG_DEVICE_CONTROL 0x4d8 177 178 /* When VF Enable is cleared(after it was previously set), 179 * this register will read a value of 1, indicating that all the 180 * VFs that belong to this PF should be flushed. 181 * Software should clear this bit within 1 second of VF Enable 182 * being set by writing a 1 to it, so that VFs are visible to the system 183 * again.WC 184 */ 185 #define PCIE_SRIOV_DISABLE_IN_PROGRESS (1 << 29) 186 187 /* When FLR is initiated, this register will read a value of 1 indicating 188 * that the Function is in FLR state. Func can be brought out of FLR state 189 * either bywriting 1 to this register (at least 50 ms after FLR was 190 * initiated),or it can also be cleared automatically after 55 ms if 191 * auto_clear bit in private reg space is set. This bit also exists in 192 * VF register space WC 193 */ 194 #define PCIE_FLR_IN_PROGRESS (1 << 27) 195 196 #define GRC_BAR2_CONFIG 0x4e0 197 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 198 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 199 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 200 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 201 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 202 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 203 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 204 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 205 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 206 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 207 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 208 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 209 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 210 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 211 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 212 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 213 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 214 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 215 216 #define GRC_BAR3_CONFIG 0x4f4 217 #define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0) 218 #define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0) 219 #define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0) 220 #define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0) 221 #define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0) 222 #define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0) 223 #define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0) 224 #define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0) 225 #define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0) 226 #define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0) 227 #define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0) 228 #define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0) 229 #define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0) 230 #define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0) 231 #define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0) 232 #define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0) 233 #define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0) 234 #define PCI_CONFIG_2_BAR3_64ENA (1L<<4) 235 #define PCI_PM_DATA_A 0x410 236 #define PCI_PM_DATA_B 0x414 237 #define PCI_ID_VAL1 0x434 238 #define PCI_ID_VAL2 0x438 239 #define PCI_ID_VAL3 0x43c 240 #define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24) 241 #define GRC_CONFIG_REG_VF_BAR_REG_1 0x608 242 #define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf 243 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C 244 245 /* This field resides in VF only and does not exist in PF. 246 * This register controls the read value of the MSIX_CONTROL[10:0] register 247 * in the VF configuration space. A value of "00000000011" indicates 248 * a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ 249 * define in version.v 250 */ 251 #define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK 0x3F 252 #ifndef __EXTRACT__LINUX__ 253 #define GRC_CONFIG_REG_PF_INIT_VF 0x624 254 255 /* First VF_NUM for PF is encoded in this register. 256 * The number of VFs assigned to a PF is assumed to be a multiple of 8. 257 * Software should program these bits based on Total Number of VFs programmed 258 * for each PF. 259 * Since registers from 0x000-0x7ff are spilt across functions, each PF will 260 * have the same location for the same 4 bits 261 */ 262 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xff 263 #endif 264 #define PXPCS_TL_CONTROL_5 0x814 265 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 266 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 267 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 268 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 269 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 270 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 271 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 272 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 273 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 274 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 275 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 276 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 277 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 278 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 279 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 280 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 281 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 282 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 283 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 284 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 285 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 286 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 287 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 288 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 289 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 290 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 291 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 292 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 293 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 294 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 295 #define PXPCS_TL_FUNC345_STAT 0x854 296 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 297 298 /*Unsupported Request Error Status in function4, if set, generate 299 *pcie_err_attn output when this error is seen. WC 300 */ 301 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 (1 << 28) 302 303 /*ECRC Error TLP Status Status in function 4, if set, 304 *generate pcie_err_attn output when this error is seen..WC 305 */ 306 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 (1 << 27) 307 308 /*Malformed TLP Status Status in function 4, if set, 309 *generate pcie_err_attn output when this error is seen..WC 310 */ 311 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 (1 << 26) 312 313 /*Receiver Overflow Status Status in function 4, if set, 314 *generate pcie_err_attn output when this error is seen..WC 315 */ 316 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 (1 << 25) 317 318 /*Unexpected Completion Status Status in function 4, if set, 319 *generate pcie_err_attn output when this error is seen..WC 320 */ 321 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 (1 << 24) 322 323 /* Receive UR Statusin function 4. If set, generate pcie_err_attn output 324 * when this error is seen. WC 325 */ 326 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 (1 << 23) 327 328 /* Completer Timeout Status Status in function 4, if set, 329 * generate pcie_err_attn output when this error is seen..WC 330 */ 331 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 (1 << 22) 332 333 /* Flow Control Protocol Error Status Status in function 4, 334 * if set, generate pcie_err_attn output when this error is seen. 335 * WC 336 */ 337 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 (1 << 21) 338 339 /* Poisoned Error Status Status in function 4, if set, generate 340 * pcie_err_attn output when this error is seen..WC 341 */ 342 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 (1 << 20) 343 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 344 345 /* Unsupported Request Error Status in function3, if set, generate 346 * pcie_err_attn output when this error is seen..WC 347 */ 348 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 (1 << 18) 349 350 /* ECRC Error TLP Status Status in function 3, if set, generate 351 * pcie_err_attn output when this error is seen.. WC 352 */ 353 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 (1 << 17) 354 355 /* Malformed TLP Status Status in function 3, if set, generate 356 * pcie_err_attn output when this error is seen..WC 357 */ 358 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 (1 << 16) 359 360 /* Receiver Overflow Status Status in function 3, if set, generate 361 * pcie_err_attn output when this error is seen..WC 362 */ 363 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 (1 << 15) 364 365 /* Unexpected Completion Status Status in function 3, if set, generate 366 * pcie_err_attn output when this error is seen. WC 367 */ 368 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 (1 << 14) 369 370 /* Receive UR Statusin function 3. If set, generate pcie_err_attn output 371 * when this error is seen. WC 372 */ 373 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 (1 << 13) 374 375 /* Completer Timeout Status Status in function 3, if set, generate 376 * pcie_err_attn output when this error is seen..WC 377 */ 378 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 (1 << 12) 379 380 /* Flow Control Protocol Error Status Status in function 3, if set, 381 * generate pcie_err_attn output when this error is seen..WC 382 */ 383 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 (1 << 11) 384 385 /* Poisoned Error Status Status in function 3, if set, generate 386 * pcie_err_attn output when this error is seen..WC 387 */ 388 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 (1 << 10) 389 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 390 391 /* Unsupported Request Error Status for Function 2, if set, 392 * generate pcie_err_attn output when this error is seen. WC 393 */ 394 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 (1 << 8) 395 396 /* ECRC Error TLP Status Status for Function 2, if set, generate 397 * pcie_err_attn output when this error is seen..WC 398 */ 399 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 (1 << 7) 400 401 /* Malformed TLP Status Status for Function 2, if set, generate 402 * pcie_err_attn output when this error is seen.. WC 403 */ 404 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 (1 << 6) 405 406 /* Receiver Overflow Status Status for Function 2, if set, generate 407 * pcie_err_attn output when this error is seen.. WC 408 */ 409 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 (1 << 5) 410 411 /* Unexpected Completion Status Status for Function 2, if set, generate 412 * pcie_err_attn output when this error is seen. WC 413 */ 414 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 (1 << 4) 415 416 /* Receive UR Statusfor Function 2. If set, generate pcie_err_attn output 417 * when this error is seen. WC 418 */ 419 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 (1 << 3) 420 421 /* Completer Timeout Status Status for Function 2, if set, generate 422 * pcie_err_attn output when this error is seen. WC 423 */ 424 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 (1 << 2) 425 426 /* Flow Control Protocol Error Status Status for Function 2, if set, 427 * generate pcie_err_attn output when this error is seen. WC 428 */ 429 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 (1 << 1) 430 431 /* Poisoned Error Status Status for Function 2, if set, generate 432 * pcie_err_attn output when this error is seen.. WC 433 */ 434 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 (1 << 0) 435 #define PXPCS_TL_FUNC678_STAT 0x85C 436 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 437 438 /* Unsupported Request Error Status in function7, if set, generate 439 * pcie_err_attn output when this error is seen. WC 440 */ 441 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 (1 << 28) 442 443 /* ECRC Error TLP Status Status in function 7, if set, generate 444 * pcie_err_attn output when this error is seen.. WC 445 */ 446 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 (1 << 27) 447 448 /* Malformed TLP Status Status in function 7, if set, generate 449 * pcie_err_attn output when this error is seen.. WC 450 */ 451 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 (1 << 26) 452 453 /* Receiver Overflow Status Status in function 7, if set, generate 454 * pcie_err_attn output when this error is seen.. WC 455 */ 456 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 (1 << 25) 457 458 /* Unexpected Completion Status Status in function 7, if set, generate 459 * pcie_err_attn output when this error is seen. WC 460 */ 461 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 (1 << 24) 462 463 /* Receive UR Statusin function 7. If set, generate pcie_err_attn 464 * output when this error is seen. WC 465 */ 466 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 (1 << 23) 467 468 /* Completer Timeout Status Status in function 7, if set, generate 469 * pcie_err_attn output when this error is seen. WC 470 */ 471 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 (1 << 22) 472 473 /* Flow Control Protocol Error Status Status in function 7, if set, 474 * generate pcie_err_attn output when this error is seen. WC 475 */ 476 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 (1 << 21) 477 478 /* Poisoned Error Status Status in function 7, if set, 479 * generate pcie_err_attn output when this error is seen.. WC 480 */ 481 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 (1 << 20) 482 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 483 484 /* Unsupported Request Error Status in function6, if set, generate 485 * pcie_err_attn output when this error is seen. WC 486 */ 487 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 (1 << 18) 488 489 /* ECRC Error TLP Status Status in function 6, if set, generate 490 * pcie_err_attn output when this error is seen.. WC 491 */ 492 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 (1 << 17) 493 494 /* Malformed TLP Status Status in function 6, if set, generate 495 * pcie_err_attn output when this error is seen.. WC 496 */ 497 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 (1 << 16) 498 499 /* Receiver Overflow Status Status in function 6, if set, generate 500 * pcie_err_attn output when this error is seen.. WC 501 */ 502 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 (1 << 15) 503 504 /* Unexpected Completion Status Status in function 6, if set, 505 * generate pcie_err_attn output when this error is seen. WC 506 */ 507 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 (1 << 14) 508 509 /* Receive UR Statusin function 6. If set, generate pcie_err_attn 510 * output when this error is seen. WC 511 */ 512 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 (1 << 13) 513 514 /* Completer Timeout Status Status in function 6, if set, generate 515 * pcie_err_attn output when this error is seen. WC 516 */ 517 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 (1 << 12) 518 519 /* Flow Control Protocol Error Status Status in function 6, if set, 520 * generate pcie_err_attn output when this error is seen. WC 521 */ 522 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 (1 << 11) 523 524 /* Poisoned Error Status Status in function 6, if set, generate 525 * pcie_err_attn output when this error is seen.. WC 526 */ 527 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 (1 << 10) 528 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 529 530 /* Unsupported Request Error Status for Function 5, if set, 531 * generate pcie_err_attn output when this error is seen. WC 532 */ 533 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 (1 << 8) 534 535 /* ECRC Error TLP Status Status for Function 5, if set, generate 536 * pcie_err_attn output when this error is seen.. WC 537 */ 538 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 (1 << 7) 539 540 /* Malformed TLP Status Status for Function 5, if set, generate 541 * pcie_err_attn output when this error is seen.. WC 542 */ 543 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 (1 << 6) 544 545 /* Receiver Overflow Status Status for Function 5, if set, generate 546 * pcie_err_attn output when this error is seen.. WC 547 */ 548 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 (1 << 5) 549 550 /* Unexpected Completion Status Status for Function 5, if set, generate 551 * pcie_err_attn output when this error is seen. WC 552 */ 553 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 (1 << 4) 554 555 /* Receive UR Statusfor Function 5. If set, generate pcie_err_attn output 556 * when this error is seen. WC 557 */ 558 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 (1 << 3) 559 560 /* Completer Timeout Status Status for Function 5, if set, generate 561 * pcie_err_attn output when this error is seen. WC 562 */ 563 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 (1 << 2) 564 565 /* Flow Control Protocol Error Status Status for Function 5, if set, 566 * generate pcie_err_attn output when this error is seen. WC 567 */ 568 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 (1 << 1) 569 570 /* Poisoned Error Status Status for Function 5, if set, 571 * generate pcie_err_attn output when this error is seen.. WC 572 */ 573 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 (1 << 0) 574 575 /* PCI CAPABILITIES 576 */ 577 578 #define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/ 579 580 #define PCIE_DEV_CAPS 0x04 581 #ifndef PCIE_DEV_CAPS_FLR_CAPABILITY 582 #define PCIE_DEV_CAPS_FLR_CAPABILITY (1 << 28) 583 #endif 584 585 #define PCIE_DEV_CTRL 0x08 586 #define PCIE_DEV_CTRL_FLR 0x8000 587 588 #define PCIE_DEV_STATUS 0x0A 589 #ifndef PCIE_DEV_STATUS_PENDING_TRANSACTION 590 #define PCIE_DEV_STATUS_PENDING_TRANSACTION (1 << 5) 591 #endif 592 593 #ifndef PCI_CAPABILITY_LIST 594 /* Ofset of first capability list entry */ 595 #define PCI_CAPABILITY_LIST 0x34 596 #endif 597 598 #define PCI_CAPABILITY_LIST_MASK 0xff 599 600 #ifndef PCI_CB_CAPABILITY_LIST 601 #define PCI_CB_CAPABILITY_LIST 0x14 602 #endif 603 604 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID)) 605 #define PCI_CAP_LIST_ID_DEF 606 #endif 607 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT)) 608 #define PCI_CAP_LIST_NEXT_DEF 609 #endif 610 #if (defined(__LINUX)) || (defined(PCI_STATUS)) 611 #define PCI_STATUS_DEF 612 #endif 613 #if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST)) 614 #define PCI_STATUS_CAP_LIST_DEF 615 #endif 616 617 #ifndef PCI_CAP_LIST_ID_DEF 618 #define PCI_CAP_LIST_ID 0x0 /* Capability ID */ 619 #endif 620 621 #define PCI_CAP_LIST_ID_MASK 0xff 622 623 #ifndef PCI_CAP_LIST_NEXT_DEF 624 /* Next capability in the list */ 625 #define PCI_CAP_LIST_NEXT 0x1 626 #endif 627 628 #define PCI_CAP_LIST_NEXT_MASK 0xff 629 630 #ifndef PCI_STATUS_DEF 631 #define PCI_STATUS 0x6 /* 16 bits */ 632 #endif 633 #ifndef PCI_STATUS_CAP_LIST_DEF 634 /* Support Capability List */ 635 #define PCI_STATUS_CAP_LIST 0x10 636 #endif 637 638 #ifndef PCI_SRIOV_CAP 639 640 /* Some PCI Config defines... need to put this in a better location... */ 641 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 642 #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 643 #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 644 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 645 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 646 #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ 647 #define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ 648 #define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ 649 #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ 650 #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ 651 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 652 #define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ 653 #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 654 #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 655 #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 656 #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 657 #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 658 #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 659 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 660 #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 661 #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ 662 663 #endif 664 665 #ifndef PCI_CAP_ID_EXP 666 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 667 #endif 668 #ifndef PCI_EXP_DEVCTL 669 #define PCI_EXP_DEVCTL 8 /* Device Control */ 670 #endif 671 #ifndef PCI_EXP_DEVCTL_RELAX_EN 672 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 673 #endif 674 675 #endif 676