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Searched refs:MSR_AMD_GSBASE (Results 1 – 16 of 16) sorted by relevance

/illumos-gate/usr/src/uts/i86pc/os/
H A Dmach_kdi.c159 old = (uintptr_t)rdmsr(MSR_AMD_GSBASE); in boot_kdi_tmpinit()
160 wrmsr(MSR_AMD_GSBASE, (uint64_t)cpu); in boot_kdi_tmpinit()
167 wrmsr(MSR_AMD_GSBASE, (uint64_t)old); in boot_kdi_tmpfini()
H A Dtrap.c1657 printf(fmt, "fsb", rdmsr(MSR_AMD_FSBASE), "gsb", rdmsr(MSR_AMD_GSBASE), in dumpregs()
/illumos-gate/usr/src/grub/grub-0.97/stage2/
H A Dcontrolregs.h126 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ macro
/illumos-gate/usr/src/uts/i86pc/ml/
H A Dbios_call_src.S104 movl $MSR_AMD_GSBASE, %ecx
369 movl $MSR_AMD_GSBASE, %ecx
H A Dmpcore.S242 movl $MSR_AMD_GSBASE, %ecx
H A Dfb_swtch_src.S114 movl $MSR_AMD_GSBASE, %ecx
H A Dcpr_wakecode.S138 movl $MSR_AMD_GSBASE, %ecx / save gsbase msr
630 movl $MSR_AMD_GSBASE, %ecx / restore gsbase msr
/illumos-gate/usr/src/uts/intel/sys/
H A Dcontrolregs.h202 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ macro
/illumos-gate/usr/src/uts/intel/kdi/
H A Dkdi_asm.S86 movl $MSR_AMD_GSBASE, %ecx; \
104 movl $MSR_AMD_GSBASE, %ecx; \
282 movl $MSR_AMD_GSBASE, %ecx
/illumos-gate/usr/src/uts/intel/os/
H A Dsundep.c565 wrmsr(MSR_AMD_GSBASE, kgsbase); in update_sregs()
665 wrmsr(MSR_AMD_GSBASE, kgsbase); in reset_sregs()
H A Ddesctbls.c670 wrmsr(MSR_AMD_GSBASE, (uint64_t)&cpus[0]); in init_gdt()
H A Darchdep.c902 PANICNVADD(pnv, "gsbase", rdmsr(MSR_AMD_GSBASE)); in panic_saveregs()
/illumos-gate/usr/src/uts/intel/amd64/sys/
H A Dprivregs.h140 movl $MSR_AMD_GSBASE, %ecx; \
/illumos-gate/usr/src/uts/intel/ml/
H A Dexception.S238 movl $MSR_AMD_GSBASE, %ecx; /* yes, set GSBASE */ \
/illumos-gate/usr/src/uts/i86xpv/os/
H A Dxpv_panic.c734 wrmsr(MSR_AMD_GSBASE, (uint64_t)&cpus[0]); in xpv_do_panic()
/illumos-gate/usr/src/uts/intel/dtrace/
H A Dfasttrap_isa.c1664 case REG_GSBASE: return (rdmsr(MSR_AMD_GSBASE)); in fasttrap_getreg()