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Searched refs:MISC_REG_CPMU_LP_IDLE_THR_P0 (Results 1 – 2 of 2) sorted by relevance

/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c3195 REG_WR(cb, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in elink_eee_set_timers()
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h6136 #define MISC_REG_CPMU_LP_IDLE_THR_P0 macro