1 /**************************************************************************
2 * ns83820.c: Etherboot device driver for the National Semiconductor 83820
3 * Written 2004 by Timothy Legge <tlegge@rogers.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Portions of this code based on:
20 * ns83820.c by Benjamin LaHaise with contributions
21 * for Linux kernel 2.4.x.
22 *
23 * Linux Driver Version 0.20, 20020610
24 *
25 * This development of this Etherboot driver was funded by:
26 *
27 * NXTV: http://www.nxtv.com/
28 *
29 * REVISION HISTORY:
30 * ================
31 *
32 * v1.0 02-16-2004 timlegge Initial port of Linux driver
33 * v1.1 02-19-2004 timlegge More rohbust transmit and poll
34 *
35 * Indent Options: indent -kr -i8
36 ***************************************************************************/
37
38 /* to get some global routines like printf */
39 #include "etherboot.h"
40 /* to get the interface to the body of the program */
41 #include "nic.h"
42 /* to get the PCI support functions, if this is a PCI NIC */
43 #include "pci.h"
44
45 #if ARCH == ia64 /* Support 64-bit addressing */
46 #define USE_64BIT_ADDR
47 #endif
48
49 //#define DDEBUG
50 #ifdef DDEBUG
51 #define dprintf(x) printf x
52 #else
53 #define dprintf(x)
54 #endif
55
56 typedef unsigned char u8;
57 typedef signed char s8;
58 typedef unsigned short u16;
59 typedef signed short s16;
60 typedef unsigned int u32;
61 typedef signed int s32;
62
63 #define HZ 100
64
65 /* Condensed operations for readability. */
66 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
67 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
68
69 /* NIC specific static variables go here */
70
71 /* Global parameters. See MODULE_PARM near the bottom. */
72 // static int ihr = 2;
73 static int reset_phy = 0;
74 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
75
76 #if defined(CONFIG_HIGHMEM64G) || defined(__ia64__)
77 #define USE_64BIT_ADDR "+"
78 #endif
79
80 #if defined(USE_64BIT_ADDR)
81 #define TRY_DAC 1
82 #else
83 #define TRY_DAC 0
84 #endif
85
86 /* tunables */
87 #define RX_BUF_SIZE 1500 /* 8192 */
88
89 /* Must not exceed ~65000. */
90 #define NR_RX_DESC 64
91 #define NR_TX_DESC 1
92
93 /* not tunable *//* Extra 6 bytes for 64 bit alignment (divisable by 8) */
94 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14 + 6) /* rx/tx mac addr + type */
95
96 #define MIN_TX_DESC_FREE 8
97
98 /* register defines */
99 #define CFGCS 0x04
100
101 #define CR_TXE 0x00000001
102 #define CR_TXD 0x00000002
103 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
104 * The Receive engine skips one descriptor and moves
105 * onto the next one!! */
106 #define CR_RXE 0x00000004
107 #define CR_RXD 0x00000008
108 #define CR_TXR 0x00000010
109 #define CR_RXR 0x00000020
110 #define CR_SWI 0x00000080
111 #define CR_RST 0x00000100
112
113 #define PTSCR_EEBIST_FAIL 0x00000001
114 #define PTSCR_EEBIST_EN 0x00000002
115 #define PTSCR_EELOAD_EN 0x00000004
116 #define PTSCR_RBIST_FAIL 0x000001b8
117 #define PTSCR_RBIST_DONE 0x00000200
118 #define PTSCR_RBIST_EN 0x00000400
119 #define PTSCR_RBIST_RST 0x00002000
120
121 #define MEAR_EEDI 0x00000001
122 #define MEAR_EEDO 0x00000002
123 #define MEAR_EECLK 0x00000004
124 #define MEAR_EESEL 0x00000008
125 #define MEAR_MDIO 0x00000010
126 #define MEAR_MDDIR 0x00000020
127 #define MEAR_MDC 0x00000040
128
129 #define ISR_TXDESC3 0x40000000
130 #define ISR_TXDESC2 0x20000000
131 #define ISR_TXDESC1 0x10000000
132 #define ISR_TXDESC0 0x08000000
133 #define ISR_RXDESC3 0x04000000
134 #define ISR_RXDESC2 0x02000000
135 #define ISR_RXDESC1 0x01000000
136 #define ISR_RXDESC0 0x00800000
137 #define ISR_TXRCMP 0x00400000
138 #define ISR_RXRCMP 0x00200000
139 #define ISR_DPERR 0x00100000
140 #define ISR_SSERR 0x00080000
141 #define ISR_RMABT 0x00040000
142 #define ISR_RTABT 0x00020000
143 #define ISR_RXSOVR 0x00010000
144 #define ISR_HIBINT 0x00008000
145 #define ISR_PHY 0x00004000
146 #define ISR_PME 0x00002000
147 #define ISR_SWI 0x00001000
148 #define ISR_MIB 0x00000800
149 #define ISR_TXURN 0x00000400
150 #define ISR_TXIDLE 0x00000200
151 #define ISR_TXERR 0x00000100
152 #define ISR_TXDESC 0x00000080
153 #define ISR_TXOK 0x00000040
154 #define ISR_RXORN 0x00000020
155 #define ISR_RXIDLE 0x00000010
156 #define ISR_RXEARLY 0x00000008
157 #define ISR_RXERR 0x00000004
158 #define ISR_RXDESC 0x00000002
159 #define ISR_RXOK 0x00000001
160
161 #define TXCFG_CSI 0x80000000
162 #define TXCFG_HBI 0x40000000
163 #define TXCFG_MLB 0x20000000
164 #define TXCFG_ATP 0x10000000
165 #define TXCFG_ECRETRY 0x00800000
166 #define TXCFG_BRST_DIS 0x00080000
167 #define TXCFG_MXDMA1024 0x00000000
168 #define TXCFG_MXDMA512 0x00700000
169 #define TXCFG_MXDMA256 0x00600000
170 #define TXCFG_MXDMA128 0x00500000
171 #define TXCFG_MXDMA64 0x00400000
172 #define TXCFG_MXDMA32 0x00300000
173 #define TXCFG_MXDMA16 0x00200000
174 #define TXCFG_MXDMA8 0x00100000
175
176 #define CFG_LNKSTS 0x80000000
177 #define CFG_SPDSTS 0x60000000
178 #define CFG_SPDSTS1 0x40000000
179 #define CFG_SPDSTS0 0x20000000
180 #define CFG_DUPSTS 0x10000000
181 #define CFG_TBI_EN 0x01000000
182 #define CFG_MODE_1000 0x00400000
183 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
184 * Read the Phy response and then configure the MAC accordingly */
185 #define CFG_AUTO_1000 0x00200000
186 #define CFG_PINT_CTL 0x001c0000
187 #define CFG_PINT_DUPSTS 0x00100000
188 #define CFG_PINT_LNKSTS 0x00080000
189 #define CFG_PINT_SPDSTS 0x00040000
190 #define CFG_TMRTEST 0x00020000
191 #define CFG_MRM_DIS 0x00010000
192 #define CFG_MWI_DIS 0x00008000
193 #define CFG_T64ADDR 0x00004000
194 #define CFG_PCI64_DET 0x00002000
195 #define CFG_DATA64_EN 0x00001000
196 #define CFG_M64ADDR 0x00000800
197 #define CFG_PHY_RST 0x00000400
198 #define CFG_PHY_DIS 0x00000200
199 #define CFG_EXTSTS_EN 0x00000100
200 #define CFG_REQALG 0x00000080
201 #define CFG_SB 0x00000040
202 #define CFG_POW 0x00000020
203 #define CFG_EXD 0x00000010
204 #define CFG_PESEL 0x00000008
205 #define CFG_BROM_DIS 0x00000004
206 #define CFG_EXT_125 0x00000002
207 #define CFG_BEM 0x00000001
208
209 #define EXTSTS_UDPPKT 0x00200000
210 #define EXTSTS_TCPPKT 0x00080000
211 #define EXTSTS_IPPKT 0x00020000
212
213 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
214
215 #define MIBC_MIBS 0x00000008
216 #define MIBC_ACLR 0x00000004
217 #define MIBC_FRZ 0x00000002
218 #define MIBC_WRN 0x00000001
219
220 #define PCR_PSEN (1 << 31)
221 #define PCR_PS_MCAST (1 << 30)
222 #define PCR_PS_DA (1 << 29)
223 #define PCR_STHI_8 (3 << 23)
224 #define PCR_STLO_4 (1 << 23)
225 #define PCR_FFHI_8K (3 << 21)
226 #define PCR_FFLO_4K (1 << 21)
227 #define PCR_PAUSE_CNT 0xFFFE
228
229 #define RXCFG_AEP 0x80000000
230 #define RXCFG_ARP 0x40000000
231 #define RXCFG_STRIPCRC 0x20000000
232 #define RXCFG_RX_FD 0x10000000
233 #define RXCFG_ALP 0x08000000
234 #define RXCFG_AIRL 0x04000000
235 #define RXCFG_MXDMA512 0x00700000
236 #define RXCFG_DRTH 0x0000003e
237 #define RXCFG_DRTH0 0x00000002
238
239 #define RFCR_RFEN 0x80000000
240 #define RFCR_AAB 0x40000000
241 #define RFCR_AAM 0x20000000
242 #define RFCR_AAU 0x10000000
243 #define RFCR_APM 0x08000000
244 #define RFCR_APAT 0x07800000
245 #define RFCR_APAT3 0x04000000
246 #define RFCR_APAT2 0x02000000
247 #define RFCR_APAT1 0x01000000
248 #define RFCR_APAT0 0x00800000
249 #define RFCR_AARP 0x00400000
250 #define RFCR_MHEN 0x00200000
251 #define RFCR_UHEN 0x00100000
252 #define RFCR_ULM 0x00080000
253
254 #define VRCR_RUDPE 0x00000080
255 #define VRCR_RTCPE 0x00000040
256 #define VRCR_RIPE 0x00000020
257 #define VRCR_IPEN 0x00000010
258 #define VRCR_DUTF 0x00000008
259 #define VRCR_DVTF 0x00000004
260 #define VRCR_VTREN 0x00000002
261 #define VRCR_VTDEN 0x00000001
262
263 #define VTCR_PPCHK 0x00000008
264 #define VTCR_GCHK 0x00000004
265 #define VTCR_VPPTI 0x00000002
266 #define VTCR_VGTI 0x00000001
267
268 #define CR 0x00
269 #define CFG 0x04
270 #define MEAR 0x08
271 #define PTSCR 0x0c
272 #define ISR 0x10
273 #define IMR 0x14
274 #define IER 0x18
275 #define IHR 0x1c
276 #define TXDP 0x20
277 #define TXDP_HI 0x24
278 #define TXCFG 0x28
279 #define GPIOR 0x2c
280 #define RXDP 0x30
281 #define RXDP_HI 0x34
282 #define RXCFG 0x38
283 #define PQCR 0x3c
284 #define WCSR 0x40
285 #define PCR 0x44
286 #define RFCR 0x48
287 #define RFDR 0x4c
288
289 #define SRR 0x58
290
291 #define VRCR 0xbc
292 #define VTCR 0xc0
293 #define VDR 0xc4
294 #define CCSR 0xcc
295
296 #define TBICR 0xe0
297 #define TBISR 0xe4
298 #define TANAR 0xe8
299 #define TANLPAR 0xec
300 #define TANER 0xf0
301 #define TESR 0xf4
302
303 #define TBICR_MR_AN_ENABLE 0x00001000
304 #define TBICR_MR_RESTART_AN 0x00000200
305
306 #define TBISR_MR_LINK_STATUS 0x00000020
307 #define TBISR_MR_AN_COMPLETE 0x00000004
308
309 #define TANAR_PS2 0x00000100
310 #define TANAR_PS1 0x00000080
311 #define TANAR_HALF_DUP 0x00000040
312 #define TANAR_FULL_DUP 0x00000020
313
314 #define GPIOR_GP5_OE 0x00000200
315 #define GPIOR_GP4_OE 0x00000100
316 #define GPIOR_GP3_OE 0x00000080
317 #define GPIOR_GP2_OE 0x00000040
318 #define GPIOR_GP1_OE 0x00000020
319 #define GPIOR_GP3_OUT 0x00000004
320 #define GPIOR_GP1_OUT 0x00000001
321
322 #define LINK_AUTONEGOTIATE 0x01
323 #define LINK_DOWN 0x02
324 #define LINK_UP 0x04
325
326
327 #define __kick_rx() writel(CR_RXE, ns->base + CR)
328
329 #define kick_rx() do { \
330 dprintf(("kick_rx: maybe kicking\n")); \
331 writel(virt_to_le32desc(&rx_ring[ns->cur_rx]), ns->base + RXDP); \
332 if (ns->next_rx == ns->next_empty) \
333 printf("uh-oh: next_rx == next_empty???\n"); \
334 __kick_rx(); \
335 } while(0)
336
337
338 #ifdef USE_64BIT_ADDR
339 #define HW_ADDR_LEN 8
340 #else
341 #define HW_ADDR_LEN 4
342 #endif
343
344 #define CMDSTS_OWN 0x80000000
345 #define CMDSTS_MORE 0x40000000
346 #define CMDSTS_INTR 0x20000000
347 #define CMDSTS_ERR 0x10000000
348 #define CMDSTS_OK 0x08000000
349 #define CMDSTS_LEN_MASK 0x0000ffff
350
351 #define CMDSTS_DEST_MASK 0x01800000
352 #define CMDSTS_DEST_SELF 0x00800000
353 #define CMDSTS_DEST_MULTI 0x01000000
354
355 #define DESC_SIZE 8 /* Should be cache line sized */
356
357 #ifdef USE_64BIT_ADDR
358 struct ring_desc {
359 uint64_t link;
360 uint64_t bufptr;
361 u32 cmdsts;
362 u32 extsts; /* Extended status field */
363 };
364 #else
365 struct ring_desc {
366 u32 link;
367 u32 bufptr;
368 u32 cmdsts;
369 u32 extsts; /* Extended status field */
370 };
371 #endif
372
373 /* Define the TX Descriptor */
374 static struct ring_desc tx_ring[NR_TX_DESC]
375 __attribute__ ((aligned(8)));
376
377 /* Create a static buffer of size REAL_RX_BUF_SIZE for each
378 TX Descriptor. All descriptors point to a
379 part of this buffer */
380 static unsigned char txb[NR_TX_DESC * REAL_RX_BUF_SIZE];
381
382 /* Define the TX Descriptor */
383 static struct ring_desc rx_ring[NR_RX_DESC]
384 __attribute__ ((aligned(8)));
385
386 /* Create a static buffer of size REAL_RX_BUF_SIZE for each
387 RX Descriptor All descriptors point to a
388 part of this buffer */
389 static unsigned char rxb[NR_RX_DESC * REAL_RX_BUF_SIZE]
390 __attribute__ ((aligned(8)));
391
392 /* Private Storage for the NIC */
393 struct ns83820_private {
394 u8 *base;
395 int up;
396 long idle;
397 u32 *next_rx_desc;
398 u16 next_rx, next_empty;
399 u32 cur_rx;
400 u32 *descs;
401 unsigned ihr;
402 u32 CFG_cache;
403 u32 MEAR_cache;
404 u32 IMR_cache;
405 int linkstate;
406 u16 tx_done_idx;
407 u16 tx_idx;
408 u16 tx_intr_idx;
409 u32 phy_descs;
410 u32 *tx_descs;
411
412 } nsx;
413 static struct ns83820_private *ns;
414
phy_intr(struct nic * nic __unused)415 static void phy_intr(struct nic *nic __unused)
416 {
417 static char *speeds[] =
418 { "10", "100", "1000", "1000(?)", "1000F" };
419 u32 cfg, new_cfg;
420 u32 tbisr, tanar, tanlpar;
421 int speed, fullduplex, newlinkstate;
422
423 cfg = readl(ns->base + CFG) ^ SPDSTS_POLARITY;
424 if (ns->CFG_cache & CFG_TBI_EN) {
425 /* we have an optical transceiver */
426 tbisr = readl(ns->base + TBISR);
427 tanar = readl(ns->base + TANAR);
428 tanlpar = readl(ns->base + TANLPAR);
429 dprintf(("phy_intr: tbisr=%hX, tanar=%hX, tanlpar=%hX\n",
430 tbisr, tanar, tanlpar));
431
432 if ((fullduplex = (tanlpar & TANAR_FULL_DUP)
433 && (tanar & TANAR_FULL_DUP))) {
434
435 /* both of us are full duplex */
436 writel(readl(ns->base + TXCFG)
437 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
438 ns->base + TXCFG);
439 writel(readl(ns->base + RXCFG) | RXCFG_RX_FD,
440 ns->base + RXCFG);
441 /* Light up full duplex LED */
442 writel(readl(ns->base + GPIOR) | GPIOR_GP1_OUT,
443 ns->base + GPIOR);
444
445 } else if (((tanlpar & TANAR_HALF_DUP)
446 && (tanar & TANAR_HALF_DUP))
447 || ((tanlpar & TANAR_FULL_DUP)
448 && (tanar & TANAR_HALF_DUP))
449 || ((tanlpar & TANAR_HALF_DUP)
450 && (tanar & TANAR_FULL_DUP))) {
451
452 /* one or both of us are half duplex */
453 writel((readl(ns->base + TXCFG)
454 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
455 ns->base + TXCFG);
456 writel(readl(ns->base + RXCFG) & ~RXCFG_RX_FD,
457 ns->base + RXCFG);
458 /* Turn off full duplex LED */
459 writel(readl(ns->base + GPIOR) & ~GPIOR_GP1_OUT,
460 ns->base + GPIOR);
461 }
462
463 speed = 4; /* 1000F */
464
465 } else {
466 /* we have a copper transceiver */
467 new_cfg =
468 ns->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
469
470 if (cfg & CFG_SPDSTS1)
471 new_cfg |= CFG_MODE_1000;
472 else
473 new_cfg &= ~CFG_MODE_1000;
474
475 speed = ((cfg / CFG_SPDSTS0) & 3);
476 fullduplex = (cfg & CFG_DUPSTS);
477
478 if (fullduplex)
479 new_cfg |= CFG_SB;
480
481 if ((cfg & CFG_LNKSTS) &&
482 ((new_cfg ^ ns->CFG_cache) & CFG_MODE_1000)) {
483 writel(new_cfg, ns->base + CFG);
484 ns->CFG_cache = new_cfg;
485 }
486
487 ns->CFG_cache &= ~CFG_SPDSTS;
488 ns->CFG_cache |= cfg & CFG_SPDSTS;
489 }
490
491 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
492
493 if (newlinkstate & LINK_UP && ns->linkstate != newlinkstate) {
494 printf("link now %s mbps, %s duplex and up.\n",
495 speeds[speed], fullduplex ? "full" : "half");
496 } else if (newlinkstate & LINK_DOWN
497 && ns->linkstate != newlinkstate) {
498 printf("link now down.\n");
499 }
500 ns->linkstate = newlinkstate;
501 }
502 static void ns83820_set_multicast(struct nic *nic __unused);
ns83820_setup_rx(struct nic * nic)503 static void ns83820_setup_rx(struct nic *nic)
504 {
505 unsigned i;
506 ns->idle = 1;
507 ns->next_rx = 0;
508 ns->next_rx_desc = ns->descs;
509 ns->next_empty = 0;
510 ns->cur_rx = 0;
511
512
513 for (i = 0; i < NR_RX_DESC; i++) {
514 rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]);
515 rx_ring[i].bufptr =
516 virt_to_le32desc(&rxb[i * REAL_RX_BUF_SIZE]);
517 rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE);
518 rx_ring[i].extsts = cpu_to_le32(0);
519 }
520 // No need to wrap the ring
521 // rx_ring[i].link = virt_to_le32desc(&rx_ring[0]);
522 writel(0, ns->base + RXDP_HI);
523 writel(virt_to_le32desc(&rx_ring[0]), ns->base + RXDP);
524
525 dprintf(("starting receiver\n"));
526
527 writel(0x0001, ns->base + CCSR);
528 writel(0, ns->base + RFCR);
529 writel(0x7fc00000, ns->base + RFCR);
530 writel(0xffc00000, ns->base + RFCR);
531
532 ns->up = 1;
533
534 phy_intr(nic);
535
536 /* Okay, let it rip */
537 ns->IMR_cache |= ISR_PHY;
538 ns->IMR_cache |= ISR_RXRCMP;
539 //dev->IMR_cache |= ISR_RXERR;
540 //dev->IMR_cache |= ISR_RXOK;
541 ns->IMR_cache |= ISR_RXORN;
542 ns->IMR_cache |= ISR_RXSOVR;
543 ns->IMR_cache |= ISR_RXDESC;
544 ns->IMR_cache |= ISR_RXIDLE;
545 ns->IMR_cache |= ISR_TXDESC;
546 ns->IMR_cache |= ISR_TXIDLE;
547
548 // No reason to enable interupts...
549 // writel(ns->IMR_cache, ns->base + IMR);
550 // writel(1, ns->base + IER);
551 ns83820_set_multicast(nic);
552 kick_rx();
553 }
554
555
ns83820_do_reset(struct nic * nic __unused,u32 which)556 static void ns83820_do_reset(struct nic *nic __unused, u32 which)
557 {
558 dprintf(("resetting chip...\n"));
559 writel(which, ns->base + CR);
560 do {
561
562 } while (readl(ns->base + CR) & which);
563 dprintf(("okay!\n"));
564 }
565
ns83820_reset(struct nic * nic)566 static void ns83820_reset(struct nic *nic)
567 {
568 unsigned i;
569 dprintf(("ns83820_reset\n"));
570
571 writel(0, ns->base + PQCR);
572
573 ns83820_setup_rx(nic);
574
575 for (i = 0; i < NR_TX_DESC; i++) {
576 tx_ring[i].link = 0;
577 tx_ring[i].bufptr = 0;
578 tx_ring[i].cmdsts = cpu_to_le32(0);
579 tx_ring[i].extsts = cpu_to_le32(0);
580 }
581
582 ns->tx_idx = 0;
583 ns->tx_done_idx = 0;
584 writel(0, ns->base + TXDP_HI);
585 return;
586 }
ns83820_getmac(struct nic * nic __unused,u8 * mac)587 static void ns83820_getmac(struct nic *nic __unused, u8 * mac)
588 {
589 unsigned i;
590 for (i = 0; i < 3; i++) {
591 u32 data;
592 /* Read from the perfect match memory: this is loaded by
593 * the chip from the EEPROM via the EELOAD self test.
594 */
595 writel(i * 2, ns->base + RFCR);
596 data = readl(ns->base + RFDR);
597 *mac++ = data;
598 *mac++ = data >> 8;
599 }
600 }
601
ns83820_set_multicast(struct nic * nic __unused)602 static void ns83820_set_multicast(struct nic *nic __unused)
603 {
604 u8 *rfcr = ns->base + RFCR;
605 u32 and_mask = 0xffffffff;
606 u32 or_mask = 0;
607 u32 val;
608
609 /* Support Multicast */
610 and_mask &= ~(RFCR_AAU | RFCR_AAM);
611 or_mask |= RFCR_AAM;
612 val = (readl(rfcr) & and_mask) | or_mask;
613 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
614 writel(val & ~RFCR_RFEN, rfcr);
615 writel(val, rfcr);
616
617 }
ns83820_run_bist(struct nic * nic __unused,const char * name,u32 enable,u32 done,u32 fail)618 static void ns83820_run_bist(struct nic *nic __unused, const char *name,
619 u32 enable, u32 done, u32 fail)
620 {
621 int timed_out = 0;
622 long start;
623 u32 status;
624 int loops = 0;
625
626 dprintf(("start %s\n", name))
627
628 start = currticks();
629
630 writel(enable, ns->base + PTSCR);
631 for (;;) {
632 loops++;
633 status = readl(ns->base + PTSCR);
634 if (!(status & enable))
635 break;
636 if (status & done)
637 break;
638 if (status & fail)
639 break;
640 if ((currticks() - start) >= HZ) {
641 timed_out = 1;
642 break;
643 }
644 }
645
646 if (status & fail)
647 printf("%s failed! (0x%hX & 0x%hX)\n", name, status, fail);
648 else if (timed_out)
649 printf("run_bist %s timed out! (%hX)\n", name, status);
650 dprintf(("done %s in %d loops\n", name, loops));
651 }
652
653 /*************************************
654 Check Link
655 *************************************/
ns83820_check_intr(struct nic * nic)656 static void ns83820_check_intr(struct nic *nic) {
657 int i;
658 u32 isr = readl(ns->base + ISR);
659 if(ISR_PHY & isr)
660 phy_intr(nic);
661 if(( ISR_RXIDLE | ISR_RXDESC | ISR_RXERR) & isr)
662 kick_rx();
663 for (i = 0; i < NR_RX_DESC; i++) {
664 if (rx_ring[i].cmdsts == CMDSTS_OWN) {
665 // rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]);
666 rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE);
667 }
668 }
669 }
670 /**************************************************************************
671 POLL - Wait for a frame
672 ***************************************************************************/
ns83820_poll(struct nic * nic,int retrieve)673 static int ns83820_poll(struct nic *nic, int retrieve)
674 {
675 /* return true if there's an ethernet packet ready to read */
676 /* nic->packet should contain data on return */
677 /* nic->packetlen should contain length of data */
678 u32 cmdsts;
679 int entry = ns->cur_rx;
680
681 ns83820_check_intr(nic);
682
683 cmdsts = le32_to_cpu(rx_ring[entry].cmdsts);
684
685 if ( ! ( (CMDSTS_OWN & (cmdsts)) && (cmdsts != (CMDSTS_OWN)) ) )
686 return 0;
687
688 if ( ! retrieve ) return 1;
689
690 if (! (CMDSTS_OK & cmdsts) )
691 return 0;
692
693 nic->packetlen = cmdsts & 0xffff;
694 memcpy(nic->packet,
695 rxb + (entry * REAL_RX_BUF_SIZE),
696 nic->packetlen);
697 // rx_ring[entry].link = 0;
698 rx_ring[entry].cmdsts = cpu_to_le32(CMDSTS_OWN);
699
700 ns->cur_rx = ++ns->cur_rx % NR_RX_DESC;
701
702 if (ns->cur_rx == 0) /* We have wrapped the ring */
703 kick_rx();
704
705 return 1;
706 }
707
kick_tx(struct nic * nic __unused)708 static inline void kick_tx(struct nic *nic __unused)
709 {
710 dprintf(("kick_tx\n"));
711 writel(CR_TXE, ns->base + CR);
712 }
713
714 /**************************************************************************
715 TRANSMIT - Transmit a frame
716 ***************************************************************************/
ns83820_transmit(struct nic * nic,const char * d,unsigned int t,unsigned int s,const char * p)717 static void ns83820_transmit(struct nic *nic, const char *d, /* Destination */
718 unsigned int t, /* Type */
719 unsigned int s, /* size */
720 const char *p)
721 { /* Packet */
722 /* send the packet to destination */
723
724 u16 nstype;
725 u32 cmdsts, extsts;
726 int cur_tx = 0;
727 u32 isr = readl(ns->base + ISR);
728 if (ISR_TXIDLE & isr)
729 kick_tx(nic);
730 /* point to the current txb incase multiple tx_rings are used */
731 memcpy(txb, d, ETH_ALEN);
732 memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN);
733 nstype = htons((u16) t);
734 memcpy(txb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
735 memcpy(txb + ETH_HLEN, p, s);
736 s += ETH_HLEN;
737 s &= 0x0FFF;
738 while (s < ETH_ZLEN)
739 txb[s++] = '\0';
740
741 /* Setup the transmit descriptor */
742 extsts = 0;
743 extsts |= EXTSTS_UDPPKT;
744
745 tx_ring[cur_tx].bufptr = virt_to_le32desc(&txb);
746 tx_ring[cur_tx].extsts = cpu_to_le32(extsts);
747
748 cmdsts = cpu_to_le32(0);
749 cmdsts |= cpu_to_le32(CMDSTS_OWN | s);
750 tx_ring[cur_tx].cmdsts = cpu_to_le32(cmdsts);
751
752 writel(virt_to_le32desc(&tx_ring[0]), ns->base + TXDP);
753 kick_tx(nic);
754 }
755
756 /**************************************************************************
757 DISABLE - Turn off ethernet interface
758 ***************************************************************************/
ns83820_disable(struct dev * dev)759 static void ns83820_disable(struct dev *dev)
760 {
761 /* put the card in its initial state */
762 /* This function serves 3 purposes.
763 * This disables DMA and interrupts so we don't receive
764 * unexpected packets or interrupts from the card after
765 * etherboot has finished.
766 * This frees resources so etherboot may use
767 * this driver on another interface
768 * This allows etherboot to reinitialize the interface
769 * if something is something goes wrong.
770 */
771 /* disable interrupts */
772 writel(0, ns->base + IMR);
773 writel(0, ns->base + IER);
774 readl(ns->base + IER);
775
776 ns->up = 0;
777
778 ns83820_do_reset((struct nic *) dev, CR_RST);
779
780 ns->IMR_cache &=
781 ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY |
782 ISR_RXIDLE);
783 writel(ns->IMR_cache, ns->base + IMR);
784
785 /* touch the pci bus... */
786 readl(ns->base + IMR);
787
788 /* assumes the transmitter is already disabled and reset */
789 writel(0, ns->base + RXDP_HI);
790 writel(0, ns->base + RXDP);
791 }
792
793 /**************************************************************************
794 IRQ - Enable, Disable, or Force interrupts
795 ***************************************************************************/
ns83820_irq(struct nic * nic __unused,irq_action_t action __unused)796 static void ns83820_irq(struct nic *nic __unused, irq_action_t action __unused)
797 {
798 switch ( action ) {
799 case DISABLE :
800 break;
801 case ENABLE :
802 break;
803 case FORCE :
804 break;
805 }
806 }
807
808 /**************************************************************************
809 PROBE - Look for an adapter, this routine's visible to the outside
810 ***************************************************************************/
811
812 #define board_found 1
813 #define valid_link 0
ns83820_probe(struct dev * dev,struct pci_device * pci)814 static int ns83820_probe(struct dev *dev, struct pci_device *pci)
815 {
816 struct nic *nic = (struct nic *) dev;
817 int sz;
818 long addr;
819 int using_dac = 0;
820
821 if (pci->ioaddr == 0)
822 return 0;
823
824 printf("ns83820.c: Found %s, vendor=0x%hX, device=0x%hX\n",
825 pci->name, pci->vendor, pci->dev_id);
826
827 /* point to private storage */
828 ns = &nsx;
829
830 adjust_pci_device(pci);
831
832 addr = pci_bar_start(pci, PCI_BASE_ADDRESS_1);
833 sz = pci_bar_size(pci, PCI_BASE_ADDRESS_1);
834
835 ns->base = ioremap(addr, (1UL << 12));
836 // ns->base = ioremap(addr, sz);
837
838 if (!ns->base)
839 return 0;
840
841 nic->irqno = 0;
842 nic->ioaddr = pci->ioaddr & ~3;
843
844 /* disable interrupts */
845 writel(0, ns->base + IMR);
846 writel(0, ns->base + IER);
847 readl(ns->base + IER);
848
849 ns->IMR_cache = 0;
850
851 ns83820_do_reset(nic, CR_RST);
852
853 /* Must reset the ram bist before running it */
854 writel(PTSCR_RBIST_RST, ns->base + PTSCR);
855 ns83820_run_bist(nic, "sram bist", PTSCR_RBIST_EN,
856 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
857 ns83820_run_bist(nic, "eeprom bist", PTSCR_EEBIST_EN, 0,
858 PTSCR_EEBIST_FAIL);
859 ns83820_run_bist(nic, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
860
861 /* I love config registers */
862 ns->CFG_cache = readl(ns->base + CFG);
863
864 if ((ns->CFG_cache & CFG_PCI64_DET)) {
865 printf("%s: detected 64 bit PCI data bus.\n", pci->name);
866 /*dev->CFG_cache |= CFG_DATA64_EN; */
867 if (!(ns->CFG_cache & CFG_DATA64_EN))
868 printf
869 ("%s: EEPROM did not enable 64 bit bus. Disabled.\n",
870 pci->name);
871 } else
872 ns->CFG_cache &= ~(CFG_DATA64_EN);
873
874 ns->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
875 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
876 CFG_M64ADDR);
877 ns->CFG_cache |=
878 CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
879 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
880 ns->CFG_cache |= CFG_REQALG;
881 ns->CFG_cache |= CFG_POW;
882 ns->CFG_cache |= CFG_TMRTEST;
883
884 /* When compiled with 64 bit addressing, we must always enable
885 * the 64 bit descriptor format.
886 */
887 #ifdef USE_64BIT_ADDR
888 ns->CFG_cache |= CFG_M64ADDR;
889 #endif
890
891 //FIXME: Enable section on dac or remove this
892 if (using_dac)
893 ns->CFG_cache |= CFG_T64ADDR;
894
895 /* Big endian mode does not seem to do what the docs suggest */
896 ns->CFG_cache &= ~CFG_BEM;
897
898 /* setup optical transceiver if we have one */
899 if (ns->CFG_cache & CFG_TBI_EN) {
900 dprintf(("%s: enabling optical transceiver\n", pci->name));
901 writel(readl(ns->base + GPIOR) | 0x3e8, ns->base + GPIOR);
902
903 /* setup auto negotiation feature advertisement */
904 writel(readl(ns->base + TANAR)
905 | TANAR_HALF_DUP | TANAR_FULL_DUP,
906 ns->base + TANAR);
907
908 /* start auto negotiation */
909 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
910 ns->base + TBICR);
911 writel(TBICR_MR_AN_ENABLE, ns->base + TBICR);
912 ns->linkstate = LINK_AUTONEGOTIATE;
913
914 ns->CFG_cache |= CFG_MODE_1000;
915 }
916 writel(ns->CFG_cache, ns->base + CFG);
917 dprintf(("CFG: %hX\n", ns->CFG_cache));
918
919 /* FIXME: reset_phy is defaulted to 0, should we reset anyway? */
920 if (reset_phy) {
921 dprintf(("%s: resetting phy\n", pci->name));
922 writel(ns->CFG_cache | CFG_PHY_RST, ns->base + CFG);
923 writel(ns->CFG_cache, ns->base + CFG);
924 }
925 #if 0 /* Huh? This sets the PCI latency register. Should be done via
926 * the PCI layer. FIXME.
927 */
928 if (readl(dev->base + SRR))
929 writel(readl(dev->base + 0x20c) | 0xfe00,
930 dev->base + 0x20c);
931 #endif
932
933 /* Note! The DMA burst size interacts with packet
934 * transmission, such that the largest packet that
935 * can be transmitted is 8192 - FLTH - burst size.
936 * If only the transmit fifo was larger...
937 */
938 /* Ramit : 1024 DMA is not a good idea, it ends up banging
939 * some DELL and COMPAQ SMP systems */
940 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
941 | ((1600 / 32) * 0x100), ns->base + TXCFG);
942
943 /* Set Rx to full duplex, don't accept runt, errored, long or length
944 * range errored packets. Use 512 byte DMA.
945 */
946 /* Ramit : 1024 DMA is not a good idea, it ends up banging
947 * some DELL and COMPAQ SMP systems
948 * Turn on ALP, only we are accpeting Jumbo Packets */
949 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
950 | RXCFG_STRIPCRC
951 //| RXCFG_ALP
952 | (RXCFG_MXDMA512) | 0, ns->base + RXCFG);
953
954 /* Disable priority queueing */
955 writel(0, ns->base + PQCR);
956
957 /* Enable IP checksum validation and detetion of VLAN headers.
958 * Note: do not set the reject options as at least the 0x102
959 * revision of the chip does not properly accept IP fragments
960 * at least for UDP.
961 */
962 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
963 * the MAC it calculates the packetsize AFTER stripping the VLAN
964 * header, and if a VLAN Tagged packet of 64 bytes is received (like
965 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
966 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
967 * it discrards it!. These guys......
968 */
969 writel(VRCR_IPEN | VRCR_VTDEN, ns->base + VRCR);
970
971 /* Enable per-packet TCP/UDP/IP checksumming */
972 writel(VTCR_PPCHK, ns->base + VTCR);
973
974 /* Ramit : Enable async and sync pause frames */
975 // writel(0, ns->base + PCR);
976 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
977 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
978 ns->base + PCR);
979
980 /* Disable Wake On Lan */
981 writel(0, ns->base + WCSR);
982
983 ns83820_getmac(nic, nic->node_addr);
984 printf("%! at ioaddr 0x%hX, ", nic->node_addr, ns->base);
985
986 if (using_dac) {
987 dprintf(("%s: using 64 bit addressing.\n", pci->name));
988 }
989
990 dprintf(("%s: DP83820 %d.%d: %! io=0x%hX\n",
991 pci->name,
992 (unsigned) readl(ns->base + SRR) >> 8,
993 (unsigned) readl(ns->base + SRR) & 0xff,
994 nic->node_addr, pci->ioaddr));
995
996 #ifdef PHY_CODE_IS_FINISHED
997 ns83820_probe_phy(dev);
998 #endif
999
1000 ns83820_reset(nic);
1001 /* point to NIC specific routines */
1002 dev->disable = ns83820_disable;
1003 nic->poll = ns83820_poll;
1004 nic->transmit = ns83820_transmit;
1005 nic->irq = ns83820_irq;
1006 return 1;
1007 }
1008
1009 static struct pci_id ns83820_nics[] = {
1010 PCI_ROM(0x100b, 0x0022, "ns83820", "National Semiconductor 83820"),
1011 };
1012
1013 struct pci_driver ns83820_driver = {
1014 .type = NIC_DRIVER,
1015 .name = "NS83820/PCI",
1016 .probe = ns83820_probe,
1017 .ids = ns83820_nics,
1018 .id_count = sizeof(ns83820_nics) / sizeof(ns83820_nics[0]),
1019 .class = 0,
1020 };
1021