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Searched refs:ISR (Results 1 – 9 of 9) sorted by relevance

/illumos-gate/usr/src/uts/i86pc/boot/
H A Dboot_serial.h36 #define ISR 2 /* ... intr status reg */ macro
43 #define FIFOR ISR /* ... fifo write reg */
H A Dboot_console.c138 outb(port + ISR, 0x20); in serial_init()
139 if (inb(port + ISR) & 0x20) { in serial_init()
144 outb(port + ISR, 0x40); /* set to bank 2 */ in serial_init()
147 outb(port + ISR, 0x00); /* set to bank 0 */ in serial_init()
160 if ((inb(port + ISR) & 0xc0) != 0xc0) { in serial_init()
/illumos-gate/usr/src/uts/sun4/sys/
H A Dsudev.h52 #define ISR 2 /* interrupt status register */ macro
60 #define FIFOR ISR /* FIFO register for 16550 */
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A Dns83820.c272 #define ISR 0x10 macro
658 u32 isr = readl(ns->base + ISR); in ns83820_check_intr()
727 u32 isr = readl(ns->base + ISR); in ns83820_transmit()
/illumos-gate/usr/src/uts/common/io/sfe/
H A Dsfereg.h125 #define ISR 0x10 /* Interrupt status register */ macro
H A Dsfe.c461 lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits; in sfe_reset_chip_sis900()
474 done |= INL(dp, ISR) & (ISR_TXRCMP | ISR_RXRCMP); in sfe_reset_chip_sis900()
515 lp->isr_pended |= INL(dp, ISR) & lp->our_intr_bits; in sfe_reset_chip_dp83815()
869 val = INL(dp, ISR); in sfe_stop_chip()
909 val = INL(dp, ISR); in sfe_stop_chip_quiesce()
1476 isr = INL(dp, ISR); in sfe_interrupt()
/illumos-gate/usr/src/uts/sun4/io/
H A Dsu_driver.c369 if (ddi_get8(handle, addr+ISR) & 0x30) { in asyprobe()
579 OUTB(ISR, 0x20); in asyattach()
580 if (INB(ISR) & 0x20) { /* 82510 chip is present */ in asyattach()
588 OUTB(ISR, 0x40); /* set to bank 2 */ in asyattach()
591 OUTB(ISR, 0x00); /* set to bank 0 */ in asyattach()
602 if ((INB(ISR) & 0xc0) == 0xc0) in asyattach()
1419 (void) INB(ISR); in asy_program()
1639 interrupt_id = INB(ISR) & 0x0F; in asyintr()
1699 OUTB(ISR, 0x00); /* set bank 0 */ in asyintr()
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/documentation/
H A Dosal.txt193 layer to the slowpath interrupt ISR [either directly or indirectly], and that
H A Decore.tex511 …elease} – this function performs the required IRQ related cleanup post the ISR release. The functi…
589 When working in INTA / MSI we work in single-ISR multiple-DPC mode; The same interrupt line can sig…
616 \item OS is triggered, calling the driver's Interrupt Service Routine [ISR].
1639 …\item PF driver's ISR wakes. It recognizes the message and calls OSAL\_PF\_VF\_MSG to notify upper…