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Searched refs:IEEE1394_CSR_OFFSET_MASK (Results 1 – 5 of 5) sorted by relevance

/illumos-gate/usr/src/uts/common/io/1394/
H A Ds1394_isoch.c323 (IEEE1394_SCSR_CHANS_AVAIL_HI & IEEE1394_CSR_OFFSET_MASK); in s1394_channel_alloc()
326 (IEEE1394_SCSR_CHANS_AVAIL_LO & IEEE1394_CSR_OFFSET_MASK); in s1394_channel_alloc()
478 (IEEE1394_SCSR_CHANS_AVAIL_HI & IEEE1394_CSR_OFFSET_MASK); in s1394_channel_free()
481 (IEEE1394_SCSR_CHANS_AVAIL_LO & IEEE1394_CSR_OFFSET_MASK); in s1394_channel_free()
629 IEEE1394_CSR_OFFSET_MASK), &old_value); in s1394_bandwidth_alloc()
652 IEEE1394_CSR_OFFSET_MASK), compare, swap, in s1394_bandwidth_alloc()
806 IEEE1394_CSR_OFFSET_MASK), &old_value); in s1394_bandwidth_free()
827 IEEE1394_CSR_OFFSET_MASK), compare, swap, in s1394_bandwidth_free()
H A Ds1394_csr.c455 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_state_clear()
561 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_state_set()
663 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_reset_start()
738 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_test_regs()
741 if ((offset == (IEEE1394_CSR_TEST_STATUS & IEEE1394_CSR_OFFSET_MASK)) && in s1394_CSR_test_regs()
810 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_cycle_time()
887 offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK; in s1394_CSR_bus_time()
996 offset = (req->cmd_addr & IEEE1394_CSR_OFFSET_MASK); in s1394_CSR_IRM_regs()
1170 offset = (req->cmd_addr & IEEE1394_CSR_OFFSET_MASK); in s1394_common_CSR_routine()
H A Ds1394_misc.c867 offset = (IEEE1394_CSR_STATE_SET & IEEE1394_CSR_OFFSET_MASK); in s1394_cycle_too_long_callback()
H A Ds1394_dev_disc.c1852 IEEE1394_CSR_OFFSET_MASK), S1394_INVALID_NODE_NUM, in s1394_become_bus_mgr()
/illumos-gate/usr/src/uts/common/sys/1394/
H A Dieee1394.h250 #define IEEE1394_CSR_OFFSET_MASK 0x00000000FFFF macro