xref: /illumos-gate/usr/src/uts/common/io/sfxge/common/efx_regs.h (revision 49ef7e0638c8b771d8a136eae78b1c0f99acc8e0)
1 /*
2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  *    this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright notice,
11  *    this list of conditions and the following disclaimer in the documentation
12  *    and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * The views and conclusions contained in the software and documentation are
27  * those of the authors and should not be interpreted as representing official
28  * policies, either expressed or implied, of the FreeBSD Project.
29  */
30 
31 #ifndef	_SYS_EFX_REGS_H
32 #define	_SYS_EFX_REGS_H
33 
34 
35 #ifdef	__cplusplus
36 extern "C" {
37 #endif
38 
39 
40 /**************************************************************************
41  *
42  * Falcon/Siena registers and descriptors
43  *
44  **************************************************************************
45  */
46 
47 /*
48  * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
49  * SPI/VPD configuration register 0
50  */
51 #define	FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300
52 /* falcona0,falconb0=eeprom_flash */
53 /*
54  * FR_AB_EE_VPD_CFG0_REG(128bit):
55  * SPI/VPD configuration register 0
56  */
57 #define	FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140
58 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
59 
60 #define	FRF_AB_EE_SF_FASTRD_EN_LBN 127
61 #define	FRF_AB_EE_SF_FASTRD_EN_WIDTH 1
62 #define	FRF_AB_EE_SF_CLOCK_DIV_LBN 120
63 #define	FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7
64 #define	FRF_AB_EE_VPD_WIP_POLL_LBN 119
65 #define	FRF_AB_EE_VPD_WIP_POLL_WIDTH 1
66 #define	FRF_AB_EE_EE_CLOCK_DIV_LBN 112
67 #define	FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7
68 #define	FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96
69 #define	FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16
70 #define	FRF_AB_EE_VPDW_LENGTH_LBN 80
71 #define	FRF_AB_EE_VPDW_LENGTH_WIDTH 15
72 #define	FRF_AB_EE_VPDW_BASE_LBN 64
73 #define	FRF_AB_EE_VPDW_BASE_WIDTH 15
74 #define	FRF_AB_EE_VPD_WR_CMD_EN_LBN 56
75 #define	FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8
76 #define	FRF_AB_EE_VPD_BASE_LBN 32
77 #define	FRF_AB_EE_VPD_BASE_WIDTH 24
78 #define	FRF_AB_EE_VPD_LENGTH_LBN 16
79 #define	FRF_AB_EE_VPD_LENGTH_WIDTH 15
80 #define	FRF_AB_EE_VPD_AD_SIZE_LBN 8
81 #define	FRF_AB_EE_VPD_AD_SIZE_WIDTH 5
82 #define	FRF_AB_EE_VPD_ACCESS_ON_LBN 5
83 #define	FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1
84 #define	FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4
85 #define	FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1
86 #define	FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2
87 #define	FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1
88 #define	FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1
89 #define	FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1
90 #define	FRF_AB_EE_VPD_EN_LBN 0
91 #define	FRF_AB_EE_VPD_EN_WIDTH 1
92 
93 
94 /*
95  * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
96  * PCIE SerDes control register 0 to 3
97  */
98 #define	FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320
99 /* falcona0,falconb0=eeprom_flash */
100 /*
101  * FR_AB_PCIE_SD_CTL0123_REG(128bit):
102  * PCIE SerDes control register 0 to 3
103  */
104 #define	FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320
105 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
106 
107 #define	FRF_AB_PCIE_TESTSIG_H_LBN 96
108 #define	FRF_AB_PCIE_TESTSIG_H_WIDTH 19
109 #define	FRF_AB_PCIE_TESTSIG_L_LBN 64
110 #define	FRF_AB_PCIE_TESTSIG_L_WIDTH 19
111 #define	FRF_AB_PCIE_OFFSET_LBN 56
112 #define	FRF_AB_PCIE_OFFSET_WIDTH 8
113 #define	FRF_AB_PCIE_OFFSETEN_H_LBN 55
114 #define	FRF_AB_PCIE_OFFSETEN_H_WIDTH 1
115 #define	FRF_AB_PCIE_OFFSETEN_L_LBN 54
116 #define	FRF_AB_PCIE_OFFSETEN_L_WIDTH 1
117 #define	FRF_AB_PCIE_HIVMODE_H_LBN 53
118 #define	FRF_AB_PCIE_HIVMODE_H_WIDTH 1
119 #define	FRF_AB_PCIE_HIVMODE_L_LBN 52
120 #define	FRF_AB_PCIE_HIVMODE_L_WIDTH 1
121 #define	FRF_AB_PCIE_PARRESET_H_LBN 51
122 #define	FRF_AB_PCIE_PARRESET_H_WIDTH 1
123 #define	FRF_AB_PCIE_PARRESET_L_LBN 50
124 #define	FRF_AB_PCIE_PARRESET_L_WIDTH 1
125 #define	FRF_AB_PCIE_LPBKWDRV_H_LBN 49
126 #define	FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1
127 #define	FRF_AB_PCIE_LPBKWDRV_L_LBN 48
128 #define	FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1
129 #define	FRF_AB_PCIE_LPBK_LBN 40
130 #define	FRF_AB_PCIE_LPBK_WIDTH 8
131 #define	FRF_AB_PCIE_PARLPBK_LBN 32
132 #define	FRF_AB_PCIE_PARLPBK_WIDTH 8
133 #define	FRF_AB_PCIE_RXTERMADJ_H_LBN 30
134 #define	FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2
135 #define	FRF_AB_PCIE_RXTERMADJ_L_LBN 28
136 #define	FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2
137 #define	FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3
138 #define	FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2
139 #define	FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1
140 #define	FFE_AB_PCIE_RXTERMADJ_NOMNL 0
141 #define	FRF_AB_PCIE_TXTERMADJ_H_LBN 26
142 #define	FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2
143 #define	FRF_AB_PCIE_TXTERMADJ_L_LBN 24
144 #define	FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2
145 #define	FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3
146 #define	FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2
147 #define	FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1
148 #define	FFE_AB_PCIE_TXTERMADJ_NOMNL 0
149 #define	FRF_AB_PCIE_RXEQCTL_H_LBN 18
150 #define	FRF_AB_PCIE_RXEQCTL_H_WIDTH 2
151 #define	FRF_AB_PCIE_RXEQCTL_L_LBN 16
152 #define	FRF_AB_PCIE_RXEQCTL_L_WIDTH 2
153 #define	FFE_AB_PCIE_RXEQCTL_OFF_ALT 3
154 #define	FFE_AB_PCIE_RXEQCTL_OFF 2
155 #define	FFE_AB_PCIE_RXEQCTL_MIN 1
156 #define	FFE_AB_PCIE_RXEQCTL_MAX 0
157 #define	FRF_AB_PCIE_HIDRV_LBN 8
158 #define	FRF_AB_PCIE_HIDRV_WIDTH 8
159 #define	FRF_AB_PCIE_LODRV_LBN 0
160 #define	FRF_AB_PCIE_LODRV_WIDTH 8
161 
162 
163 /*
164  * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
165  * PCIE SerDes control register 4 and 5
166  */
167 #define	FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330
168 /* falcona0,falconb0=eeprom_flash */
169 /*
170  * FR_AB_PCIE_SD_CTL45_REG(128bit):
171  * PCIE SerDes control register 4 and 5
172  */
173 #define	FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330
174 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
175 
176 #define	FRF_AB_PCIE_DTX7_LBN 60
177 #define	FRF_AB_PCIE_DTX7_WIDTH 4
178 #define	FRF_AB_PCIE_DTX6_LBN 56
179 #define	FRF_AB_PCIE_DTX6_WIDTH 4
180 #define	FRF_AB_PCIE_DTX5_LBN 52
181 #define	FRF_AB_PCIE_DTX5_WIDTH 4
182 #define	FRF_AB_PCIE_DTX4_LBN 48
183 #define	FRF_AB_PCIE_DTX4_WIDTH 4
184 #define	FRF_AB_PCIE_DTX3_LBN 44
185 #define	FRF_AB_PCIE_DTX3_WIDTH 4
186 #define	FRF_AB_PCIE_DTX2_LBN 40
187 #define	FRF_AB_PCIE_DTX2_WIDTH 4
188 #define	FRF_AB_PCIE_DTX1_LBN 36
189 #define	FRF_AB_PCIE_DTX1_WIDTH 4
190 #define	FRF_AB_PCIE_DTX0_LBN 32
191 #define	FRF_AB_PCIE_DTX0_WIDTH 4
192 #define	FRF_AB_PCIE_DEQ7_LBN 28
193 #define	FRF_AB_PCIE_DEQ7_WIDTH 4
194 #define	FRF_AB_PCIE_DEQ6_LBN 24
195 #define	FRF_AB_PCIE_DEQ6_WIDTH 4
196 #define	FRF_AB_PCIE_DEQ5_LBN 20
197 #define	FRF_AB_PCIE_DEQ5_WIDTH 4
198 #define	FRF_AB_PCIE_DEQ4_LBN 16
199 #define	FRF_AB_PCIE_DEQ4_WIDTH 4
200 #define	FRF_AB_PCIE_DEQ3_LBN 12
201 #define	FRF_AB_PCIE_DEQ3_WIDTH 4
202 #define	FRF_AB_PCIE_DEQ2_LBN 8
203 #define	FRF_AB_PCIE_DEQ2_WIDTH 4
204 #define	FRF_AB_PCIE_DEQ1_LBN 4
205 #define	FRF_AB_PCIE_DEQ1_WIDTH 4
206 #define	FRF_AB_PCIE_DEQ0_LBN 0
207 #define	FRF_AB_PCIE_DEQ0_WIDTH 4
208 
209 
210 /*
211  * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit):
212  * PCIE PCS control and status register
213  */
214 #define	FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340
215 /* falcona0,falconb0=eeprom_flash */
216 /*
217  * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):
218  * PCIE PCS control and status register
219  */
220 #define	FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340
221 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
222 
223 #define	FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52
224 #define	FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4
225 #define	FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48
226 #define	FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4
227 #define	FRF_AB_PCIE_PRBSERR_LBN 40
228 #define	FRF_AB_PCIE_PRBSERR_WIDTH 8
229 #define	FRF_AB_PCIE_PRBSERRH0_LBN 32
230 #define	FRF_AB_PCIE_PRBSERRH0_WIDTH 8
231 #define	FRF_AB_PCIE_FASTINIT_H_LBN 15
232 #define	FRF_AB_PCIE_FASTINIT_H_WIDTH 1
233 #define	FRF_AB_PCIE_FASTINIT_L_LBN 14
234 #define	FRF_AB_PCIE_FASTINIT_L_WIDTH 1
235 #define	FRF_AB_PCIE_CTCDISABLE_H_LBN 13
236 #define	FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1
237 #define	FRF_AB_PCIE_CTCDISABLE_L_LBN 12
238 #define	FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1
239 #define	FRF_AB_PCIE_PRBSSYNC_H_LBN 11
240 #define	FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1
241 #define	FRF_AB_PCIE_PRBSSYNC_L_LBN 10
242 #define	FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1
243 #define	FRF_AB_PCIE_PRBSERRACK_H_LBN 9
244 #define	FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1
245 #define	FRF_AB_PCIE_PRBSERRACK_L_LBN 8
246 #define	FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1
247 #define	FRF_AB_PCIE_PRBSSEL_LBN 0
248 #define	FRF_AB_PCIE_PRBSSEL_WIDTH 8
249 
250 
251 /*
252  * FR_AB_HW_INIT_REG_SF(128bit):
253  * Hardware initialization register
254  */
255 #define	FR_AB_HW_INIT_REG_SF_OFST 0x00000350
256 /* falcona0,falconb0=eeprom_flash */
257 /*
258  * FR_AZ_HW_INIT_REG(128bit):
259  * Hardware initialization register
260  */
261 #define	FR_AZ_HW_INIT_REG_OFST 0x000000c0
262 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
263 
264 #define	FRF_BB_BDMRD_CPLF_FULL_LBN 124
265 #define	FRF_BB_BDMRD_CPLF_FULL_WIDTH 1
266 #define	FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121
267 #define	FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3
268 #define	FRF_CZ_TX_MRG_TAGS_LBN 120
269 #define	FRF_CZ_TX_MRG_TAGS_WIDTH 1
270 #define	FRF_AZ_TRGT_MASK_ALL_LBN 100
271 #define	FRF_AZ_TRGT_MASK_ALL_WIDTH 1
272 #define	FRF_AZ_DOORBELL_DROP_LBN 92
273 #define	FRF_AZ_DOORBELL_DROP_WIDTH 8
274 #define	FRF_AB_TX_RREQ_MASK_EN_LBN 76
275 #define	FRF_AB_TX_RREQ_MASK_EN_WIDTH 1
276 #define	FRF_AB_PE_EIDLE_DIS_LBN 75
277 #define	FRF_AB_PE_EIDLE_DIS_WIDTH 1
278 #define	FRF_AZ_FC_BLOCKING_EN_LBN 45
279 #define	FRF_AZ_FC_BLOCKING_EN_WIDTH 1
280 #define	FRF_AZ_B2B_REQ_EN_LBN 44
281 #define	FRF_AZ_B2B_REQ_EN_WIDTH 1
282 #define	FRF_AZ_POST_WR_MASK_LBN 40
283 #define	FRF_AZ_POST_WR_MASK_WIDTH 4
284 #define	FRF_AZ_TLP_TC_LBN 34
285 #define	FRF_AZ_TLP_TC_WIDTH 3
286 #define	FRF_AZ_TLP_ATTR_LBN 32
287 #define	FRF_AZ_TLP_ATTR_WIDTH 2
288 #define	FRF_AB_INTB_VEC_LBN 24
289 #define	FRF_AB_INTB_VEC_WIDTH 5
290 #define	FRF_AB_INTA_VEC_LBN 16
291 #define	FRF_AB_INTA_VEC_WIDTH 5
292 #define	FRF_AZ_WD_TIMER_LBN 8
293 #define	FRF_AZ_WD_TIMER_WIDTH 8
294 #define	FRF_AZ_US_DISABLE_LBN 5
295 #define	FRF_AZ_US_DISABLE_WIDTH 1
296 #define	FRF_AZ_TLP_EP_LBN 4
297 #define	FRF_AZ_TLP_EP_WIDTH 1
298 #define	FRF_AZ_ATTR_SEL_LBN 3
299 #define	FRF_AZ_ATTR_SEL_WIDTH 1
300 #define	FRF_AZ_TD_SEL_LBN 1
301 #define	FRF_AZ_TD_SEL_WIDTH 1
302 #define	FRF_AZ_TLP_TD_LBN 0
303 #define	FRF_AZ_TLP_TD_WIDTH 1
304 
305 
306 /*
307  * FR_AB_NIC_STAT_REG_SF(128bit):
308  * NIC status register
309  */
310 #define	FR_AB_NIC_STAT_REG_SF_OFST 0x00000360
311 /* falcona0,falconb0=eeprom_flash */
312 /*
313  * FR_AB_NIC_STAT_REG(128bit):
314  * NIC status register
315  */
316 #define	FR_AB_NIC_STAT_REG_OFST 0x00000200
317 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
318 
319 #define	FRF_BB_AER_DIS_LBN 34
320 #define	FRF_BB_AER_DIS_WIDTH 1
321 #define	FRF_BB_EE_STRAP_EN_LBN 31
322 #define	FRF_BB_EE_STRAP_EN_WIDTH 1
323 #define	FRF_BB_EE_STRAP_LBN 24
324 #define	FRF_BB_EE_STRAP_WIDTH 4
325 #define	FRF_BB_REVISION_ID_LBN 17
326 #define	FRF_BB_REVISION_ID_WIDTH 7
327 #define	FRF_AB_ONCHIP_SRAM_LBN 16
328 #define	FRF_AB_ONCHIP_SRAM_WIDTH 1
329 #define	FRF_AB_SF_PRST_LBN 9
330 #define	FRF_AB_SF_PRST_WIDTH 1
331 #define	FRF_AB_EE_PRST_LBN 8
332 #define	FRF_AB_EE_PRST_WIDTH 1
333 #define	FRF_AB_ATE_MODE_LBN 3
334 #define	FRF_AB_ATE_MODE_WIDTH 1
335 #define	FRF_AB_STRAP_PINS_LBN 0
336 #define	FRF_AB_STRAP_PINS_WIDTH 3
337 
338 
339 /*
340  * FR_AB_GLB_CTL_REG_SF(128bit):
341  * Global control register
342  */
343 #define	FR_AB_GLB_CTL_REG_SF_OFST 0x00000370
344 /* falcona0,falconb0=eeprom_flash */
345 /*
346  * FR_AB_GLB_CTL_REG(128bit):
347  * Global control register
348  */
349 #define	FR_AB_GLB_CTL_REG_OFST 0x00000220
350 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
351 
352 #define	FRF_AB_EXT_PHY_RST_CTL_LBN 63
353 #define	FRF_AB_EXT_PHY_RST_CTL_WIDTH 1
354 #define	FRF_AB_XAUI_SD_RST_CTL_LBN 62
355 #define	FRF_AB_XAUI_SD_RST_CTL_WIDTH 1
356 #define	FRF_AB_PCIE_SD_RST_CTL_LBN 61
357 #define	FRF_AB_PCIE_SD_RST_CTL_WIDTH 1
358 #define	FRF_AA_PCIX_RST_CTL_LBN 60
359 #define	FRF_AA_PCIX_RST_CTL_WIDTH 1
360 #define	FRF_BB_BIU_RST_CTL_LBN 60
361 #define	FRF_BB_BIU_RST_CTL_WIDTH 1
362 #define	FRF_AB_PCIE_STKY_RST_CTL_LBN 59
363 #define	FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1
364 #define	FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58
365 #define	FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1
366 #define	FRF_AB_PCIE_CORE_RST_CTL_LBN 57
367 #define	FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1
368 #define	FRF_AB_XGRX_RST_CTL_LBN 56
369 #define	FRF_AB_XGRX_RST_CTL_WIDTH 1
370 #define	FRF_AB_XGTX_RST_CTL_LBN 55
371 #define	FRF_AB_XGTX_RST_CTL_WIDTH 1
372 #define	FRF_AB_EM_RST_CTL_LBN 54
373 #define	FRF_AB_EM_RST_CTL_WIDTH 1
374 #define	FRF_AB_EV_RST_CTL_LBN 53
375 #define	FRF_AB_EV_RST_CTL_WIDTH 1
376 #define	FRF_AB_SR_RST_CTL_LBN 52
377 #define	FRF_AB_SR_RST_CTL_WIDTH 1
378 #define	FRF_AB_RX_RST_CTL_LBN 51
379 #define	FRF_AB_RX_RST_CTL_WIDTH 1
380 #define	FRF_AB_TX_RST_CTL_LBN 50
381 #define	FRF_AB_TX_RST_CTL_WIDTH 1
382 #define	FRF_AB_EE_RST_CTL_LBN 49
383 #define	FRF_AB_EE_RST_CTL_WIDTH 1
384 #define	FRF_AB_CS_RST_CTL_LBN 48
385 #define	FRF_AB_CS_RST_CTL_WIDTH 1
386 #define	FRF_AB_HOT_RST_CTL_LBN 40
387 #define	FRF_AB_HOT_RST_CTL_WIDTH 2
388 #define	FRF_AB_RST_EXT_PHY_LBN 31
389 #define	FRF_AB_RST_EXT_PHY_WIDTH 1
390 #define	FRF_AB_RST_XAUI_SD_LBN 30
391 #define	FRF_AB_RST_XAUI_SD_WIDTH 1
392 #define	FRF_AB_RST_PCIE_SD_LBN 29
393 #define	FRF_AB_RST_PCIE_SD_WIDTH 1
394 #define	FRF_AA_RST_PCIX_LBN 28
395 #define	FRF_AA_RST_PCIX_WIDTH 1
396 #define	FRF_BB_RST_BIU_LBN 28
397 #define	FRF_BB_RST_BIU_WIDTH 1
398 #define	FRF_AB_RST_PCIE_STKY_LBN 27
399 #define	FRF_AB_RST_PCIE_STKY_WIDTH 1
400 #define	FRF_AB_RST_PCIE_NSTKY_LBN 26
401 #define	FRF_AB_RST_PCIE_NSTKY_WIDTH 1
402 #define	FRF_AB_RST_PCIE_CORE_LBN 25
403 #define	FRF_AB_RST_PCIE_CORE_WIDTH 1
404 #define	FRF_AB_RST_XGRX_LBN 24
405 #define	FRF_AB_RST_XGRX_WIDTH 1
406 #define	FRF_AB_RST_XGTX_LBN 23
407 #define	FRF_AB_RST_XGTX_WIDTH 1
408 #define	FRF_AB_RST_EM_LBN 22
409 #define	FRF_AB_RST_EM_WIDTH 1
410 #define	FRF_AB_RST_EV_LBN 21
411 #define	FRF_AB_RST_EV_WIDTH 1
412 #define	FRF_AB_RST_SR_LBN 20
413 #define	FRF_AB_RST_SR_WIDTH 1
414 #define	FRF_AB_RST_RX_LBN 19
415 #define	FRF_AB_RST_RX_WIDTH 1
416 #define	FRF_AB_RST_TX_LBN 18
417 #define	FRF_AB_RST_TX_WIDTH 1
418 #define	FRF_AB_RST_SF_LBN 17
419 #define	FRF_AB_RST_SF_WIDTH 1
420 #define	FRF_AB_RST_CS_LBN 16
421 #define	FRF_AB_RST_CS_WIDTH 1
422 #define	FRF_AB_INT_RST_DUR_LBN 4
423 #define	FRF_AB_INT_RST_DUR_WIDTH 3
424 #define	FRF_AB_EXT_PHY_RST_DUR_LBN 1
425 #define	FRF_AB_EXT_PHY_RST_DUR_WIDTH 3
426 #define	FFE_AB_EXT_PHY_RST_DUR_10240US 7
427 #define	FFE_AB_EXT_PHY_RST_DUR_5120US 6
428 #define	FFE_AB_EXT_PHY_RST_DUR_2560US 5
429 #define	FFE_AB_EXT_PHY_RST_DUR_1280US 4
430 #define	FFE_AB_EXT_PHY_RST_DUR_640US 3
431 #define	FFE_AB_EXT_PHY_RST_DUR_320US 2
432 #define	FFE_AB_EXT_PHY_RST_DUR_160US 1
433 #define	FFE_AB_EXT_PHY_RST_DUR_80US 0
434 #define	FRF_AB_SWRST_LBN 0
435 #define	FRF_AB_SWRST_WIDTH 1
436 
437 
438 /*
439  * FR_AZ_IOM_IND_ADR_REG(32bit):
440  * IO-mapped indirect access address register
441  */
442 #define	FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000
443 /* falcona0,falconb0,sienaa0=net_func_bar0 */
444 
445 #define	FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24
446 #define	FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1
447 #define	FRF_AZ_IOM_IND_ADR_LBN 0
448 #define	FRF_AZ_IOM_IND_ADR_WIDTH 24
449 
450 
451 /*
452  * FR_AZ_IOM_IND_DAT_REG(32bit):
453  * IO-mapped indirect access data register
454  */
455 #define	FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004
456 /* falcona0,falconb0,sienaa0=net_func_bar0 */
457 
458 #define	FRF_AZ_IOM_IND_DAT_LBN 0
459 #define	FRF_AZ_IOM_IND_DAT_WIDTH 32
460 
461 
462 /*
463  * FR_AZ_ADR_REGION_REG(128bit):
464  * Address region register
465  */
466 #define	FR_AZ_ADR_REGION_REG_OFST 0x00000000
467 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
468 
469 #define	FRF_AZ_ADR_REGION3_LBN 96
470 #define	FRF_AZ_ADR_REGION3_WIDTH 18
471 #define	FRF_AZ_ADR_REGION2_LBN 64
472 #define	FRF_AZ_ADR_REGION2_WIDTH 18
473 #define	FRF_AZ_ADR_REGION1_LBN 32
474 #define	FRF_AZ_ADR_REGION1_WIDTH 18
475 #define	FRF_AZ_ADR_REGION0_LBN 0
476 #define	FRF_AZ_ADR_REGION0_WIDTH 18
477 
478 
479 /*
480  * FR_AZ_INT_EN_REG_KER(128bit):
481  * Kernel driver Interrupt enable register
482  */
483 #define	FR_AZ_INT_EN_REG_KER_OFST 0x00000010
484 /* falcona0,falconb0,sienaa0=net_func_bar2 */
485 
486 #define	FRF_AZ_KER_INT_LEVE_SEL_LBN 8
487 #define	FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6
488 #define	FRF_AZ_KER_INT_CHAR_LBN 4
489 #define	FRF_AZ_KER_INT_CHAR_WIDTH 1
490 #define	FRF_AZ_KER_INT_KER_LBN 3
491 #define	FRF_AZ_KER_INT_KER_WIDTH 1
492 #define	FRF_AZ_DRV_INT_EN_KER_LBN 0
493 #define	FRF_AZ_DRV_INT_EN_KER_WIDTH 1
494 
495 
496 /*
497  * FR_AZ_INT_EN_REG_CHAR(128bit):
498  * Char Driver interrupt enable register
499  */
500 #define	FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020
501 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
502 
503 #define	FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8
504 #define	FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6
505 #define	FRF_AZ_CHAR_INT_CHAR_LBN 4
506 #define	FRF_AZ_CHAR_INT_CHAR_WIDTH 1
507 #define	FRF_AZ_CHAR_INT_KER_LBN 3
508 #define	FRF_AZ_CHAR_INT_KER_WIDTH 1
509 #define	FRF_AZ_DRV_INT_EN_CHAR_LBN 0
510 #define	FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1
511 
512 
513 /*
514  * FR_AZ_INT_ADR_REG_KER(128bit):
515  * Interrupt host address for Kernel driver
516  */
517 #define	FR_AZ_INT_ADR_REG_KER_OFST 0x00000030
518 /* falcona0,falconb0,sienaa0=net_func_bar2 */
519 
520 #define	FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64
521 #define	FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1
522 #define	FRF_AZ_INT_ADR_KER_LBN 0
523 #define	FRF_AZ_INT_ADR_KER_WIDTH 64
524 #define	FRF_AZ_INT_ADR_KER_DW0_LBN 0
525 #define	FRF_AZ_INT_ADR_KER_DW0_WIDTH 32
526 #define	FRF_AZ_INT_ADR_KER_DW1_LBN 32
527 #define	FRF_AZ_INT_ADR_KER_DW1_WIDTH 32
528 
529 
530 /*
531  * FR_AZ_INT_ADR_REG_CHAR(128bit):
532  * Interrupt host address for Char driver
533  */
534 #define	FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040
535 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
536 
537 #define	FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64
538 #define	FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1
539 #define	FRF_AZ_INT_ADR_CHAR_LBN 0
540 #define	FRF_AZ_INT_ADR_CHAR_WIDTH 64
541 #define	FRF_AZ_INT_ADR_CHAR_DW0_LBN 0
542 #define	FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32
543 #define	FRF_AZ_INT_ADR_CHAR_DW1_LBN 32
544 #define	FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32
545 
546 
547 /*
548  * FR_AA_INT_ACK_KER(32bit):
549  * Kernel interrupt acknowledge register
550  */
551 #define	FR_AA_INT_ACK_KER_OFST 0x00000050
552 /* falcona0=net_func_bar2 */
553 
554 #define	FRF_AA_INT_ACK_KER_FIELD_LBN 0
555 #define	FRF_AA_INT_ACK_KER_FIELD_WIDTH 32
556 
557 
558 /*
559  * FR_BZ_INT_ISR0_REG(128bit):
560  * Function 0 Interrupt Acknowlege Status register
561  */
562 #define	FR_BZ_INT_ISR0_REG_OFST 0x00000090
563 /* falconb0,sienaa0=net_func_bar2 */
564 
565 #define	FRF_BZ_INT_ISR_REG_LBN 0
566 #define	FRF_BZ_INT_ISR_REG_WIDTH 64
567 #define	FRF_BZ_INT_ISR_REG_DW0_LBN 0
568 #define	FRF_BZ_INT_ISR_REG_DW0_WIDTH 32
569 #define	FRF_BZ_INT_ISR_REG_DW1_LBN 32
570 #define	FRF_BZ_INT_ISR_REG_DW1_WIDTH 32
571 
572 
573 /*
574  * FR_AB_EE_SPI_HCMD_REG(128bit):
575  * SPI host command register
576  */
577 #define	FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100
578 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
579 
580 #define	FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31
581 #define	FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1
582 #define	FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28
583 #define	FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1
584 #define	FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24
585 #define	FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1
586 #define	FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16
587 #define	FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5
588 #define	FRF_AB_EE_SPI_HCMD_READ_LBN 15
589 #define	FRF_AB_EE_SPI_HCMD_READ_WIDTH 1
590 #define	FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12
591 #define	FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2
592 #define	FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8
593 #define	FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2
594 #define	FRF_AB_EE_SPI_HCMD_ENC_LBN 0
595 #define	FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8
596 
597 
598 /*
599  * FR_CZ_USR_EV_CFG(32bit):
600  * User Level Event Configuration register
601  */
602 #define	FR_CZ_USR_EV_CFG_OFST 0x00000100
603 /* sienaa0=net_func_bar2 */
604 
605 #define	FRF_CZ_USREV_DIS_LBN 16
606 #define	FRF_CZ_USREV_DIS_WIDTH 1
607 #define	FRF_CZ_DFLT_EVQ_LBN 0
608 #define	FRF_CZ_DFLT_EVQ_WIDTH 10
609 
610 
611 /*
612  * FR_AB_EE_SPI_HADR_REG(128bit):
613  * SPI host address register
614  */
615 #define	FR_AB_EE_SPI_HADR_REG_OFST 0x00000110
616 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
617 
618 #define	FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24
619 #define	FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8
620 #define	FRF_AB_EE_SPI_HADR_ADR_LBN 0
621 #define	FRF_AB_EE_SPI_HADR_ADR_WIDTH 24
622 
623 
624 /*
625  * FR_AB_EE_SPI_HDATA_REG(128bit):
626  * SPI host data register
627  */
628 #define	FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120
629 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
630 
631 #define	FRF_AB_EE_SPI_HDATA3_LBN 96
632 #define	FRF_AB_EE_SPI_HDATA3_WIDTH 32
633 #define	FRF_AB_EE_SPI_HDATA2_LBN 64
634 #define	FRF_AB_EE_SPI_HDATA2_WIDTH 32
635 #define	FRF_AB_EE_SPI_HDATA1_LBN 32
636 #define	FRF_AB_EE_SPI_HDATA1_WIDTH 32
637 #define	FRF_AB_EE_SPI_HDATA0_LBN 0
638 #define	FRF_AB_EE_SPI_HDATA0_WIDTH 32
639 
640 
641 /*
642  * FR_AB_EE_BASE_PAGE_REG(128bit):
643  * Expansion ROM base mirror register
644  */
645 #define	FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130
646 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
647 
648 #define	FRF_AB_EE_EXPROM_MASK_LBN 16
649 #define	FRF_AB_EE_EXPROM_MASK_WIDTH 13
650 #define	FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0
651 #define	FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13
652 
653 
654 /*
655  * FR_AB_EE_VPD_SW_CNTL_REG(128bit):
656  * VPD access SW control register
657  */
658 #define	FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150
659 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
660 
661 #define	FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31
662 #define	FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1
663 #define	FRF_AB_EE_VPD_CYC_WRITE_LBN 28
664 #define	FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1
665 #define	FRF_AB_EE_VPD_CYC_ADR_LBN 0
666 #define	FRF_AB_EE_VPD_CYC_ADR_WIDTH 15
667 
668 
669 /*
670  * FR_AB_EE_VPD_SW_DATA_REG(128bit):
671  * VPD access SW data register
672  */
673 #define	FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160
674 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
675 
676 #define	FRF_AB_EE_VPD_CYC_DAT_LBN 0
677 #define	FRF_AB_EE_VPD_CYC_DAT_WIDTH 32
678 
679 
680 /*
681  * FR_BB_PCIE_CORE_INDIRECT_REG(64bit):
682  * Indirect Access to PCIE Core registers
683  */
684 #define	FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0
685 /* falconb0=net_func_bar2 */
686 
687 #define	FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32
688 #define	FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32
689 #define	FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15
690 #define	FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1
691 #define	FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0
692 #define	FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12
693 
694 
695 /*
696  * FR_AB_GPIO_CTL_REG(128bit):
697  * GPIO control register
698  */
699 #define	FR_AB_GPIO_CTL_REG_OFST 0x00000210
700 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
701 
702 #define	FRF_AB_GPIO15_OEN_LBN 63
703 #define	FRF_AB_GPIO15_OEN_WIDTH 1
704 #define	FRF_AB_GPIO14_OEN_LBN 62
705 #define	FRF_AB_GPIO14_OEN_WIDTH 1
706 #define	FRF_AB_GPIO13_OEN_LBN 61
707 #define	FRF_AB_GPIO13_OEN_WIDTH 1
708 #define	FRF_AB_GPIO12_OEN_LBN 60
709 #define	FRF_AB_GPIO12_OEN_WIDTH 1
710 #define	FRF_AB_GPIO11_OEN_LBN 59
711 #define	FRF_AB_GPIO11_OEN_WIDTH 1
712 #define	FRF_AB_GPIO10_OEN_LBN 58
713 #define	FRF_AB_GPIO10_OEN_WIDTH 1
714 #define	FRF_AB_GPIO9_OEN_LBN 57
715 #define	FRF_AB_GPIO9_OEN_WIDTH 1
716 #define	FRF_AB_GPIO8_OEN_LBN 56
717 #define	FRF_AB_GPIO8_OEN_WIDTH 1
718 #define	FRF_AB_GPIO15_OUT_LBN 55
719 #define	FRF_AB_GPIO15_OUT_WIDTH 1
720 #define	FRF_AB_GPIO14_OUT_LBN 54
721 #define	FRF_AB_GPIO14_OUT_WIDTH 1
722 #define	FRF_AB_GPIO13_OUT_LBN 53
723 #define	FRF_AB_GPIO13_OUT_WIDTH 1
724 #define	FRF_AB_GPIO12_OUT_LBN 52
725 #define	FRF_AB_GPIO12_OUT_WIDTH 1
726 #define	FRF_AB_GPIO11_OUT_LBN 51
727 #define	FRF_AB_GPIO11_OUT_WIDTH 1
728 #define	FRF_AB_GPIO10_OUT_LBN 50
729 #define	FRF_AB_GPIO10_OUT_WIDTH 1
730 #define	FRF_AB_GPIO9_OUT_LBN 49
731 #define	FRF_AB_GPIO9_OUT_WIDTH 1
732 #define	FRF_AB_GPIO8_OUT_LBN 48
733 #define	FRF_AB_GPIO8_OUT_WIDTH 1
734 #define	FRF_AB_GPIO15_IN_LBN 47
735 #define	FRF_AB_GPIO15_IN_WIDTH 1
736 #define	FRF_AB_GPIO14_IN_LBN 46
737 #define	FRF_AB_GPIO14_IN_WIDTH 1
738 #define	FRF_AB_GPIO13_IN_LBN 45
739 #define	FRF_AB_GPIO13_IN_WIDTH 1
740 #define	FRF_AB_GPIO12_IN_LBN 44
741 #define	FRF_AB_GPIO12_IN_WIDTH 1
742 #define	FRF_AB_GPIO11_IN_LBN 43
743 #define	FRF_AB_GPIO11_IN_WIDTH 1
744 #define	FRF_AB_GPIO10_IN_LBN 42
745 #define	FRF_AB_GPIO10_IN_WIDTH 1
746 #define	FRF_AB_GPIO9_IN_LBN 41
747 #define	FRF_AB_GPIO9_IN_WIDTH 1
748 #define	FRF_AB_GPIO8_IN_LBN 40
749 #define	FRF_AB_GPIO8_IN_WIDTH 1
750 #define	FRF_AB_GPIO15_PWRUP_VALUE_LBN 39
751 #define	FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1
752 #define	FRF_AB_GPIO14_PWRUP_VALUE_LBN 38
753 #define	FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1
754 #define	FRF_AB_GPIO13_PWRUP_VALUE_LBN 37
755 #define	FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1
756 #define	FRF_AB_GPIO12_PWRUP_VALUE_LBN 36
757 #define	FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1
758 #define	FRF_AB_GPIO11_PWRUP_VALUE_LBN 35
759 #define	FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1
760 #define	FRF_AB_GPIO10_PWRUP_VALUE_LBN 34
761 #define	FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1
762 #define	FRF_AB_GPIO9_PWRUP_VALUE_LBN 33
763 #define	FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1
764 #define	FRF_AB_GPIO8_PWRUP_VALUE_LBN 32
765 #define	FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1
766 #define	FRF_BB_CLK156_OUT_EN_LBN 31
767 #define	FRF_BB_CLK156_OUT_EN_WIDTH 1
768 #define	FRF_BB_USE_NIC_CLK_LBN 30
769 #define	FRF_BB_USE_NIC_CLK_WIDTH 1
770 #define	FRF_AB_GPIO5_OEN_LBN 29
771 #define	FRF_AB_GPIO5_OEN_WIDTH 1
772 #define	FRF_AB_GPIO4_OEN_LBN 28
773 #define	FRF_AB_GPIO4_OEN_WIDTH 1
774 #define	FRF_AB_GPIO3_OEN_LBN 27
775 #define	FRF_AB_GPIO3_OEN_WIDTH 1
776 #define	FRF_AB_GPIO2_OEN_LBN 26
777 #define	FRF_AB_GPIO2_OEN_WIDTH 1
778 #define	FRF_AB_GPIO1_OEN_LBN 25
779 #define	FRF_AB_GPIO1_OEN_WIDTH 1
780 #define	FRF_AB_GPIO0_OEN_LBN 24
781 #define	FRF_AB_GPIO0_OEN_WIDTH 1
782 #define	FRF_AB_GPIO5_OUT_LBN 21
783 #define	FRF_AB_GPIO5_OUT_WIDTH 1
784 #define	FRF_AB_GPIO4_OUT_LBN 20
785 #define	FRF_AB_GPIO4_OUT_WIDTH 1
786 #define	FRF_AB_GPIO3_OUT_LBN 19
787 #define	FRF_AB_GPIO3_OUT_WIDTH 1
788 #define	FRF_AB_GPIO2_OUT_LBN 18
789 #define	FRF_AB_GPIO2_OUT_WIDTH 1
790 #define	FRF_AB_GPIO1_OUT_LBN 17
791 #define	FRF_AB_GPIO1_OUT_WIDTH 1
792 #define	FRF_AB_GPIO0_OUT_LBN 16
793 #define	FRF_AB_GPIO0_OUT_WIDTH 1
794 #define	FRF_AB_GPIO5_IN_LBN 13
795 #define	FRF_AB_GPIO5_IN_WIDTH 1
796 #define	FRF_AB_GPIO4_IN_LBN 12
797 #define	FRF_AB_GPIO4_IN_WIDTH 1
798 #define	FRF_AB_GPIO3_IN_LBN 11
799 #define	FRF_AB_GPIO3_IN_WIDTH 1
800 #define	FRF_AB_GPIO2_IN_LBN 10
801 #define	FRF_AB_GPIO2_IN_WIDTH 1
802 #define	FRF_AB_GPIO1_IN_LBN 9
803 #define	FRF_AB_GPIO1_IN_WIDTH 1
804 #define	FRF_AB_GPIO0_IN_LBN 8
805 #define	FRF_AB_GPIO0_IN_WIDTH 1
806 #define	FRF_AB_GPIO5_PWRUP_VALUE_LBN 5
807 #define	FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1
808 #define	FRF_AB_GPIO4_PWRUP_VALUE_LBN 4
809 #define	FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1
810 #define	FRF_AB_GPIO3_PWRUP_VALUE_LBN 3
811 #define	FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1
812 #define	FRF_AB_GPIO2_PWRUP_VALUE_LBN 2
813 #define	FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1
814 #define	FRF_AB_GPIO1_PWRUP_VALUE_LBN 1
815 #define	FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1
816 #define	FRF_AB_GPIO0_PWRUP_VALUE_LBN 0
817 #define	FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1
818 
819 
820 /*
821  * FR_AZ_FATAL_INTR_REG_KER(128bit):
822  * Fatal interrupt register for Kernel
823  */
824 #define	FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230
825 /* falcona0,falconb0,sienaa0=net_func_bar2 */
826 
827 #define	FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44
828 #define	FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1
829 #define	FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43
830 #define	FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1
831 #define	FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43
832 #define	FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1
833 #define	FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42
834 #define	FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1
835 #define	FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41
836 #define	FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1
837 #define	FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40
838 #define	FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1
839 #define	FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39
840 #define	FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1
841 #define	FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38
842 #define	FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1
843 #define	FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37
844 #define	FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1
845 #define	FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36
846 #define	FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1
847 #define	FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35
848 #define	FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1
849 #define	FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34
850 #define	FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1
851 #define	FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33
852 #define	FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1
853 #define	FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32
854 #define	FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1
855 #define	FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12
856 #define	FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1
857 #define	FRF_AB_PCI_BUSERR_INT_KER_LBN 11
858 #define	FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1
859 #define	FRF_CZ_MBU_PERR_INT_KER_LBN 11
860 #define	FRF_CZ_MBU_PERR_INT_KER_WIDTH 1
861 #define	FRF_AZ_SRAM_OOB_INT_KER_LBN 10
862 #define	FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1
863 #define	FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9
864 #define	FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1
865 #define	FRF_AZ_MEM_PERR_INT_KER_LBN 8
866 #define	FRF_AZ_MEM_PERR_INT_KER_WIDTH 1
867 #define	FRF_AZ_RBUF_OWN_INT_KER_LBN 7
868 #define	FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1
869 #define	FRF_AZ_TBUF_OWN_INT_KER_LBN 6
870 #define	FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1
871 #define	FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5
872 #define	FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1
873 #define	FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4
874 #define	FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1
875 #define	FRF_AZ_EVQ_OWN_INT_KER_LBN 3
876 #define	FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1
877 #define	FRF_AZ_EVF_OFLO_INT_KER_LBN 2
878 #define	FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1
879 #define	FRF_AZ_ILL_ADR_INT_KER_LBN 1
880 #define	FRF_AZ_ILL_ADR_INT_KER_WIDTH 1
881 #define	FRF_AZ_SRM_PERR_INT_KER_LBN 0
882 #define	FRF_AZ_SRM_PERR_INT_KER_WIDTH 1
883 
884 
885 /*
886  * FR_AZ_FATAL_INTR_REG_CHAR(128bit):
887  * Fatal interrupt register for Char
888  */
889 #define	FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240
890 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
891 
892 #define	FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44
893 #define	FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1
894 #define	FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43
895 #define	FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1
896 #define	FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43
897 #define	FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1
898 #define	FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42
899 #define	FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1
900 #define	FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41
901 #define	FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1
902 #define	FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40
903 #define	FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1
904 #define	FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39
905 #define	FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1
906 #define	FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38
907 #define	FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1
908 #define	FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37
909 #define	FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1
910 #define	FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36
911 #define	FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1
912 #define	FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35
913 #define	FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1
914 #define	FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34
915 #define	FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1
916 #define	FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33
917 #define	FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1
918 #define	FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32
919 #define	FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1
920 #define	FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12
921 #define	FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1
922 #define	FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11
923 #define	FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1
924 #define	FRF_CZ_MBU_PERR_INT_CHAR_LBN 11
925 #define	FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1
926 #define	FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10
927 #define	FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1
928 #define	FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9
929 #define	FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1
930 #define	FRF_AZ_MEM_PERR_INT_CHAR_LBN 8
931 #define	FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1
932 #define	FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7
933 #define	FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1
934 #define	FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6
935 #define	FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1
936 #define	FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5
937 #define	FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1
938 #define	FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4
939 #define	FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1
940 #define	FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3
941 #define	FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1
942 #define	FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2
943 #define	FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1
944 #define	FRF_AZ_ILL_ADR_INT_CHAR_LBN 1
945 #define	FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1
946 #define	FRF_AZ_SRM_PERR_INT_CHAR_LBN 0
947 #define	FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1
948 
949 
950 /*
951  * FR_AZ_DP_CTRL_REG(128bit):
952  * Datapath control register
953  */
954 #define	FR_AZ_DP_CTRL_REG_OFST 0x00000250
955 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
956 
957 #define	FRF_AZ_FLS_EVQ_ID_LBN 0
958 #define	FRF_AZ_FLS_EVQ_ID_WIDTH 12
959 
960 
961 /*
962  * FR_AZ_MEM_STAT_REG(128bit):
963  * Memory status register
964  */
965 #define	FR_AZ_MEM_STAT_REG_OFST 0x00000260
966 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
967 
968 #define	FRF_AB_MEM_PERR_VEC_LBN 53
969 #define	FRF_AB_MEM_PERR_VEC_WIDTH 40
970 #define	FRF_AB_MEM_PERR_VEC_DW0_LBN 53
971 #define	FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32
972 #define	FRF_AB_MEM_PERR_VEC_DW1_LBN 85
973 #define	FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6
974 #define	FRF_AB_MBIST_CORR_LBN 38
975 #define	FRF_AB_MBIST_CORR_WIDTH 15
976 #define	FRF_AB_MBIST_ERR_LBN 0
977 #define	FRF_AB_MBIST_ERR_WIDTH 40
978 #define	FRF_AB_MBIST_ERR_DW0_LBN 0
979 #define	FRF_AB_MBIST_ERR_DW0_WIDTH 32
980 #define	FRF_AB_MBIST_ERR_DW1_LBN 32
981 #define	FRF_AB_MBIST_ERR_DW1_WIDTH 6
982 #define	FRF_CZ_MEM_PERR_VEC_LBN 0
983 #define	FRF_CZ_MEM_PERR_VEC_WIDTH 35
984 #define	FRF_CZ_MEM_PERR_VEC_DW0_LBN 0
985 #define	FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32
986 #define	FRF_CZ_MEM_PERR_VEC_DW1_LBN 32
987 #define	FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3
988 
989 
990 /*
991  * FR_PORT0_CS_DEBUG_REG(128bit):
992  * Debug register
993  */
994 
995 #define	FR_AZ_CS_DEBUG_REG_OFST 0x00000270
996 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
997 
998 #define	FRF_AB_GLB_DEBUG2_SEL_LBN 50
999 #define	FRF_AB_GLB_DEBUG2_SEL_WIDTH 3
1000 #define	FRF_AB_DEBUG_BLK_SEL2_LBN 47
1001 #define	FRF_AB_DEBUG_BLK_SEL2_WIDTH 3
1002 #define	FRF_AB_DEBUG_BLK_SEL1_LBN 44
1003 #define	FRF_AB_DEBUG_BLK_SEL1_WIDTH 3
1004 #define	FRF_AB_DEBUG_BLK_SEL0_LBN 41
1005 #define	FRF_AB_DEBUG_BLK_SEL0_WIDTH 3
1006 #define	FRF_CZ_CS_PORT_NUM_LBN 40
1007 #define	FRF_CZ_CS_PORT_NUM_WIDTH 2
1008 #define	FRF_AB_MISC_DEBUG_ADDR_LBN 36
1009 #define	FRF_AB_MISC_DEBUG_ADDR_WIDTH 5
1010 #define	FRF_CZ_CS_RESERVED_LBN 36
1011 #define	FRF_CZ_CS_RESERVED_WIDTH 4
1012 #define	FRF_AB_SERDES_DEBUG_ADDR_LBN 31
1013 #define	FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5
1014 #define	FRF_CZ_CS_PORT_FPE_DW0_LBN 1
1015 #define	FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32
1016 #define	FRF_CZ_CS_PORT_FPE_DW1_LBN 33
1017 #define	FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3
1018 #define	FRF_CZ_CS_PORT_FPE_LBN 1
1019 #define	FRF_CZ_CS_PORT_FPE_WIDTH 35
1020 #define	FRF_AB_EM_DEBUG_ADDR_LBN 26
1021 #define	FRF_AB_EM_DEBUG_ADDR_WIDTH 5
1022 #define	FRF_AB_SR_DEBUG_ADDR_LBN 21
1023 #define	FRF_AB_SR_DEBUG_ADDR_WIDTH 5
1024 #define	FRF_AB_EV_DEBUG_ADDR_LBN 16
1025 #define	FRF_AB_EV_DEBUG_ADDR_WIDTH 5
1026 #define	FRF_AB_RX_DEBUG_ADDR_LBN 11
1027 #define	FRF_AB_RX_DEBUG_ADDR_WIDTH 5
1028 #define	FRF_AB_TX_DEBUG_ADDR_LBN 6
1029 #define	FRF_AB_TX_DEBUG_ADDR_WIDTH 5
1030 #define	FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1
1031 #define	FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5
1032 #define	FRF_AZ_CS_DEBUG_EN_LBN 0
1033 #define	FRF_AZ_CS_DEBUG_EN_WIDTH 1
1034 
1035 
1036 /*
1037  * FR_AZ_DRIVER_REG(128bit):
1038  * Driver scratch register [0-7]
1039  */
1040 #define	FR_AZ_DRIVER_REG_OFST 0x00000280
1041 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1042 #define	FR_AZ_DRIVER_REG_STEP 16
1043 #define	FR_AZ_DRIVER_REG_ROWS 8
1044 
1045 #define	FRF_AZ_DRIVER_DW0_LBN 0
1046 #define	FRF_AZ_DRIVER_DW0_WIDTH 32
1047 
1048 
1049 /*
1050  * FR_AZ_ALTERA_BUILD_REG(128bit):
1051  * Altera build register
1052  */
1053 #define	FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300
1054 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1055 
1056 #define	FRF_AZ_ALTERA_BUILD_VER_LBN 0
1057 #define	FRF_AZ_ALTERA_BUILD_VER_WIDTH 32
1058 
1059 
1060 /*
1061  * FR_AZ_CSR_SPARE_REG(128bit):
1062  * Spare register
1063  */
1064 #define	FR_AZ_CSR_SPARE_REG_OFST 0x00000310
1065 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1066 
1067 #define	FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72
1068 #define	FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2
1069 #define	FRF_AZ_MEM_PERR_EN_LBN 64
1070 #define	FRF_AZ_MEM_PERR_EN_WIDTH 38
1071 #define	FRF_AZ_MEM_PERR_EN_DW0_LBN 64
1072 #define	FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32
1073 #define	FRF_AZ_MEM_PERR_EN_DW1_LBN 96
1074 #define	FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6
1075 #define	FRF_AZ_CSR_SPARE_BITS_LBN 0
1076 #define	FRF_AZ_CSR_SPARE_BITS_WIDTH 32
1077 
1078 
1079 /*
1080  * FR_BZ_DEBUG_DATA_OUT_REG(128bit):
1081  * Live Debug and Debug 2 out ports
1082  */
1083 #define	FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350
1084 /* falconb0,sienaa0=net_func_bar2 */
1085 
1086 #define	FRF_BZ_DEBUG2_PORT_LBN 25
1087 #define	FRF_BZ_DEBUG2_PORT_WIDTH 15
1088 #define	FRF_BZ_DEBUG1_PORT_LBN 0
1089 #define	FRF_BZ_DEBUG1_PORT_WIDTH 25
1090 
1091 
1092 /*
1093  * FR_BZ_EVQ_RPTR_REGP0(32bit):
1094  * Event queue read pointer register
1095  */
1096 #define	FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400
1097 /* falconb0,sienaa0=net_func_bar2 */
1098 #define	FR_BZ_EVQ_RPTR_REGP0_STEP 8192
1099 #define	FR_BZ_EVQ_RPTR_REGP0_ROWS 1024
1100 /*
1101  * FR_AA_EVQ_RPTR_REG_KER(32bit):
1102  * Event queue read pointer register
1103  */
1104 #define	FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00
1105 /* falcona0=net_func_bar2 */
1106 #define	FR_AA_EVQ_RPTR_REG_KER_STEP 4
1107 #define	FR_AA_EVQ_RPTR_REG_KER_ROWS 4
1108 /*
1109  * FR_AZ_EVQ_RPTR_REG(32bit):
1110  * Event queue read pointer register
1111  */
1112 #define	FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000
1113 /* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1114 #define	FR_AZ_EVQ_RPTR_REG_STEP 16
1115 #define	FR_AB_EVQ_RPTR_REG_ROWS 4096
1116 #define	FR_CZ_EVQ_RPTR_REG_ROWS 1024
1117 /*
1118  * FR_BB_EVQ_RPTR_REGP123(32bit):
1119  * Event queue read pointer register
1120  */
1121 #define	FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400
1122 /* falconb0=net_func_bar2 */
1123 #define	FR_BB_EVQ_RPTR_REGP123_STEP 8192
1124 #define	FR_BB_EVQ_RPTR_REGP123_ROWS 3072
1125 
1126 #define	FRF_AZ_EVQ_RPTR_VLD_LBN 15
1127 #define	FRF_AZ_EVQ_RPTR_VLD_WIDTH 1
1128 #define	FRF_AZ_EVQ_RPTR_LBN 0
1129 #define	FRF_AZ_EVQ_RPTR_WIDTH 15
1130 
1131 
1132 /*
1133  * FR_BZ_TIMER_COMMAND_REGP0(128bit):
1134  * Timer Command Registers
1135  */
1136 #define	FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420
1137 /* falconb0,sienaa0=net_func_bar2 */
1138 #define	FR_BZ_TIMER_COMMAND_REGP0_STEP 8192
1139 #define	FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024
1140 /*
1141  * FR_AA_TIMER_COMMAND_REG_KER(128bit):
1142  * Timer Command Registers
1143  */
1144 #define	FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420
1145 /* falcona0=net_func_bar2 */
1146 #define	FR_AA_TIMER_COMMAND_REG_KER_STEP 8192
1147 #define	FR_AA_TIMER_COMMAND_REG_KER_ROWS 4
1148 /*
1149  * FR_AB_TIMER_COMMAND_REGP123(128bit):
1150  * Timer Command Registers
1151  */
1152 #define	FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420
1153 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
1154 #define	FR_AB_TIMER_COMMAND_REGP123_STEP 8192
1155 #define	FR_AB_TIMER_COMMAND_REGP123_ROWS 3072
1156 /*
1157  * FR_AA_TIMER_COMMAND_REGP0(128bit):
1158  * Timer Command Registers
1159  */
1160 #define	FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420
1161 /* falcona0=char_func_bar0 */
1162 #define	FR_AA_TIMER_COMMAND_REGP0_STEP 8192
1163 #define	FR_AA_TIMER_COMMAND_REGP0_ROWS 1020
1164 
1165 #define	FRF_CZ_TC_TIMER_MODE_LBN 14
1166 #define	FRF_CZ_TC_TIMER_MODE_WIDTH 2
1167 #define	FRF_AB_TC_TIMER_MODE_LBN 12
1168 #define	FRF_AB_TC_TIMER_MODE_WIDTH 2
1169 #define	FRF_CZ_TC_TIMER_VAL_LBN 0
1170 #define	FRF_CZ_TC_TIMER_VAL_WIDTH 14
1171 #define	FRF_AB_TC_TIMER_VAL_LBN 0
1172 #define	FRF_AB_TC_TIMER_VAL_WIDTH 12
1173 
1174 
1175 /*
1176  * FR_AZ_DRV_EV_REG(128bit):
1177  * Driver generated event register
1178  */
1179 #define	FR_AZ_DRV_EV_REG_OFST 0x00000440
1180 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1181 
1182 #define	FRF_AZ_DRV_EV_QID_LBN 64
1183 #define	FRF_AZ_DRV_EV_QID_WIDTH 12
1184 #define	FRF_AZ_DRV_EV_DATA_LBN 0
1185 #define	FRF_AZ_DRV_EV_DATA_WIDTH 64
1186 #define	FRF_AZ_DRV_EV_DATA_DW0_LBN 0
1187 #define	FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32
1188 #define	FRF_AZ_DRV_EV_DATA_DW1_LBN 32
1189 #define	FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32
1190 
1191 
1192 /*
1193  * FR_AZ_EVQ_CTL_REG(128bit):
1194  * Event queue control register
1195  */
1196 #define	FR_AZ_EVQ_CTL_REG_OFST 0x00000450
1197 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1198 
1199 #define	FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15
1200 #define	FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10
1201 #define	FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15
1202 #define	FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6
1203 #define	FRF_AZ_EVQ_OWNERR_CTL_LBN 14
1204 #define	FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1
1205 #define	FRF_AZ_EVQ_FIFO_AF_TH_LBN 7
1206 #define	FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7
1207 #define	FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0
1208 #define	FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7
1209 
1210 
1211 /*
1212  * FR_AZ_EVQ_CNT1_REG(128bit):
1213  * Event counter 1 register
1214  */
1215 #define	FR_AZ_EVQ_CNT1_REG_OFST 0x00000460
1216 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1217 
1218 #define	FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120
1219 #define	FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7
1220 #define	FRF_AZ_EVQ_CNT_TOBIU_LBN 100
1221 #define	FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20
1222 #define	FRF_AZ_EVQ_TX_REQ_CNT_LBN 80
1223 #define	FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20
1224 #define	FRF_AZ_EVQ_RX_REQ_CNT_LBN 60
1225 #define	FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20
1226 #define	FRF_AZ_EVQ_EM_REQ_CNT_LBN 40
1227 #define	FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20
1228 #define	FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20
1229 #define	FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20
1230 #define	FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0
1231 #define	FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20
1232 
1233 
1234 /*
1235  * FR_AZ_EVQ_CNT2_REG(128bit):
1236  * Event counter 2 register
1237  */
1238 #define	FR_AZ_EVQ_CNT2_REG_OFST 0x00000470
1239 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1240 
1241 #define	FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104
1242 #define	FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20
1243 #define	FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84
1244 #define	FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20
1245 #define	FRF_AZ_EVQ_RDY_CNT_LBN 80
1246 #define	FRF_AZ_EVQ_RDY_CNT_WIDTH 4
1247 #define	FRF_AZ_EVQ_WU_REQ_CNT_LBN 60
1248 #define	FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20
1249 #define	FRF_AZ_EVQ_WET_REQ_CNT_LBN 40
1250 #define	FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20
1251 #define	FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20
1252 #define	FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20
1253 #define	FRF_AZ_EVQ_TM_REQ_CNT_LBN 0
1254 #define	FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20
1255 
1256 
1257 /*
1258  * FR_CZ_USR_EV_REG(32bit):
1259  * Event mailbox register
1260  */
1261 #define	FR_CZ_USR_EV_REG_OFST 0x00000540
1262 /* sienaa0=net_func_bar2 */
1263 #define	FR_CZ_USR_EV_REG_STEP 8192
1264 #define	FR_CZ_USR_EV_REG_ROWS 1024
1265 
1266 #define	FRF_CZ_USR_EV_DATA_LBN 0
1267 #define	FRF_CZ_USR_EV_DATA_WIDTH 32
1268 
1269 
1270 /*
1271  * FR_AZ_BUF_TBL_CFG_REG(128bit):
1272  * Buffer table configuration register
1273  */
1274 #define	FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600
1275 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1276 
1277 #define	FRF_AZ_BUF_TBL_MODE_LBN 3
1278 #define	FRF_AZ_BUF_TBL_MODE_WIDTH 1
1279 
1280 
1281 /*
1282  * FR_AZ_SRM_RX_DC_CFG_REG(128bit):
1283  * SRAM receive descriptor cache configuration register
1284  */
1285 #define	FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610
1286 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1287 
1288 #define	FRF_AZ_SRM_CLK_TMP_EN_LBN 21
1289 #define	FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1
1290 #define	FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0
1291 #define	FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21
1292 
1293 
1294 /*
1295  * FR_AZ_SRM_TX_DC_CFG_REG(128bit):
1296  * SRAM transmit descriptor cache configuration register
1297  */
1298 #define	FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620
1299 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1300 
1301 #define	FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0
1302 #define	FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21
1303 
1304 
1305 /*
1306  * FR_AZ_SRM_CFG_REG(128bit):
1307  * SRAM configuration register
1308  */
1309 #define	FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380
1310 /* falcona0,falconb0=eeprom_flash */
1311 /*
1312  * FR_AZ_SRM_CFG_REG(128bit):
1313  * SRAM configuration register
1314  */
1315 #define	FR_AZ_SRM_CFG_REG_OFST 0x00000630
1316 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1317 
1318 #define	FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5
1319 #define	FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1
1320 #define	FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4
1321 #define	FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1
1322 #define	FRF_AZ_SRM_INIT_EN_LBN 3
1323 #define	FRF_AZ_SRM_INIT_EN_WIDTH 1
1324 #define	FRF_AZ_SRM_NUM_BANK_LBN 2
1325 #define	FRF_AZ_SRM_NUM_BANK_WIDTH 1
1326 #define	FRF_AZ_SRM_BANK_SIZE_LBN 0
1327 #define	FRF_AZ_SRM_BANK_SIZE_WIDTH 2
1328 
1329 
1330 /*
1331  * FR_AZ_BUF_TBL_UPD_REG(128bit):
1332  * Buffer table update register
1333  */
1334 #define	FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650
1335 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1336 
1337 #define	FRF_AZ_BUF_UPD_CMD_LBN 63
1338 #define	FRF_AZ_BUF_UPD_CMD_WIDTH 1
1339 #define	FRF_AZ_BUF_CLR_CMD_LBN 62
1340 #define	FRF_AZ_BUF_CLR_CMD_WIDTH 1
1341 #define	FRF_AZ_BUF_CLR_END_ID_LBN 32
1342 #define	FRF_AZ_BUF_CLR_END_ID_WIDTH 20
1343 #define	FRF_AZ_BUF_CLR_START_ID_LBN 0
1344 #define	FRF_AZ_BUF_CLR_START_ID_WIDTH 20
1345 
1346 
1347 /*
1348  * FR_AZ_SRM_UPD_EVQ_REG(128bit):
1349  * Buffer table update register
1350  */
1351 #define	FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660
1352 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1353 
1354 #define	FRF_AZ_SRM_UPD_EVQ_ID_LBN 0
1355 #define	FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12
1356 
1357 
1358 /*
1359  * FR_AZ_SRAM_PARITY_REG(128bit):
1360  * SRAM parity register.
1361  */
1362 #define	FR_AZ_SRAM_PARITY_REG_OFST 0x00000670
1363 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1364 
1365 #define	FRF_CZ_BYPASS_ECC_LBN 3
1366 #define	FRF_CZ_BYPASS_ECC_WIDTH 1
1367 #define	FRF_CZ_SEC_INT_LBN 2
1368 #define	FRF_CZ_SEC_INT_WIDTH 1
1369 #define	FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1
1370 #define	FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1
1371 #define	FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0
1372 #define	FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1
1373 #define	FRF_AB_FORCE_SRAM_PERR_LBN 0
1374 #define	FRF_AB_FORCE_SRAM_PERR_WIDTH 1
1375 
1376 
1377 /*
1378  * FR_AZ_RX_CFG_REG(128bit):
1379  * Receive configuration register
1380  */
1381 #define	FR_AZ_RX_CFG_REG_OFST 0x00000800
1382 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1383 
1384 #define	FRF_CZ_RX_HDR_SPLIT_EN_LBN 71
1385 #define	FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1
1386 #define	FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62
1387 #define	FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9
1388 #define	FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53
1389 #define	FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9
1390 #define	FRF_CZ_RX_PRE_RFF_IPG_LBN 49
1391 #define	FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4
1392 #define	FRF_BZ_RX_TCP_SUP_LBN 48
1393 #define	FRF_BZ_RX_TCP_SUP_WIDTH 1
1394 #define	FRF_BZ_RX_INGR_EN_LBN 47
1395 #define	FRF_BZ_RX_INGR_EN_WIDTH 1
1396 #define	FRF_BZ_RX_IP_HASH_LBN 46
1397 #define	FRF_BZ_RX_IP_HASH_WIDTH 1
1398 #define	FRF_BZ_RX_HASH_ALG_LBN 45
1399 #define	FRF_BZ_RX_HASH_ALG_WIDTH 1
1400 #define	FRF_BZ_RX_HASH_INSRT_HDR_LBN 44
1401 #define	FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1
1402 #define	FRF_BZ_RX_DESC_PUSH_EN_LBN 43
1403 #define	FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1
1404 #define	FRF_BZ_RX_RDW_PATCH_EN_LBN 42
1405 #define	FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1
1406 #define	FRF_BB_RX_PCI_BURST_SIZE_LBN 39
1407 #define	FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3
1408 #define	FRF_BZ_RX_OWNERR_CTL_LBN 38
1409 #define	FRF_BZ_RX_OWNERR_CTL_WIDTH 1
1410 #define	FRF_BZ_RX_XON_TX_TH_LBN 33
1411 #define	FRF_BZ_RX_XON_TX_TH_WIDTH 5
1412 #define	FRF_AA_RX_DESC_PUSH_EN_LBN 35
1413 #define	FRF_AA_RX_DESC_PUSH_EN_WIDTH 1
1414 #define	FRF_AA_RX_RDW_PATCH_EN_LBN 34
1415 #define	FRF_AA_RX_RDW_PATCH_EN_WIDTH 1
1416 #define	FRF_AA_RX_PCI_BURST_SIZE_LBN 31
1417 #define	FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3
1418 #define	FRF_BZ_RX_XOFF_TX_TH_LBN 28
1419 #define	FRF_BZ_RX_XOFF_TX_TH_WIDTH 5
1420 #define	FRF_AA_RX_OWNERR_CTL_LBN 30
1421 #define	FRF_AA_RX_OWNERR_CTL_WIDTH 1
1422 #define	FRF_AA_RX_XON_TX_TH_LBN 25
1423 #define	FRF_AA_RX_XON_TX_TH_WIDTH 5
1424 #define	FRF_BZ_RX_USR_BUF_SIZE_LBN 19
1425 #define	FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9
1426 #define	FRF_AA_RX_XOFF_TX_TH_LBN 20
1427 #define	FRF_AA_RX_XOFF_TX_TH_WIDTH 5
1428 #define	FRF_AA_RX_USR_BUF_SIZE_LBN 11
1429 #define	FRF_AA_RX_USR_BUF_SIZE_WIDTH 9
1430 #define	FRF_BZ_RX_XON_MAC_TH_LBN 10
1431 #define	FRF_BZ_RX_XON_MAC_TH_WIDTH 9
1432 #define	FRF_AA_RX_XON_MAC_TH_LBN 6
1433 #define	FRF_AA_RX_XON_MAC_TH_WIDTH 5
1434 #define	FRF_BZ_RX_XOFF_MAC_TH_LBN 1
1435 #define	FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9
1436 #define	FRF_AA_RX_XOFF_MAC_TH_LBN 1
1437 #define	FRF_AA_RX_XOFF_MAC_TH_WIDTH 5
1438 #define	FRF_AZ_RX_XOFF_MAC_EN_LBN 0
1439 #define	FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1
1440 
1441 
1442 /*
1443  * FR_AZ_RX_FILTER_CTL_REG(128bit):
1444  * Receive filter control registers
1445  */
1446 #define	FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810
1447 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1448 
1449 #define	FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94
1450 #define	FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8
1451 #define	FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86
1452 #define	FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8
1453 #define	FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85
1454 #define	FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1
1455 #define	FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69
1456 #define	FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16
1457 #define	FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57
1458 #define	FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12
1459 #define	FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56
1460 #define	FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1461 #define	FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55
1462 #define	FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1463 #define	FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43
1464 #define	FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12
1465 #define	FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42
1466 #define	FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1467 #define	FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41
1468 #define	FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1469 #define	FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40
1470 #define	FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1
1471 #define	FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32
1472 #define	FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8
1473 #define	FRF_AZ_NUM_KER_LBN 24
1474 #define	FRF_AZ_NUM_KER_WIDTH 2
1475 #define	FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16
1476 #define	FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8
1477 #define	FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8
1478 #define	FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8
1479 #define	FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0
1480 #define	FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8
1481 
1482 
1483 /*
1484  * FR_AZ_RX_FLUSH_DESCQ_REG(128bit):
1485  * Receive flush descriptor queue register
1486  */
1487 #define	FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820
1488 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1489 
1490 #define	FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24
1491 #define	FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1
1492 #define	FRF_AZ_RX_FLUSH_DESCQ_LBN 0
1493 #define	FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12
1494 
1495 
1496 /*
1497  * FR_BZ_RX_DESC_UPD_REGP0(128bit):
1498  * Receive descriptor update register.
1499  */
1500 #define	FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830
1501 /* falconb0,sienaa0=net_func_bar2 */
1502 #define	FR_BZ_RX_DESC_UPD_REGP0_STEP 8192
1503 #define	FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024
1504 /*
1505  * FR_AA_RX_DESC_UPD_REG_KER(128bit):
1506  * Receive descriptor update register.
1507  */
1508 #define	FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830
1509 /* falcona0=net_func_bar2 */
1510 #define	FR_AA_RX_DESC_UPD_REG_KER_STEP 8192
1511 #define	FR_AA_RX_DESC_UPD_REG_KER_ROWS 4
1512 /*
1513  * FR_AB_RX_DESC_UPD_REGP123(128bit):
1514  * Receive descriptor update register.
1515  */
1516 #define	FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830
1517 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
1518 #define	FR_AB_RX_DESC_UPD_REGP123_STEP 8192
1519 #define	FR_AB_RX_DESC_UPD_REGP123_ROWS 3072
1520 /*
1521  * FR_AA_RX_DESC_UPD_REGP0(128bit):
1522  * Receive descriptor update register.
1523  */
1524 #define	FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830
1525 /* falcona0=char_func_bar0 */
1526 #define	FR_AA_RX_DESC_UPD_REGP0_STEP 8192
1527 #define	FR_AA_RX_DESC_UPD_REGP0_ROWS 1020
1528 
1529 #define	FRF_AZ_RX_DESC_WPTR_LBN 96
1530 #define	FRF_AZ_RX_DESC_WPTR_WIDTH 12
1531 #define	FRF_AZ_RX_DESC_PUSH_CMD_LBN 95
1532 #define	FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1
1533 #define	FRF_AZ_RX_DESC_LBN 0
1534 #define	FRF_AZ_RX_DESC_WIDTH 64
1535 #define	FRF_AZ_RX_DESC_DW0_LBN 0
1536 #define	FRF_AZ_RX_DESC_DW0_WIDTH 32
1537 #define	FRF_AZ_RX_DESC_DW1_LBN 32
1538 #define	FRF_AZ_RX_DESC_DW1_WIDTH 32
1539 
1540 
1541 /*
1542  * FR_AZ_RX_DC_CFG_REG(128bit):
1543  * Receive descriptor cache configuration register
1544  */
1545 #define	FR_AZ_RX_DC_CFG_REG_OFST 0x00000840
1546 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1547 
1548 #define	FRF_AZ_RX_MAX_PF_LBN 2
1549 #define	FRF_AZ_RX_MAX_PF_WIDTH 2
1550 #define	FRF_AZ_RX_DC_SIZE_LBN 0
1551 #define	FRF_AZ_RX_DC_SIZE_WIDTH 2
1552 #define	FFE_AZ_RX_DC_SIZE_64 3
1553 #define	FFE_AZ_RX_DC_SIZE_32 2
1554 #define	FFE_AZ_RX_DC_SIZE_16 1
1555 #define	FFE_AZ_RX_DC_SIZE_8 0
1556 
1557 
1558 /*
1559  * FR_AZ_RX_DC_PF_WM_REG(128bit):
1560  * Receive descriptor cache pre-fetch watermark register
1561  */
1562 #define	FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850
1563 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1564 
1565 #define	FRF_AZ_RX_DC_PF_HWM_LBN 6
1566 #define	FRF_AZ_RX_DC_PF_HWM_WIDTH 6
1567 #define	FRF_AZ_RX_DC_PF_LWM_LBN 0
1568 #define	FRF_AZ_RX_DC_PF_LWM_WIDTH 6
1569 
1570 
1571 /*
1572  * FR_BZ_RX_RSS_TKEY_REG(128bit):
1573  * RSS Toeplitz hash key
1574  */
1575 #define	FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860
1576 /* falconb0,sienaa0=net_func_bar2 */
1577 
1578 #define	FRF_BZ_RX_RSS_TKEY_LBN 96
1579 #define	FRF_BZ_RX_RSS_TKEY_WIDTH 32
1580 #define	FRF_BZ_RX_RSS_TKEY_DW3_LBN 96
1581 #define	FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32
1582 #define	FRF_BZ_RX_RSS_TKEY_DW2_LBN 64
1583 #define	FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32
1584 #define	FRF_BZ_RX_RSS_TKEY_DW1_LBN 32
1585 #define	FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32
1586 #define	FRF_BZ_RX_RSS_TKEY_DW0_LBN 0
1587 #define	FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32
1588 
1589 
1590 /*
1591  * FR_AZ_RX_NODESC_DROP_REG(128bit):
1592  * Receive dropped packet counter register
1593  */
1594 #define	FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880
1595 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1596 
1597 #define	FRF_AZ_RX_NODESC_DROP_CNT_LBN 0
1598 #define	FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16
1599 
1600 
1601 /*
1602  * FR_AZ_RX_SELF_RST_REG(128bit):
1603  * Receive self reset register
1604  */
1605 #define	FR_AZ_RX_SELF_RST_REG_OFST 0x00000890
1606 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1607 
1608 #define	FRF_AZ_RX_ISCSI_DIS_LBN 17
1609 #define	FRF_AZ_RX_ISCSI_DIS_WIDTH 1
1610 #define	FRF_AB_RX_SW_RST_REG_LBN 16
1611 #define	FRF_AB_RX_SW_RST_REG_WIDTH 1
1612 #define	FRF_AB_RX_SELF_RST_EN_LBN 8
1613 #define	FRF_AB_RX_SELF_RST_EN_WIDTH 1
1614 #define	FRF_AZ_RX_MAX_PF_LAT_LBN 4
1615 #define	FRF_AZ_RX_MAX_PF_LAT_WIDTH 4
1616 #define	FRF_AZ_RX_MAX_LU_LAT_LBN 0
1617 #define	FRF_AZ_RX_MAX_LU_LAT_WIDTH 4
1618 
1619 
1620 /*
1621  * FR_AZ_RX_DEBUG_REG(128bit):
1622  * undocumented register
1623  */
1624 #define	FR_AZ_RX_DEBUG_REG_OFST 0x000008a0
1625 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1626 
1627 #define	FRF_AZ_RX_DEBUG_LBN 0
1628 #define	FRF_AZ_RX_DEBUG_WIDTH 64
1629 #define	FRF_AZ_RX_DEBUG_DW0_LBN 0
1630 #define	FRF_AZ_RX_DEBUG_DW0_WIDTH 32
1631 #define	FRF_AZ_RX_DEBUG_DW1_LBN 32
1632 #define	FRF_AZ_RX_DEBUG_DW1_WIDTH 32
1633 
1634 
1635 /*
1636  * FR_AZ_RX_PUSH_DROP_REG(128bit):
1637  * Receive descriptor push dropped counter register
1638  */
1639 #define	FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0
1640 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1641 
1642 #define	FRF_AZ_RX_PUSH_DROP_CNT_LBN 0
1643 #define	FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32
1644 
1645 
1646 /*
1647  * FR_CZ_RX_RSS_IPV6_REG1(128bit):
1648  * IPv6 RSS Toeplitz hash key low bytes
1649  */
1650 #define	FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0
1651 /* sienaa0=net_func_bar2 */
1652 
1653 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0
1654 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128
1655 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0
1656 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32
1657 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32
1658 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32
1659 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64
1660 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32
1661 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96
1662 #define	FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32
1663 
1664 
1665 /*
1666  * FR_CZ_RX_RSS_IPV6_REG2(128bit):
1667  * IPv6 RSS Toeplitz hash key middle bytes
1668  */
1669 #define	FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0
1670 /* sienaa0=net_func_bar2 */
1671 
1672 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0
1673 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128
1674 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0
1675 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32
1676 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32
1677 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32
1678 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64
1679 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32
1680 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96
1681 #define	FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32
1682 
1683 
1684 /*
1685  * FR_CZ_RX_RSS_IPV6_REG3(128bit):
1686  * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings
1687  */
1688 #define	FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0
1689 /* sienaa0=net_func_bar2 */
1690 
1691 #define	FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66
1692 #define	FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1
1693 #define	FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65
1694 #define	FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1
1695 #define	FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64
1696 #define	FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1
1697 #define	FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0
1698 #define	FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64
1699 #define	FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0
1700 #define	FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32
1701 #define	FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32
1702 #define	FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32
1703 
1704 
1705 /*
1706  * FR_AZ_TX_FLUSH_DESCQ_REG(128bit):
1707  * Transmit flush descriptor queue register
1708  */
1709 #define	FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00
1710 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1711 
1712 #define	FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12
1713 #define	FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1
1714 #define	FRF_AZ_TX_FLUSH_DESCQ_LBN 0
1715 #define	FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12
1716 
1717 
1718 /*
1719  * FR_BZ_TX_DESC_UPD_REGP0(128bit):
1720  * Transmit descriptor update register.
1721  */
1722 #define	FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10
1723 /* falconb0,sienaa0=net_func_bar2 */
1724 #define	FR_BZ_TX_DESC_UPD_REGP0_STEP 8192
1725 #define	FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024
1726 /*
1727  * FR_AA_TX_DESC_UPD_REG_KER(128bit):
1728  * Transmit descriptor update register.
1729  */
1730 #define	FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10
1731 /* falcona0=net_func_bar2 */
1732 #define	FR_AA_TX_DESC_UPD_REG_KER_STEP 8192
1733 #define	FR_AA_TX_DESC_UPD_REG_KER_ROWS 8
1734 /*
1735  * FR_AB_TX_DESC_UPD_REGP123(128bit):
1736  * Transmit descriptor update register.
1737  */
1738 #define	FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10
1739 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
1740 #define	FR_AB_TX_DESC_UPD_REGP123_STEP 8192
1741 #define	FR_AB_TX_DESC_UPD_REGP123_ROWS 3072
1742 /*
1743  * FR_AA_TX_DESC_UPD_REGP0(128bit):
1744  * Transmit descriptor update register.
1745  */
1746 #define	FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10
1747 /* falcona0=char_func_bar0 */
1748 #define	FR_AA_TX_DESC_UPD_REGP0_STEP 8192
1749 #define	FR_AA_TX_DESC_UPD_REGP0_ROWS 1020
1750 
1751 #define	FRF_AZ_TX_DESC_WPTR_LBN 96
1752 #define	FRF_AZ_TX_DESC_WPTR_WIDTH 12
1753 #define	FRF_AZ_TX_DESC_PUSH_CMD_LBN 95
1754 #define	FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1
1755 #define	FRF_AZ_TX_DESC_LBN 0
1756 #define	FRF_AZ_TX_DESC_WIDTH 95
1757 #define	FRF_AZ_TX_DESC_DW0_LBN 0
1758 #define	FRF_AZ_TX_DESC_DW0_WIDTH 32
1759 #define	FRF_AZ_TX_DESC_DW1_LBN 32
1760 #define	FRF_AZ_TX_DESC_DW1_WIDTH 32
1761 #define	FRF_AZ_TX_DESC_DW2_LBN 64
1762 #define	FRF_AZ_TX_DESC_DW2_WIDTH 31
1763 
1764 
1765 /*
1766  * FR_AZ_TX_DC_CFG_REG(128bit):
1767  * Transmit descriptor cache configuration register
1768  */
1769 #define	FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20
1770 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1771 
1772 #define	FRF_AZ_TX_DC_SIZE_LBN 0
1773 #define	FRF_AZ_TX_DC_SIZE_WIDTH 2
1774 #define	FFE_AZ_TX_DC_SIZE_32 2
1775 #define	FFE_AZ_TX_DC_SIZE_16 1
1776 #define	FFE_AZ_TX_DC_SIZE_8 0
1777 
1778 
1779 /*
1780  * FR_AA_TX_CHKSM_CFG_REG(128bit):
1781  * Transmit checksum configuration register
1782  */
1783 #define	FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30
1784 /* falcona0=net_func_bar2,falcona0=char_func_bar0 */
1785 
1786 #define	FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96
1787 #define	FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32
1788 #define	FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64
1789 #define	FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32
1790 #define	FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32
1791 #define	FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32
1792 #define	FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0
1793 #define	FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32
1794 
1795 
1796 /*
1797  * FR_AZ_TX_CFG_REG(128bit):
1798  * Transmit configuration register
1799  */
1800 #define	FR_AZ_TX_CFG_REG_OFST 0x00000a50
1801 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1802 
1803 #define	FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114
1804 #define	FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8
1805 #define	FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113
1806 #define	FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1
1807 #define	FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105
1808 #define	FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1809 #define	FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97
1810 #define	FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1811 #define	FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89
1812 #define	FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1813 #define	FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81
1814 #define	FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1815 #define	FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73
1816 #define	FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1817 #define	FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65
1818 #define	FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1819 #define	FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64
1820 #define	FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1
1821 #define	FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48
1822 #define	FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16
1823 #define	FRF_CZ_TX_FILTER_EN_BIT_LBN 47
1824 #define	FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1
1825 #define	FRF_AZ_TX_IP_ID_P0_OFS_LBN 16
1826 #define	FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15
1827 #define	FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5
1828 #define	FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1
1829 #define	FRF_AZ_TX_P1_PRI_EN_LBN 4
1830 #define	FRF_AZ_TX_P1_PRI_EN_WIDTH 1
1831 #define	FRF_AZ_TX_OWNERR_CTL_LBN 2
1832 #define	FRF_AZ_TX_OWNERR_CTL_WIDTH 1
1833 #define	FRF_AA_TX_NON_IP_DROP_DIS_LBN 1
1834 #define	FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1
1835 #define	FRF_AZ_TX_IP_ID_REP_EN_LBN 0
1836 #define	FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1
1837 
1838 
1839 /*
1840  * FR_AZ_TX_PUSH_DROP_REG(128bit):
1841  * Transmit push dropped register
1842  */
1843 #define	FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60
1844 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1845 
1846 #define	FRF_AZ_TX_PUSH_DROP_CNT_LBN 0
1847 #define	FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32
1848 
1849 
1850 /*
1851  * FR_AZ_TX_RESERVED_REG(128bit):
1852  * Transmit configuration register
1853  */
1854 #define	FR_AZ_TX_RESERVED_REG_OFST 0x00000a80
1855 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1856 
1857 #define	FRF_AZ_TX_EVT_CNT_LBN 121
1858 #define	FRF_AZ_TX_EVT_CNT_WIDTH 7
1859 #define	FRF_AZ_TX_PREF_AGE_CNT_LBN 119
1860 #define	FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2
1861 #define	FRF_AZ_TX_RD_COMP_TMR_LBN 96
1862 #define	FRF_AZ_TX_RD_COMP_TMR_WIDTH 23
1863 #define	FRF_AZ_TX_PUSH_EN_LBN 89
1864 #define	FRF_AZ_TX_PUSH_EN_WIDTH 1
1865 #define	FRF_AZ_TX_PUSH_CHK_DIS_LBN 88
1866 #define	FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1
1867 #define	FRF_AZ_TX_D_FF_FULL_P0_LBN 85
1868 #define	FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1
1869 #define	FRF_AZ_TX_DMAR_ST_P0_LBN 81
1870 #define	FRF_AZ_TX_DMAR_ST_P0_WIDTH 1
1871 #define	FRF_AZ_TX_DMAQ_ST_LBN 78
1872 #define	FRF_AZ_TX_DMAQ_ST_WIDTH 1
1873 #define	FRF_AZ_TX_RX_SPACER_LBN 64
1874 #define	FRF_AZ_TX_RX_SPACER_WIDTH 8
1875 #define	FRF_AZ_TX_DROP_ABORT_EN_LBN 60
1876 #define	FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1
1877 #define	FRF_AZ_TX_SOFT_EVT_EN_LBN 59
1878 #define	FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1
1879 #define	FRF_AZ_TX_PS_EVT_DIS_LBN 58
1880 #define	FRF_AZ_TX_PS_EVT_DIS_WIDTH 1
1881 #define	FRF_AZ_TX_RX_SPACER_EN_LBN 57
1882 #define	FRF_AZ_TX_RX_SPACER_EN_WIDTH 1
1883 #define	FRF_AZ_TX_XP_TIMER_LBN 52
1884 #define	FRF_AZ_TX_XP_TIMER_WIDTH 5
1885 #define	FRF_AZ_TX_PREF_SPACER_LBN 44
1886 #define	FRF_AZ_TX_PREF_SPACER_WIDTH 8
1887 #define	FRF_AZ_TX_PREF_WD_TMR_LBN 22
1888 #define	FRF_AZ_TX_PREF_WD_TMR_WIDTH 22
1889 #define	FRF_AZ_TX_ONLY1TAG_LBN 21
1890 #define	FRF_AZ_TX_ONLY1TAG_WIDTH 1
1891 #define	FRF_AZ_TX_PREF_THRESHOLD_LBN 19
1892 #define	FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2
1893 #define	FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18
1894 #define	FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1
1895 #define	FRF_AZ_TX_DIS_NON_IP_EV_LBN 17
1896 #define	FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1
1897 #define	FRF_AA_TX_DMA_FF_THR_LBN 16
1898 #define	FRF_AA_TX_DMA_FF_THR_WIDTH 1
1899 #define	FRF_AZ_TX_DMA_SPACER_LBN 8
1900 #define	FRF_AZ_TX_DMA_SPACER_WIDTH 8
1901 #define	FRF_AA_TX_TCP_DIS_LBN 7
1902 #define	FRF_AA_TX_TCP_DIS_WIDTH 1
1903 #define	FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7
1904 #define	FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1
1905 #define	FRF_AA_TX_IP_DIS_LBN 6
1906 #define	FRF_AA_TX_IP_DIS_WIDTH 1
1907 #define	FRF_AZ_TX_MAX_CPL_LBN 2
1908 #define	FRF_AZ_TX_MAX_CPL_WIDTH 2
1909 #define	FFE_AZ_TX_MAX_CPL_16 3
1910 #define	FFE_AZ_TX_MAX_CPL_8 2
1911 #define	FFE_AZ_TX_MAX_CPL_4 1
1912 #define	FFE_AZ_TX_MAX_CPL_NOLIMIT 0
1913 #define	FRF_AZ_TX_MAX_PREF_LBN 0
1914 #define	FRF_AZ_TX_MAX_PREF_WIDTH 2
1915 #define	FFE_AZ_TX_MAX_PREF_32 3
1916 #define	FFE_AZ_TX_MAX_PREF_16 2
1917 #define	FFE_AZ_TX_MAX_PREF_8 1
1918 #define	FFE_AZ_TX_MAX_PREF_OFF 0
1919 
1920 
1921 /*
1922  * FR_BZ_TX_PACE_REG(128bit):
1923  * Transmit pace control register
1924  */
1925 #define	FR_BZ_TX_PACE_REG_OFST 0x00000a90
1926 /* falconb0,sienaa0=net_func_bar2 */
1927 /*
1928  * FR_AA_TX_PACE_REG(128bit):
1929  * Transmit pace control register
1930  */
1931 #define	FR_AA_TX_PACE_REG_OFST 0x00f80000
1932 /* falcona0=char_func_bar0 */
1933 
1934 #define	FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19
1935 #define	FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10
1936 #define	FRF_AZ_TX_PACE_SB_AF_LBN 9
1937 #define	FRF_AZ_TX_PACE_SB_AF_WIDTH 10
1938 #define	FRF_AZ_TX_PACE_FB_BASE_LBN 5
1939 #define	FRF_AZ_TX_PACE_FB_BASE_WIDTH 4
1940 #define	FRF_AZ_TX_PACE_BIN_TH_LBN 0
1941 #define	FRF_AZ_TX_PACE_BIN_TH_WIDTH 5
1942 
1943 
1944 /*
1945  * FR_AZ_TX_PACE_DROP_QID_REG(128bit):
1946  * PACE Drop QID Counter
1947  */
1948 #define	FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0
1949 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1950 
1951 #define	FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0
1952 #define	FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16
1953 
1954 
1955 /*
1956  * FR_AB_TX_VLAN_REG(128bit):
1957  * Transmit VLAN tag register
1958  */
1959 #define	FR_AB_TX_VLAN_REG_OFST 0x00000ae0
1960 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
1961 
1962 #define	FRF_AB_TX_VLAN_EN_LBN 127
1963 #define	FRF_AB_TX_VLAN_EN_WIDTH 1
1964 #define	FRF_AB_TX_VLAN7_PORT1_EN_LBN 125
1965 #define	FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1
1966 #define	FRF_AB_TX_VLAN7_PORT0_EN_LBN 124
1967 #define	FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1
1968 #define	FRF_AB_TX_VLAN7_LBN 112
1969 #define	FRF_AB_TX_VLAN7_WIDTH 12
1970 #define	FRF_AB_TX_VLAN6_PORT1_EN_LBN 109
1971 #define	FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1
1972 #define	FRF_AB_TX_VLAN6_PORT0_EN_LBN 108
1973 #define	FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1
1974 #define	FRF_AB_TX_VLAN6_LBN 96
1975 #define	FRF_AB_TX_VLAN6_WIDTH 12
1976 #define	FRF_AB_TX_VLAN5_PORT1_EN_LBN 93
1977 #define	FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1
1978 #define	FRF_AB_TX_VLAN5_PORT0_EN_LBN 92
1979 #define	FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1
1980 #define	FRF_AB_TX_VLAN5_LBN 80
1981 #define	FRF_AB_TX_VLAN5_WIDTH 12
1982 #define	FRF_AB_TX_VLAN4_PORT1_EN_LBN 77
1983 #define	FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1
1984 #define	FRF_AB_TX_VLAN4_PORT0_EN_LBN 76
1985 #define	FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1
1986 #define	FRF_AB_TX_VLAN4_LBN 64
1987 #define	FRF_AB_TX_VLAN4_WIDTH 12
1988 #define	FRF_AB_TX_VLAN3_PORT1_EN_LBN 61
1989 #define	FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1
1990 #define	FRF_AB_TX_VLAN3_PORT0_EN_LBN 60
1991 #define	FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1
1992 #define	FRF_AB_TX_VLAN3_LBN 48
1993 #define	FRF_AB_TX_VLAN3_WIDTH 12
1994 #define	FRF_AB_TX_VLAN2_PORT1_EN_LBN 45
1995 #define	FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1
1996 #define	FRF_AB_TX_VLAN2_PORT0_EN_LBN 44
1997 #define	FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1
1998 #define	FRF_AB_TX_VLAN2_LBN 32
1999 #define	FRF_AB_TX_VLAN2_WIDTH 12
2000 #define	FRF_AB_TX_VLAN1_PORT1_EN_LBN 29
2001 #define	FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1
2002 #define	FRF_AB_TX_VLAN1_PORT0_EN_LBN 28
2003 #define	FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1
2004 #define	FRF_AB_TX_VLAN1_LBN 16
2005 #define	FRF_AB_TX_VLAN1_WIDTH 12
2006 #define	FRF_AB_TX_VLAN0_PORT1_EN_LBN 13
2007 #define	FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1
2008 #define	FRF_AB_TX_VLAN0_PORT0_EN_LBN 12
2009 #define	FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1
2010 #define	FRF_AB_TX_VLAN0_LBN 0
2011 #define	FRF_AB_TX_VLAN0_WIDTH 12
2012 
2013 
2014 /*
2015  * FR_AZ_TX_IPFIL_PORTEN_REG(128bit):
2016  * Transmit filter control register
2017  */
2018 #define	FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0
2019 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
2020 
2021 #define	FRF_AZ_TX_MADR0_FIL_EN_LBN 64
2022 #define	FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1
2023 #define	FRF_AB_TX_IPFIL31_PORT_EN_LBN 62
2024 #define	FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1
2025 #define	FRF_AB_TX_IPFIL30_PORT_EN_LBN 60
2026 #define	FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1
2027 #define	FRF_AB_TX_IPFIL29_PORT_EN_LBN 58
2028 #define	FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1
2029 #define	FRF_AB_TX_IPFIL28_PORT_EN_LBN 56
2030 #define	FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1
2031 #define	FRF_AB_TX_IPFIL27_PORT_EN_LBN 54
2032 #define	FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1
2033 #define	FRF_AB_TX_IPFIL26_PORT_EN_LBN 52
2034 #define	FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1
2035 #define	FRF_AB_TX_IPFIL25_PORT_EN_LBN 50
2036 #define	FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1
2037 #define	FRF_AB_TX_IPFIL24_PORT_EN_LBN 48
2038 #define	FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1
2039 #define	FRF_AB_TX_IPFIL23_PORT_EN_LBN 46
2040 #define	FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1
2041 #define	FRF_AB_TX_IPFIL22_PORT_EN_LBN 44
2042 #define	FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1
2043 #define	FRF_AB_TX_IPFIL21_PORT_EN_LBN 42
2044 #define	FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1
2045 #define	FRF_AB_TX_IPFIL20_PORT_EN_LBN 40
2046 #define	FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1
2047 #define	FRF_AB_TX_IPFIL19_PORT_EN_LBN 38
2048 #define	FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1
2049 #define	FRF_AB_TX_IPFIL18_PORT_EN_LBN 36
2050 #define	FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1
2051 #define	FRF_AB_TX_IPFIL17_PORT_EN_LBN 34
2052 #define	FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1
2053 #define	FRF_AB_TX_IPFIL16_PORT_EN_LBN 32
2054 #define	FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1
2055 #define	FRF_AB_TX_IPFIL15_PORT_EN_LBN 30
2056 #define	FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1
2057 #define	FRF_AB_TX_IPFIL14_PORT_EN_LBN 28
2058 #define	FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1
2059 #define	FRF_AB_TX_IPFIL13_PORT_EN_LBN 26
2060 #define	FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1
2061 #define	FRF_AB_TX_IPFIL12_PORT_EN_LBN 24
2062 #define	FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1
2063 #define	FRF_AB_TX_IPFIL11_PORT_EN_LBN 22
2064 #define	FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1
2065 #define	FRF_AB_TX_IPFIL10_PORT_EN_LBN 20
2066 #define	FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1
2067 #define	FRF_AB_TX_IPFIL9_PORT_EN_LBN 18
2068 #define	FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1
2069 #define	FRF_AB_TX_IPFIL8_PORT_EN_LBN 16
2070 #define	FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1
2071 #define	FRF_AB_TX_IPFIL7_PORT_EN_LBN 14
2072 #define	FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1
2073 #define	FRF_AB_TX_IPFIL6_PORT_EN_LBN 12
2074 #define	FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1
2075 #define	FRF_AB_TX_IPFIL5_PORT_EN_LBN 10
2076 #define	FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1
2077 #define	FRF_AB_TX_IPFIL4_PORT_EN_LBN 8
2078 #define	FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1
2079 #define	FRF_AB_TX_IPFIL3_PORT_EN_LBN 6
2080 #define	FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1
2081 #define	FRF_AB_TX_IPFIL2_PORT_EN_LBN 4
2082 #define	FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1
2083 #define	FRF_AB_TX_IPFIL1_PORT_EN_LBN 2
2084 #define	FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1
2085 #define	FRF_AB_TX_IPFIL0_PORT_EN_LBN 0
2086 #define	FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1
2087 
2088 
2089 /*
2090  * FR_AB_TX_IPFIL_TBL(128bit):
2091  * Transmit IP source address filter table
2092  */
2093 #define	FR_AB_TX_IPFIL_TBL_OFST 0x00000b00
2094 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
2095 #define	FR_AB_TX_IPFIL_TBL_STEP 16
2096 #define	FR_AB_TX_IPFIL_TBL_ROWS 16
2097 
2098 #define	FRF_AB_TX_IPFIL_MASK_1_LBN 96
2099 #define	FRF_AB_TX_IPFIL_MASK_1_WIDTH 32
2100 #define	FRF_AB_TX_IP_SRC_ADR_1_LBN 64
2101 #define	FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32
2102 #define	FRF_AB_TX_IPFIL_MASK_0_LBN 32
2103 #define	FRF_AB_TX_IPFIL_MASK_0_WIDTH 32
2104 #define	FRF_AB_TX_IP_SRC_ADR_0_LBN 0
2105 #define	FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32
2106 
2107 
2108 /*
2109  * FR_AB_MD_TXD_REG(128bit):
2110  * PHY management transmit data register
2111  */
2112 #define	FR_AB_MD_TXD_REG_OFST 0x00000c00
2113 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2114 
2115 #define	FRF_AB_MD_TXD_LBN 0
2116 #define	FRF_AB_MD_TXD_WIDTH 16
2117 
2118 
2119 /*
2120  * FR_AB_MD_RXD_REG(128bit):
2121  * PHY management receive data register
2122  */
2123 #define	FR_AB_MD_RXD_REG_OFST 0x00000c10
2124 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2125 
2126 #define	FRF_AB_MD_RXD_LBN 0
2127 #define	FRF_AB_MD_RXD_WIDTH 16
2128 
2129 
2130 /*
2131  * FR_AB_MD_CS_REG(128bit):
2132  * PHY management configuration & status register
2133  */
2134 #define	FR_AB_MD_CS_REG_OFST 0x00000c20
2135 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2136 
2137 #define	FRF_AB_MD_RD_EN_LBN 15
2138 #define	FRF_AB_MD_RD_EN_WIDTH 1
2139 #define	FRF_AB_MD_WR_EN_LBN 14
2140 #define	FRF_AB_MD_WR_EN_WIDTH 1
2141 #define	FRF_AB_MD_ADDR_CMD_LBN 13
2142 #define	FRF_AB_MD_ADDR_CMD_WIDTH 1
2143 #define	FRF_AB_MD_PT_LBN 7
2144 #define	FRF_AB_MD_PT_WIDTH 3
2145 #define	FRF_AB_MD_PL_LBN 6
2146 #define	FRF_AB_MD_PL_WIDTH 1
2147 #define	FRF_AB_MD_INT_CLR_LBN 5
2148 #define	FRF_AB_MD_INT_CLR_WIDTH 1
2149 #define	FRF_AB_MD_GC_LBN 4
2150 #define	FRF_AB_MD_GC_WIDTH 1
2151 #define	FRF_AB_MD_PRSP_LBN 3
2152 #define	FRF_AB_MD_PRSP_WIDTH 1
2153 #define	FRF_AB_MD_RIC_LBN 2
2154 #define	FRF_AB_MD_RIC_WIDTH 1
2155 #define	FRF_AB_MD_RDC_LBN 1
2156 #define	FRF_AB_MD_RDC_WIDTH 1
2157 #define	FRF_AB_MD_WRC_LBN 0
2158 #define	FRF_AB_MD_WRC_WIDTH 1
2159 
2160 
2161 /*
2162  * FR_AB_MD_PHY_ADR_REG(128bit):
2163  * PHY management PHY address register
2164  */
2165 #define	FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30
2166 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2167 
2168 #define	FRF_AB_MD_PHY_ADR_LBN 0
2169 #define	FRF_AB_MD_PHY_ADR_WIDTH 16
2170 
2171 
2172 /*
2173  * FR_AB_MD_ID_REG(128bit):
2174  * PHY management ID register
2175  */
2176 #define	FR_AB_MD_ID_REG_OFST 0x00000c40
2177 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2178 
2179 #define	FRF_AB_MD_PRT_ADR_LBN 11
2180 #define	FRF_AB_MD_PRT_ADR_WIDTH 5
2181 #define	FRF_AB_MD_DEV_ADR_LBN 6
2182 #define	FRF_AB_MD_DEV_ADR_WIDTH 5
2183 
2184 
2185 /*
2186  * FR_AB_MD_STAT_REG(128bit):
2187  * PHY management status & mask register
2188  */
2189 #define	FR_AB_MD_STAT_REG_OFST 0x00000c50
2190 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2191 
2192 #define	FRF_AB_MD_PINT_LBN 4
2193 #define	FRF_AB_MD_PINT_WIDTH 1
2194 #define	FRF_AB_MD_DONE_LBN 3
2195 #define	FRF_AB_MD_DONE_WIDTH 1
2196 #define	FRF_AB_MD_BSERR_LBN 2
2197 #define	FRF_AB_MD_BSERR_WIDTH 1
2198 #define	FRF_AB_MD_LNFL_LBN 1
2199 #define	FRF_AB_MD_LNFL_WIDTH 1
2200 #define	FRF_AB_MD_BSY_LBN 0
2201 #define	FRF_AB_MD_BSY_WIDTH 1
2202 
2203 
2204 /*
2205  * FR_AB_MAC_STAT_DMA_REG(128bit):
2206  * Port MAC statistical counter DMA register
2207  */
2208 #define	FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60
2209 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2210 
2211 #define	FRF_AB_MAC_STAT_DMA_CMD_LBN 48
2212 #define	FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1
2213 #define	FRF_AB_MAC_STAT_DMA_ADR_LBN 0
2214 #define	FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48
2215 #define	FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0
2216 #define	FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32
2217 #define	FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32
2218 #define	FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16
2219 
2220 
2221 /*
2222  * FR_AB_MAC_CTRL_REG(128bit):
2223  * Port MAC control register
2224  */
2225 #define	FR_AB_MAC_CTRL_REG_OFST 0x00000c80
2226 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2227 
2228 #define	FRF_AB_MAC_XOFF_VAL_LBN 16
2229 #define	FRF_AB_MAC_XOFF_VAL_WIDTH 16
2230 #define	FRF_BB_TXFIFO_DRAIN_EN_LBN 7
2231 #define	FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1
2232 #define	FRF_AB_MAC_XG_DISTXCRC_LBN 5
2233 #define	FRF_AB_MAC_XG_DISTXCRC_WIDTH 1
2234 #define	FRF_AB_MAC_BCAD_ACPT_LBN 4
2235 #define	FRF_AB_MAC_BCAD_ACPT_WIDTH 1
2236 #define	FRF_AB_MAC_UC_PROM_LBN 3
2237 #define	FRF_AB_MAC_UC_PROM_WIDTH 1
2238 #define	FRF_AB_MAC_LINK_STATUS_LBN 2
2239 #define	FRF_AB_MAC_LINK_STATUS_WIDTH 1
2240 #define	FRF_AB_MAC_SPEED_LBN 0
2241 #define	FRF_AB_MAC_SPEED_WIDTH 2
2242 #define	FRF_AB_MAC_SPEED_10M 0
2243 #define	FRF_AB_MAC_SPEED_100M 1
2244 #define	FRF_AB_MAC_SPEED_1G 2
2245 #define	FRF_AB_MAC_SPEED_10G 3
2246 
2247 /*
2248  * FR_BB_GEN_MODE_REG(128bit):
2249  * General Purpose mode register (external interrupt mask)
2250  */
2251 #define	FR_BB_GEN_MODE_REG_OFST 0x00000c90
2252 /* falconb0=net_func_bar2 */
2253 
2254 #define	FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3
2255 #define	FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1
2256 #define	FRF_BB_XG_PHY_INT_POL_SEL_LBN 2
2257 #define	FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1
2258 #define	FRF_BB_XFP_PHY_INT_MASK_LBN 1
2259 #define	FRF_BB_XFP_PHY_INT_MASK_WIDTH 1
2260 #define	FRF_BB_XG_PHY_INT_MASK_LBN 0
2261 #define	FRF_BB_XG_PHY_INT_MASK_WIDTH 1
2262 
2263 
2264 /*
2265  * FR_AB_MAC_MC_HASH_REG0(128bit):
2266  * Multicast address hash table
2267  */
2268 #define	FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0
2269 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2270 
2271 #define	FRF_AB_MAC_MCAST_HASH0_LBN 0
2272 #define	FRF_AB_MAC_MCAST_HASH0_WIDTH 128
2273 #define	FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0
2274 #define	FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32
2275 #define	FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32
2276 #define	FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32
2277 #define	FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64
2278 #define	FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32
2279 #define	FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96
2280 #define	FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32
2281 
2282 
2283 /*
2284  * FR_AB_MAC_MC_HASH_REG1(128bit):
2285  * Multicast address hash table
2286  */
2287 #define	FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0
2288 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2289 
2290 #define	FRF_AB_MAC_MCAST_HASH1_LBN 0
2291 #define	FRF_AB_MAC_MCAST_HASH1_WIDTH 128
2292 #define	FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0
2293 #define	FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32
2294 #define	FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32
2295 #define	FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32
2296 #define	FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64
2297 #define	FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32
2298 #define	FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96
2299 #define	FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32
2300 
2301 
2302 /*
2303  * FR_AB_GM_CFG1_REG(32bit):
2304  * GMAC configuration register 1
2305  */
2306 #define	FR_AB_GM_CFG1_REG_OFST 0x00000e00
2307 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2308 
2309 #define	FRF_AB_GM_SW_RST_LBN 31
2310 #define	FRF_AB_GM_SW_RST_WIDTH 1
2311 #define	FRF_AB_GM_SIM_RST_LBN 30
2312 #define	FRF_AB_GM_SIM_RST_WIDTH 1
2313 #define	FRF_AB_GM_RST_RX_MAC_CTL_LBN 19
2314 #define	FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1
2315 #define	FRF_AB_GM_RST_TX_MAC_CTL_LBN 18
2316 #define	FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1
2317 #define	FRF_AB_GM_RST_RX_FUNC_LBN 17
2318 #define	FRF_AB_GM_RST_RX_FUNC_WIDTH 1
2319 #define	FRF_AB_GM_RST_TX_FUNC_LBN 16
2320 #define	FRF_AB_GM_RST_TX_FUNC_WIDTH 1
2321 #define	FRF_AB_GM_LOOP_LBN 8
2322 #define	FRF_AB_GM_LOOP_WIDTH 1
2323 #define	FRF_AB_GM_RX_FC_EN_LBN 5
2324 #define	FRF_AB_GM_RX_FC_EN_WIDTH 1
2325 #define	FRF_AB_GM_TX_FC_EN_LBN 4
2326 #define	FRF_AB_GM_TX_FC_EN_WIDTH 1
2327 #define	FRF_AB_GM_SYNC_RXEN_LBN 3
2328 #define	FRF_AB_GM_SYNC_RXEN_WIDTH 1
2329 #define	FRF_AB_GM_RX_EN_LBN 2
2330 #define	FRF_AB_GM_RX_EN_WIDTH 1
2331 #define	FRF_AB_GM_SYNC_TXEN_LBN 1
2332 #define	FRF_AB_GM_SYNC_TXEN_WIDTH 1
2333 #define	FRF_AB_GM_TX_EN_LBN 0
2334 #define	FRF_AB_GM_TX_EN_WIDTH 1
2335 
2336 
2337 /*
2338  * FR_AB_GM_CFG2_REG(32bit):
2339  * GMAC configuration register 2
2340  */
2341 #define	FR_AB_GM_CFG2_REG_OFST 0x00000e10
2342 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2343 
2344 #define	FRF_AB_GM_PAMBL_LEN_LBN 12
2345 #define	FRF_AB_GM_PAMBL_LEN_WIDTH 4
2346 #define	FRF_AB_GM_IF_MODE_LBN 8
2347 #define	FRF_AB_GM_IF_MODE_WIDTH 2
2348 #define	FRF_AB_GM_IF_MODE_BYTE_MODE 2
2349 #define	FRF_AB_GM_IF_MODE_NIBBLE_MODE 1
2350 #define	FRF_AB_GM_HUGE_FRM_EN_LBN 5
2351 #define	FRF_AB_GM_HUGE_FRM_EN_WIDTH 1
2352 #define	FRF_AB_GM_LEN_CHK_LBN 4
2353 #define	FRF_AB_GM_LEN_CHK_WIDTH 1
2354 #define	FRF_AB_GM_PAD_CRC_EN_LBN 2
2355 #define	FRF_AB_GM_PAD_CRC_EN_WIDTH 1
2356 #define	FRF_AB_GM_CRC_EN_LBN 1
2357 #define	FRF_AB_GM_CRC_EN_WIDTH 1
2358 #define	FRF_AB_GM_FD_LBN 0
2359 #define	FRF_AB_GM_FD_WIDTH 1
2360 
2361 
2362 /*
2363  * FR_AB_GM_IPG_REG(32bit):
2364  * GMAC IPG register
2365  */
2366 #define	FR_AB_GM_IPG_REG_OFST 0x00000e20
2367 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2368 
2369 #define	FRF_AB_GM_NONB2B_IPG1_LBN 24
2370 #define	FRF_AB_GM_NONB2B_IPG1_WIDTH 7
2371 #define	FRF_AB_GM_NONB2B_IPG2_LBN 16
2372 #define	FRF_AB_GM_NONB2B_IPG2_WIDTH 7
2373 #define	FRF_AB_GM_MIN_IPG_ENF_LBN 8
2374 #define	FRF_AB_GM_MIN_IPG_ENF_WIDTH 8
2375 #define	FRF_AB_GM_B2B_IPG_LBN 0
2376 #define	FRF_AB_GM_B2B_IPG_WIDTH 7
2377 
2378 
2379 /*
2380  * FR_AB_GM_HD_REG(32bit):
2381  * GMAC half duplex register
2382  */
2383 #define	FR_AB_GM_HD_REG_OFST 0x00000e30
2384 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2385 
2386 #define	FRF_AB_GM_ALT_BOFF_VAL_LBN 20
2387 #define	FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4
2388 #define	FRF_AB_GM_ALT_BOFF_EN_LBN 19
2389 #define	FRF_AB_GM_ALT_BOFF_EN_WIDTH 1
2390 #define	FRF_AB_GM_BP_NO_BOFF_LBN 18
2391 #define	FRF_AB_GM_BP_NO_BOFF_WIDTH 1
2392 #define	FRF_AB_GM_DIS_BOFF_LBN 17
2393 #define	FRF_AB_GM_DIS_BOFF_WIDTH 1
2394 #define	FRF_AB_GM_EXDEF_TX_EN_LBN 16
2395 #define	FRF_AB_GM_EXDEF_TX_EN_WIDTH 1
2396 #define	FRF_AB_GM_RTRY_LIMIT_LBN 12
2397 #define	FRF_AB_GM_RTRY_LIMIT_WIDTH 4
2398 #define	FRF_AB_GM_COL_WIN_LBN 0
2399 #define	FRF_AB_GM_COL_WIN_WIDTH 10
2400 
2401 
2402 /*
2403  * FR_AB_GM_MAX_FLEN_REG(32bit):
2404  * GMAC maximum frame length register
2405  */
2406 #define	FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40
2407 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2408 
2409 #define	FRF_AB_GM_MAX_FLEN_LBN 0
2410 #define	FRF_AB_GM_MAX_FLEN_WIDTH 16
2411 
2412 
2413 /*
2414  * FR_AB_GM_TEST_REG(32bit):
2415  * GMAC test register
2416  */
2417 #define	FR_AB_GM_TEST_REG_OFST 0x00000e70
2418 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2419 
2420 #define	FRF_AB_GM_MAX_BOFF_LBN 3
2421 #define	FRF_AB_GM_MAX_BOFF_WIDTH 1
2422 #define	FRF_AB_GM_REG_TX_FLOW_EN_LBN 2
2423 #define	FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1
2424 #define	FRF_AB_GM_TEST_PAUSE_LBN 1
2425 #define	FRF_AB_GM_TEST_PAUSE_WIDTH 1
2426 #define	FRF_AB_GM_SHORT_SLOT_LBN 0
2427 #define	FRF_AB_GM_SHORT_SLOT_WIDTH 1
2428 
2429 
2430 /*
2431  * FR_AB_GM_ADR1_REG(32bit):
2432  * GMAC station address register 1
2433  */
2434 #define	FR_AB_GM_ADR1_REG_OFST 0x00000f00
2435 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2436 
2437 #define	FRF_AB_GM_ADR_B0_LBN 24
2438 #define	FRF_AB_GM_ADR_B0_WIDTH 8
2439 #define	FRF_AB_GM_ADR_B1_LBN 16
2440 #define	FRF_AB_GM_ADR_B1_WIDTH 8
2441 #define	FRF_AB_GM_ADR_B2_LBN 8
2442 #define	FRF_AB_GM_ADR_B2_WIDTH 8
2443 #define	FRF_AB_GM_ADR_B3_LBN 0
2444 #define	FRF_AB_GM_ADR_B3_WIDTH 8
2445 
2446 
2447 /*
2448  * FR_AB_GM_ADR2_REG(32bit):
2449  * GMAC station address register 2
2450  */
2451 #define	FR_AB_GM_ADR2_REG_OFST 0x00000f10
2452 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2453 
2454 #define	FRF_AB_GM_ADR_B4_LBN 24
2455 #define	FRF_AB_GM_ADR_B4_WIDTH 8
2456 #define	FRF_AB_GM_ADR_B5_LBN 16
2457 #define	FRF_AB_GM_ADR_B5_WIDTH 8
2458 
2459 
2460 /*
2461  * FR_AB_GMF_CFG0_REG(32bit):
2462  * GMAC FIFO configuration register 0
2463  */
2464 #define	FR_AB_GMF_CFG0_REG_OFST 0x00000f20
2465 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2466 
2467 #define	FRF_AB_GMF_FTFENRPLY_LBN 20
2468 #define	FRF_AB_GMF_FTFENRPLY_WIDTH 1
2469 #define	FRF_AB_GMF_STFENRPLY_LBN 19
2470 #define	FRF_AB_GMF_STFENRPLY_WIDTH 1
2471 #define	FRF_AB_GMF_FRFENRPLY_LBN 18
2472 #define	FRF_AB_GMF_FRFENRPLY_WIDTH 1
2473 #define	FRF_AB_GMF_SRFENRPLY_LBN 17
2474 #define	FRF_AB_GMF_SRFENRPLY_WIDTH 1
2475 #define	FRF_AB_GMF_WTMENRPLY_LBN 16
2476 #define	FRF_AB_GMF_WTMENRPLY_WIDTH 1
2477 #define	FRF_AB_GMF_FTFENREQ_LBN 12
2478 #define	FRF_AB_GMF_FTFENREQ_WIDTH 1
2479 #define	FRF_AB_GMF_STFENREQ_LBN 11
2480 #define	FRF_AB_GMF_STFENREQ_WIDTH 1
2481 #define	FRF_AB_GMF_FRFENREQ_LBN 10
2482 #define	FRF_AB_GMF_FRFENREQ_WIDTH 1
2483 #define	FRF_AB_GMF_SRFENREQ_LBN 9
2484 #define	FRF_AB_GMF_SRFENREQ_WIDTH 1
2485 #define	FRF_AB_GMF_WTMENREQ_LBN 8
2486 #define	FRF_AB_GMF_WTMENREQ_WIDTH 1
2487 #define	FRF_AB_GMF_HSTRSTFT_LBN 4
2488 #define	FRF_AB_GMF_HSTRSTFT_WIDTH 1
2489 #define	FRF_AB_GMF_HSTRSTST_LBN 3
2490 #define	FRF_AB_GMF_HSTRSTST_WIDTH 1
2491 #define	FRF_AB_GMF_HSTRSTFR_LBN 2
2492 #define	FRF_AB_GMF_HSTRSTFR_WIDTH 1
2493 #define	FRF_AB_GMF_HSTRSTSR_LBN 1
2494 #define	FRF_AB_GMF_HSTRSTSR_WIDTH 1
2495 #define	FRF_AB_GMF_HSTRSTWT_LBN 0
2496 #define	FRF_AB_GMF_HSTRSTWT_WIDTH 1
2497 
2498 
2499 /*
2500  * FR_AB_GMF_CFG1_REG(32bit):
2501  * GMAC FIFO configuration register 1
2502  */
2503 #define	FR_AB_GMF_CFG1_REG_OFST 0x00000f30
2504 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2505 
2506 #define	FRF_AB_GMF_CFGFRTH_LBN 16
2507 #define	FRF_AB_GMF_CFGFRTH_WIDTH 5
2508 #define	FRF_AB_GMF_CFGXOFFRTX_LBN 0
2509 #define	FRF_AB_GMF_CFGXOFFRTX_WIDTH 16
2510 
2511 
2512 /*
2513  * FR_AB_GMF_CFG2_REG(32bit):
2514  * GMAC FIFO configuration register 2
2515  */
2516 #define	FR_AB_GMF_CFG2_REG_OFST 0x00000f40
2517 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2518 
2519 #define	FRF_AB_GMF_CFGHWM_LBN 16
2520 #define	FRF_AB_GMF_CFGHWM_WIDTH 6
2521 #define	FRF_AB_GMF_CFGLWM_LBN 0
2522 #define	FRF_AB_GMF_CFGLWM_WIDTH 6
2523 
2524 
2525 /*
2526  * FR_AB_GMF_CFG3_REG(32bit):
2527  * GMAC FIFO configuration register 3
2528  */
2529 #define	FR_AB_GMF_CFG3_REG_OFST 0x00000f50
2530 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2531 
2532 #define	FRF_AB_GMF_CFGHWMFT_LBN 16
2533 #define	FRF_AB_GMF_CFGHWMFT_WIDTH 6
2534 #define	FRF_AB_GMF_CFGFTTH_LBN 0
2535 #define	FRF_AB_GMF_CFGFTTH_WIDTH 6
2536 
2537 
2538 /*
2539  * FR_AB_GMF_CFG4_REG(32bit):
2540  * GMAC FIFO configuration register 4
2541  */
2542 #define	FR_AB_GMF_CFG4_REG_OFST 0x00000f60
2543 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2544 
2545 #define	FRF_AB_GMF_HSTFLTRFRM_LBN 0
2546 #define	FRF_AB_GMF_HSTFLTRFRM_WIDTH 18
2547 
2548 
2549 /*
2550  * FR_AB_GMF_CFG5_REG(32bit):
2551  * GMAC FIFO configuration register 5
2552  */
2553 #define	FR_AB_GMF_CFG5_REG_OFST 0x00000f70
2554 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2555 
2556 #define	FRF_AB_GMF_CFGHDPLX_LBN 22
2557 #define	FRF_AB_GMF_CFGHDPLX_WIDTH 1
2558 #define	FRF_AB_GMF_SRFULL_LBN 21
2559 #define	FRF_AB_GMF_SRFULL_WIDTH 1
2560 #define	FRF_AB_GMF_HSTSRFULLCLR_LBN 20
2561 #define	FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1
2562 #define	FRF_AB_GMF_CFGBYTMODE_LBN 19
2563 #define	FRF_AB_GMF_CFGBYTMODE_WIDTH 1
2564 #define	FRF_AB_GMF_HSTDRPLT64_LBN 18
2565 #define	FRF_AB_GMF_HSTDRPLT64_WIDTH 1
2566 #define	FRF_AB_GMF_HSTFLTRFRMDC_LBN 0
2567 #define	FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18
2568 
2569 
2570 /*
2571  * FR_BB_TX_SRC_MAC_TBL(128bit):
2572  * Transmit IP source address filter table
2573  */
2574 #define	FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000
2575 /* falconb0=net_func_bar2 */
2576 #define	FR_BB_TX_SRC_MAC_TBL_STEP 16
2577 #define	FR_BB_TX_SRC_MAC_TBL_ROWS 16
2578 
2579 #define	FRF_BB_TX_SRC_MAC_ADR_1_LBN 64
2580 #define	FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48
2581 #define	FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64
2582 #define	FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32
2583 #define	FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96
2584 #define	FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16
2585 #define	FRF_BB_TX_SRC_MAC_ADR_0_LBN 0
2586 #define	FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48
2587 #define	FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0
2588 #define	FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32
2589 #define	FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32
2590 #define	FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16
2591 
2592 
2593 /*
2594  * FR_BB_TX_SRC_MAC_CTL_REG(128bit):
2595  * Transmit MAC source address filter control
2596  */
2597 #define	FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100
2598 /* falconb0=net_func_bar2 */
2599 
2600 #define	FRF_BB_TX_SRC_DROP_CTR_LBN 16
2601 #define	FRF_BB_TX_SRC_DROP_CTR_WIDTH 16
2602 #define	FRF_BB_TX_SRC_FLTR_EN_LBN 15
2603 #define	FRF_BB_TX_SRC_FLTR_EN_WIDTH 1
2604 #define	FRF_BB_TX_DROP_CTR_CLR_LBN 12
2605 #define	FRF_BB_TX_DROP_CTR_CLR_WIDTH 1
2606 #define	FRF_BB_TX_MAC_QID_SEL_LBN 0
2607 #define	FRF_BB_TX_MAC_QID_SEL_WIDTH 3
2608 
2609 
2610 /*
2611  * FR_AB_XM_ADR_LO_REG(128bit):
2612  * XGMAC address register low
2613  */
2614 #define	FR_AB_XM_ADR_LO_REG_OFST 0x00001200
2615 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2616 
2617 #define	FRF_AB_XM_ADR_LO_LBN 0
2618 #define	FRF_AB_XM_ADR_LO_WIDTH 32
2619 
2620 
2621 /*
2622  * FR_AB_XM_ADR_HI_REG(128bit):
2623  * XGMAC address register high
2624  */
2625 #define	FR_AB_XM_ADR_HI_REG_OFST 0x00001210
2626 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2627 
2628 #define	FRF_AB_XM_ADR_HI_LBN 0
2629 #define	FRF_AB_XM_ADR_HI_WIDTH 16
2630 
2631 
2632 /*
2633  * FR_AB_XM_GLB_CFG_REG(128bit):
2634  * XGMAC global configuration
2635  */
2636 #define	FR_AB_XM_GLB_CFG_REG_OFST 0x00001220
2637 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2638 
2639 #define	FRF_AB_XM_RMTFLT_GEN_LBN 17
2640 #define	FRF_AB_XM_RMTFLT_GEN_WIDTH 1
2641 #define	FRF_AB_XM_DEBUG_MODE_LBN 16
2642 #define	FRF_AB_XM_DEBUG_MODE_WIDTH 1
2643 #define	FRF_AB_XM_RX_STAT_EN_LBN 11
2644 #define	FRF_AB_XM_RX_STAT_EN_WIDTH 1
2645 #define	FRF_AB_XM_TX_STAT_EN_LBN 10
2646 #define	FRF_AB_XM_TX_STAT_EN_WIDTH 1
2647 #define	FRF_AB_XM_RX_JUMBO_MODE_LBN 6
2648 #define	FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1
2649 #define	FRF_AB_XM_WAN_MODE_LBN 5
2650 #define	FRF_AB_XM_WAN_MODE_WIDTH 1
2651 #define	FRF_AB_XM_INTCLR_MODE_LBN 3
2652 #define	FRF_AB_XM_INTCLR_MODE_WIDTH 1
2653 #define	FRF_AB_XM_CORE_RST_LBN 0
2654 #define	FRF_AB_XM_CORE_RST_WIDTH 1
2655 
2656 
2657 /*
2658  * FR_AB_XM_TX_CFG_REG(128bit):
2659  * XGMAC transmit configuration
2660  */
2661 #define	FR_AB_XM_TX_CFG_REG_OFST 0x00001230
2662 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2663 
2664 #define	FRF_AB_XM_TX_PROG_LBN 24
2665 #define	FRF_AB_XM_TX_PROG_WIDTH 1
2666 #define	FRF_AB_XM_IPG_LBN 16
2667 #define	FRF_AB_XM_IPG_WIDTH 4
2668 #define	FRF_AB_XM_FCNTL_LBN 10
2669 #define	FRF_AB_XM_FCNTL_WIDTH 1
2670 #define	FRF_AB_XM_TXCRC_LBN 8
2671 #define	FRF_AB_XM_TXCRC_WIDTH 1
2672 #define	FRF_AB_XM_EDRC_LBN 6
2673 #define	FRF_AB_XM_EDRC_WIDTH 1
2674 #define	FRF_AB_XM_AUTO_PAD_LBN 5
2675 #define	FRF_AB_XM_AUTO_PAD_WIDTH 1
2676 #define	FRF_AB_XM_TX_PRMBL_LBN 2
2677 #define	FRF_AB_XM_TX_PRMBL_WIDTH 1
2678 #define	FRF_AB_XM_TXEN_LBN 1
2679 #define	FRF_AB_XM_TXEN_WIDTH 1
2680 #define	FRF_AB_XM_TX_RST_LBN 0
2681 #define	FRF_AB_XM_TX_RST_WIDTH 1
2682 
2683 
2684 /*
2685  * FR_AB_XM_RX_CFG_REG(128bit):
2686  * XGMAC receive configuration
2687  */
2688 #define	FR_AB_XM_RX_CFG_REG_OFST 0x00001240
2689 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2690 
2691 #define	FRF_AB_XM_PASS_LENERR_LBN 26
2692 #define	FRF_AB_XM_PASS_LENERR_WIDTH 1
2693 #define	FRF_AB_XM_PASS_CRC_ERR_LBN 25
2694 #define	FRF_AB_XM_PASS_CRC_ERR_WIDTH 1
2695 #define	FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24
2696 #define	FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1
2697 #define	FRF_AB_XM_REJ_BCAST_LBN 20
2698 #define	FRF_AB_XM_REJ_BCAST_WIDTH 1
2699 #define	FRF_AB_XM_ACPT_ALL_MCAST_LBN 11
2700 #define	FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1
2701 #define	FRF_AB_XM_ACPT_ALL_UCAST_LBN 9
2702 #define	FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1
2703 #define	FRF_AB_XM_AUTO_DEPAD_LBN 8
2704 #define	FRF_AB_XM_AUTO_DEPAD_WIDTH 1
2705 #define	FRF_AB_XM_RXCRC_LBN 3
2706 #define	FRF_AB_XM_RXCRC_WIDTH 1
2707 #define	FRF_AB_XM_RX_PRMBL_LBN 2
2708 #define	FRF_AB_XM_RX_PRMBL_WIDTH 1
2709 #define	FRF_AB_XM_RXEN_LBN 1
2710 #define	FRF_AB_XM_RXEN_WIDTH 1
2711 #define	FRF_AB_XM_RX_RST_LBN 0
2712 #define	FRF_AB_XM_RX_RST_WIDTH 1
2713 
2714 
2715 /*
2716  * FR_AB_XM_MGT_INT_MASK(128bit):
2717  * documentation to be written for sum_XM_MGT_INT_MASK
2718  */
2719 #define	FR_AB_XM_MGT_INT_MASK_OFST 0x00001250
2720 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2721 
2722 #define	FRF_AB_XM_MSK_STA_INTR_LBN 16
2723 #define	FRF_AB_XM_MSK_STA_INTR_WIDTH 1
2724 #define	FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9
2725 #define	FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1
2726 #define	FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8
2727 #define	FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1
2728 #define	FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2
2729 #define	FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1
2730 #define	FRF_AB_XM_MSK_RMTFLT_LBN 1
2731 #define	FRF_AB_XM_MSK_RMTFLT_WIDTH 1
2732 #define	FRF_AB_XM_MSK_LCLFLT_LBN 0
2733 #define	FRF_AB_XM_MSK_LCLFLT_WIDTH 1
2734 
2735 
2736 /*
2737  * FR_AB_XM_FC_REG(128bit):
2738  * XGMAC flow control register
2739  */
2740 #define	FR_AB_XM_FC_REG_OFST 0x00001270
2741 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2742 
2743 #define	FRF_AB_XM_PAUSE_TIME_LBN 16
2744 #define	FRF_AB_XM_PAUSE_TIME_WIDTH 16
2745 #define	FRF_AB_XM_RX_MAC_STAT_LBN 11
2746 #define	FRF_AB_XM_RX_MAC_STAT_WIDTH 1
2747 #define	FRF_AB_XM_TX_MAC_STAT_LBN 10
2748 #define	FRF_AB_XM_TX_MAC_STAT_WIDTH 1
2749 #define	FRF_AB_XM_MCNTL_PASS_LBN 8
2750 #define	FRF_AB_XM_MCNTL_PASS_WIDTH 2
2751 #define	FRF_AB_XM_REJ_CNTL_UCAST_LBN 6
2752 #define	FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1
2753 #define	FRF_AB_XM_REJ_CNTL_MCAST_LBN 5
2754 #define	FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1
2755 #define	FRF_AB_XM_ZPAUSE_LBN 2
2756 #define	FRF_AB_XM_ZPAUSE_WIDTH 1
2757 #define	FRF_AB_XM_XMIT_PAUSE_LBN 1
2758 #define	FRF_AB_XM_XMIT_PAUSE_WIDTH 1
2759 #define	FRF_AB_XM_DIS_FCNTL_LBN 0
2760 #define	FRF_AB_XM_DIS_FCNTL_WIDTH 1
2761 
2762 
2763 /*
2764  * FR_AB_XM_PAUSE_TIME_REG(128bit):
2765  * XGMAC pause time register
2766  */
2767 #define	FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290
2768 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2769 
2770 #define	FRF_AB_XM_TX_PAUSE_CNT_LBN 16
2771 #define	FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16
2772 #define	FRF_AB_XM_RX_PAUSE_CNT_LBN 0
2773 #define	FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16
2774 
2775 
2776 /*
2777  * FR_AB_XM_TX_PARAM_REG(128bit):
2778  * XGMAC transmit parameter register
2779  */
2780 #define	FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0
2781 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2782 
2783 #define	FRF_AB_XM_TX_JUMBO_MODE_LBN 31
2784 #define	FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1
2785 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19
2786 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11
2787 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16
2788 #define	FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3
2789 #define	FRF_AB_XM_PAD_CHAR_LBN 0
2790 #define	FRF_AB_XM_PAD_CHAR_WIDTH 8
2791 
2792 
2793 /*
2794  * FR_AB_XM_RX_PARAM_REG(128bit):
2795  * XGMAC receive parameter register
2796  */
2797 #define	FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0
2798 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2799 
2800 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3
2801 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11
2802 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0
2803 #define	FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3
2804 
2805 
2806 /*
2807  * FR_AB_XM_MGT_INT_MSK_REG(128bit):
2808  * XGMAC management interrupt mask register
2809  */
2810 #define	FR_AB_XM_MGT_INT_REG_OFST 0x000012f0
2811 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2812 
2813 #define	FRF_AB_XM_STAT_CNTR_OF_LBN 9
2814 #define	FRF_AB_XM_STAT_CNTR_OF_WIDTH 1
2815 #define	FRF_AB_XM_STAT_CNTR_HF_LBN 8
2816 #define	FRF_AB_XM_STAT_CNTR_HF_WIDTH 1
2817 #define	FRF_AB_XM_PRMBLE_ERR_LBN 2
2818 #define	FRF_AB_XM_PRMBLE_ERR_WIDTH 1
2819 #define	FRF_AB_XM_RMTFLT_LBN 1
2820 #define	FRF_AB_XM_RMTFLT_WIDTH 1
2821 #define	FRF_AB_XM_LCLFLT_LBN 0
2822 #define	FRF_AB_XM_LCLFLT_WIDTH 1
2823 
2824 
2825 /*
2826  * FR_AB_XX_PWR_RST_REG(128bit):
2827  * XGXS/XAUI powerdown/reset register
2828  */
2829 #define	FR_AB_XX_PWR_RST_REG_OFST 0x00001300
2830 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2831 
2832 #define	FRF_AB_XX_PWRDND_SIG_LBN 31
2833 #define	FRF_AB_XX_PWRDND_SIG_WIDTH 1
2834 #define	FRF_AB_XX_PWRDNC_SIG_LBN 30
2835 #define	FRF_AB_XX_PWRDNC_SIG_WIDTH 1
2836 #define	FRF_AB_XX_PWRDNB_SIG_LBN 29
2837 #define	FRF_AB_XX_PWRDNB_SIG_WIDTH 1
2838 #define	FRF_AB_XX_PWRDNA_SIG_LBN 28
2839 #define	FRF_AB_XX_PWRDNA_SIG_WIDTH 1
2840 #define	FRF_AB_XX_SIM_MODE_LBN 27
2841 #define	FRF_AB_XX_SIM_MODE_WIDTH 1
2842 #define	FRF_AB_XX_RSTPLLCD_SIG_LBN 25
2843 #define	FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1
2844 #define	FRF_AB_XX_RSTPLLAB_SIG_LBN 24
2845 #define	FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1
2846 #define	FRF_AB_XX_RESETD_SIG_LBN 23
2847 #define	FRF_AB_XX_RESETD_SIG_WIDTH 1
2848 #define	FRF_AB_XX_RESETC_SIG_LBN 22
2849 #define	FRF_AB_XX_RESETC_SIG_WIDTH 1
2850 #define	FRF_AB_XX_RESETB_SIG_LBN 21
2851 #define	FRF_AB_XX_RESETB_SIG_WIDTH 1
2852 #define	FRF_AB_XX_RESETA_SIG_LBN 20
2853 #define	FRF_AB_XX_RESETA_SIG_WIDTH 1
2854 #define	FRF_AB_XX_RSTXGXSRX_SIG_LBN 18
2855 #define	FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1
2856 #define	FRF_AB_XX_RSTXGXSTX_SIG_LBN 17
2857 #define	FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1
2858 #define	FRF_AB_XX_SD_RST_ACT_LBN 16
2859 #define	FRF_AB_XX_SD_RST_ACT_WIDTH 1
2860 #define	FRF_AB_XX_PWRDND_EN_LBN 15
2861 #define	FRF_AB_XX_PWRDND_EN_WIDTH 1
2862 #define	FRF_AB_XX_PWRDNC_EN_LBN 14
2863 #define	FRF_AB_XX_PWRDNC_EN_WIDTH 1
2864 #define	FRF_AB_XX_PWRDNB_EN_LBN 13
2865 #define	FRF_AB_XX_PWRDNB_EN_WIDTH 1
2866 #define	FRF_AB_XX_PWRDNA_EN_LBN 12
2867 #define	FRF_AB_XX_PWRDNA_EN_WIDTH 1
2868 #define	FRF_AB_XX_RSTPLLCD_EN_LBN 9
2869 #define	FRF_AB_XX_RSTPLLCD_EN_WIDTH 1
2870 #define	FRF_AB_XX_RSTPLLAB_EN_LBN 8
2871 #define	FRF_AB_XX_RSTPLLAB_EN_WIDTH 1
2872 #define	FRF_AB_XX_RESETD_EN_LBN 7
2873 #define	FRF_AB_XX_RESETD_EN_WIDTH 1
2874 #define	FRF_AB_XX_RESETC_EN_LBN 6
2875 #define	FRF_AB_XX_RESETC_EN_WIDTH 1
2876 #define	FRF_AB_XX_RESETB_EN_LBN 5
2877 #define	FRF_AB_XX_RESETB_EN_WIDTH 1
2878 #define	FRF_AB_XX_RESETA_EN_LBN 4
2879 #define	FRF_AB_XX_RESETA_EN_WIDTH 1
2880 #define	FRF_AB_XX_RSTXGXSRX_EN_LBN 2
2881 #define	FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1
2882 #define	FRF_AB_XX_RSTXGXSTX_EN_LBN 1
2883 #define	FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1
2884 #define	FRF_AB_XX_RST_XX_EN_LBN 0
2885 #define	FRF_AB_XX_RST_XX_EN_WIDTH 1
2886 
2887 
2888 /*
2889  * FR_AB_XX_SD_CTL_REG(128bit):
2890  * XGXS/XAUI powerdown/reset control register
2891  */
2892 #define	FR_AB_XX_SD_CTL_REG_OFST 0x00001310
2893 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2894 
2895 #define	FRF_AB_XX_TERMADJ1_LBN 17
2896 #define	FRF_AB_XX_TERMADJ1_WIDTH 1
2897 #define	FRF_AB_XX_TERMADJ0_LBN 16
2898 #define	FRF_AB_XX_TERMADJ0_WIDTH 1
2899 #define	FRF_AB_XX_HIDRVD_LBN 15
2900 #define	FRF_AB_XX_HIDRVD_WIDTH 1
2901 #define	FRF_AB_XX_LODRVD_LBN 14
2902 #define	FRF_AB_XX_LODRVD_WIDTH 1
2903 #define	FRF_AB_XX_HIDRVC_LBN 13
2904 #define	FRF_AB_XX_HIDRVC_WIDTH 1
2905 #define	FRF_AB_XX_LODRVC_LBN 12
2906 #define	FRF_AB_XX_LODRVC_WIDTH 1
2907 #define	FRF_AB_XX_HIDRVB_LBN 11
2908 #define	FRF_AB_XX_HIDRVB_WIDTH 1
2909 #define	FRF_AB_XX_LODRVB_LBN 10
2910 #define	FRF_AB_XX_LODRVB_WIDTH 1
2911 #define	FRF_AB_XX_HIDRVA_LBN 9
2912 #define	FRF_AB_XX_HIDRVA_WIDTH 1
2913 #define	FRF_AB_XX_LODRVA_LBN 8
2914 #define	FRF_AB_XX_LODRVA_WIDTH 1
2915 #define	FRF_AB_XX_LPBKD_LBN 3
2916 #define	FRF_AB_XX_LPBKD_WIDTH 1
2917 #define	FRF_AB_XX_LPBKC_LBN 2
2918 #define	FRF_AB_XX_LPBKC_WIDTH 1
2919 #define	FRF_AB_XX_LPBKB_LBN 1
2920 #define	FRF_AB_XX_LPBKB_WIDTH 1
2921 #define	FRF_AB_XX_LPBKA_LBN 0
2922 #define	FRF_AB_XX_LPBKA_WIDTH 1
2923 
2924 
2925 /*
2926  * FR_AB_XX_TXDRV_CTL_REG(128bit):
2927  * XAUI SerDes transmit drive control register
2928  */
2929 #define	FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320
2930 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2931 
2932 #define	FRF_AB_XX_DEQD_LBN 28
2933 #define	FRF_AB_XX_DEQD_WIDTH 4
2934 #define	FRF_AB_XX_DEQC_LBN 24
2935 #define	FRF_AB_XX_DEQC_WIDTH 4
2936 #define	FRF_AB_XX_DEQB_LBN 20
2937 #define	FRF_AB_XX_DEQB_WIDTH 4
2938 #define	FRF_AB_XX_DEQA_LBN 16
2939 #define	FRF_AB_XX_DEQA_WIDTH 4
2940 #define	FRF_AB_XX_DTXD_LBN 12
2941 #define	FRF_AB_XX_DTXD_WIDTH 4
2942 #define	FRF_AB_XX_DTXC_LBN 8
2943 #define	FRF_AB_XX_DTXC_WIDTH 4
2944 #define	FRF_AB_XX_DTXB_LBN 4
2945 #define	FRF_AB_XX_DTXB_WIDTH 4
2946 #define	FRF_AB_XX_DTXA_LBN 0
2947 #define	FRF_AB_XX_DTXA_WIDTH 4
2948 
2949 
2950 /*
2951  * FR_AB_XX_PRBS_CTL_REG(128bit):
2952  * documentation to be written for sum_XX_PRBS_CTL_REG
2953  */
2954 #define	FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330
2955 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2956 
2957 #define	FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30
2958 #define	FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2
2959 #define	FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29
2960 #define	FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1
2961 #define	FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28
2962 #define	FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1
2963 #define	FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26
2964 #define	FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2
2965 #define	FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25
2966 #define	FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1
2967 #define	FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24
2968 #define	FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1
2969 #define	FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22
2970 #define	FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2
2971 #define	FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21
2972 #define	FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1
2973 #define	FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20
2974 #define	FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1
2975 #define	FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18
2976 #define	FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2
2977 #define	FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17
2978 #define	FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1
2979 #define	FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16
2980 #define	FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1
2981 #define	FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14
2982 #define	FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2
2983 #define	FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13
2984 #define	FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1
2985 #define	FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12
2986 #define	FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1
2987 #define	FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10
2988 #define	FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2
2989 #define	FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9
2990 #define	FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1
2991 #define	FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8
2992 #define	FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1
2993 #define	FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6
2994 #define	FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2
2995 #define	FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5
2996 #define	FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1
2997 #define	FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4
2998 #define	FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1
2999 #define	FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2
3000 #define	FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2
3001 #define	FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1
3002 #define	FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1
3003 #define	FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0
3004 #define	FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1
3005 
3006 
3007 /*
3008  * FR_AB_XX_PRBS_CHK_REG(128bit):
3009  * documentation to be written for sum_XX_PRBS_CHK_REG
3010  */
3011 #define	FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340
3012 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3013 
3014 #define	FRF_AB_XX_REV_LB_EN_LBN 16
3015 #define	FRF_AB_XX_REV_LB_EN_WIDTH 1
3016 #define	FRF_AB_XX_CH3_DEG_DET_LBN 15
3017 #define	FRF_AB_XX_CH3_DEG_DET_WIDTH 1
3018 #define	FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14
3019 #define	FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1
3020 #define	FRF_AB_XX_CH3_PRBS_FRUN_LBN 13
3021 #define	FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1
3022 #define	FRF_AB_XX_CH3_ERR_CHK_LBN 12
3023 #define	FRF_AB_XX_CH3_ERR_CHK_WIDTH 1
3024 #define	FRF_AB_XX_CH2_DEG_DET_LBN 11
3025 #define	FRF_AB_XX_CH2_DEG_DET_WIDTH 1
3026 #define	FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10
3027 #define	FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1
3028 #define	FRF_AB_XX_CH2_PRBS_FRUN_LBN 9
3029 #define	FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1
3030 #define	FRF_AB_XX_CH2_ERR_CHK_LBN 8
3031 #define	FRF_AB_XX_CH2_ERR_CHK_WIDTH 1
3032 #define	FRF_AB_XX_CH1_DEG_DET_LBN 7
3033 #define	FRF_AB_XX_CH1_DEG_DET_WIDTH 1
3034 #define	FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6
3035 #define	FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1
3036 #define	FRF_AB_XX_CH1_PRBS_FRUN_LBN 5
3037 #define	FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1
3038 #define	FRF_AB_XX_CH1_ERR_CHK_LBN 4
3039 #define	FRF_AB_XX_CH1_ERR_CHK_WIDTH 1
3040 #define	FRF_AB_XX_CH0_DEG_DET_LBN 3
3041 #define	FRF_AB_XX_CH0_DEG_DET_WIDTH 1
3042 #define	FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2
3043 #define	FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1
3044 #define	FRF_AB_XX_CH0_PRBS_FRUN_LBN 1
3045 #define	FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1
3046 #define	FRF_AB_XX_CH0_ERR_CHK_LBN 0
3047 #define	FRF_AB_XX_CH0_ERR_CHK_WIDTH 1
3048 
3049 
3050 /*
3051  * FR_AB_XX_PRBS_ERR_REG(128bit):
3052  * documentation to be written for sum_XX_PRBS_ERR_REG
3053  */
3054 #define	FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350
3055 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3056 
3057 #define	FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24
3058 #define	FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8
3059 #define	FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16
3060 #define	FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8
3061 #define	FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8
3062 #define	FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8
3063 #define	FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0
3064 #define	FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8
3065 
3066 
3067 /*
3068  * FR_AB_XX_CORE_STAT_REG(128bit):
3069  * XAUI XGXS core status register
3070  */
3071 #define	FR_AB_XX_CORE_STAT_REG_OFST 0x00001360
3072 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3073 
3074 #define	FRF_AB_XX_FORCE_SIG3_LBN 31
3075 #define	FRF_AB_XX_FORCE_SIG3_WIDTH 1
3076 #define	FRF_AB_XX_FORCE_SIG3_VAL_LBN 30
3077 #define	FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1
3078 #define	FRF_AB_XX_FORCE_SIG2_LBN 29
3079 #define	FRF_AB_XX_FORCE_SIG2_WIDTH 1
3080 #define	FRF_AB_XX_FORCE_SIG2_VAL_LBN 28
3081 #define	FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1
3082 #define	FRF_AB_XX_FORCE_SIG1_LBN 27
3083 #define	FRF_AB_XX_FORCE_SIG1_WIDTH 1
3084 #define	FRF_AB_XX_FORCE_SIG1_VAL_LBN 26
3085 #define	FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1
3086 #define	FRF_AB_XX_FORCE_SIG0_LBN 25
3087 #define	FRF_AB_XX_FORCE_SIG0_WIDTH 1
3088 #define	FRF_AB_XX_FORCE_SIG0_VAL_LBN 24
3089 #define	FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1
3090 #define	FRF_AB_XX_XGXS_LB_EN_LBN 23
3091 #define	FRF_AB_XX_XGXS_LB_EN_WIDTH 1
3092 #define	FRF_AB_XX_XGMII_LB_EN_LBN 22
3093 #define	FRF_AB_XX_XGMII_LB_EN_WIDTH 1
3094 #define	FRF_AB_XX_MATCH_FAULT_LBN 21
3095 #define	FRF_AB_XX_MATCH_FAULT_WIDTH 1
3096 #define	FRF_AB_XX_ALIGN_DONE_LBN 20
3097 #define	FRF_AB_XX_ALIGN_DONE_WIDTH 1
3098 #define	FRF_AB_XX_SYNC_STAT3_LBN 19
3099 #define	FRF_AB_XX_SYNC_STAT3_WIDTH 1
3100 #define	FRF_AB_XX_SYNC_STAT2_LBN 18
3101 #define	FRF_AB_XX_SYNC_STAT2_WIDTH 1
3102 #define	FRF_AB_XX_SYNC_STAT1_LBN 17
3103 #define	FRF_AB_XX_SYNC_STAT1_WIDTH 1
3104 #define	FRF_AB_XX_SYNC_STAT0_LBN 16
3105 #define	FRF_AB_XX_SYNC_STAT0_WIDTH 1
3106 #define	FRF_AB_XX_COMMA_DET_CH3_LBN 15
3107 #define	FRF_AB_XX_COMMA_DET_CH3_WIDTH 1
3108 #define	FRF_AB_XX_COMMA_DET_CH2_LBN 14
3109 #define	FRF_AB_XX_COMMA_DET_CH2_WIDTH 1
3110 #define	FRF_AB_XX_COMMA_DET_CH1_LBN 13
3111 #define	FRF_AB_XX_COMMA_DET_CH1_WIDTH 1
3112 #define	FRF_AB_XX_COMMA_DET_CH0_LBN 12
3113 #define	FRF_AB_XX_COMMA_DET_CH0_WIDTH 1
3114 #define	FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11
3115 #define	FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1
3116 #define	FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10
3117 #define	FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1
3118 #define	FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9
3119 #define	FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1
3120 #define	FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8
3121 #define	FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1
3122 #define	FRF_AB_XX_CHAR_ERR_CH3_LBN 7
3123 #define	FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1
3124 #define	FRF_AB_XX_CHAR_ERR_CH2_LBN 6
3125 #define	FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1
3126 #define	FRF_AB_XX_CHAR_ERR_CH1_LBN 5
3127 #define	FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1
3128 #define	FRF_AB_XX_CHAR_ERR_CH0_LBN 4
3129 #define	FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1
3130 #define	FRF_AB_XX_DISPERR_CH3_LBN 3
3131 #define	FRF_AB_XX_DISPERR_CH3_WIDTH 1
3132 #define	FRF_AB_XX_DISPERR_CH2_LBN 2
3133 #define	FRF_AB_XX_DISPERR_CH2_WIDTH 1
3134 #define	FRF_AB_XX_DISPERR_CH1_LBN 1
3135 #define	FRF_AB_XX_DISPERR_CH1_WIDTH 1
3136 #define	FRF_AB_XX_DISPERR_CH0_LBN 0
3137 #define	FRF_AB_XX_DISPERR_CH0_WIDTH 1
3138 
3139 
3140 /*
3141  * FR_AA_RX_DESC_PTR_TBL_KER(128bit):
3142  * Receive descriptor pointer table
3143  */
3144 #define	FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800
3145 /* falcona0=net_func_bar2 */
3146 #define	FR_AA_RX_DESC_PTR_TBL_KER_STEP 16
3147 #define	FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4
3148 /*
3149  * FR_AZ_RX_DESC_PTR_TBL(128bit):
3150  * Receive descriptor pointer table
3151  */
3152 #define	FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000
3153 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3154 #define	FR_AZ_RX_DESC_PTR_TBL_STEP 16
3155 #define	FR_CZ_RX_DESC_PTR_TBL_ROWS 1024
3156 #define	FR_AB_RX_DESC_PTR_TBL_ROWS 4096
3157 
3158 #define	FRF_CZ_RX_HDR_SPLIT_LBN 90
3159 #define	FRF_CZ_RX_HDR_SPLIT_WIDTH 1
3160 #define	FRF_AZ_RX_RESET_LBN 89
3161 #define	FRF_AZ_RX_RESET_WIDTH 1
3162 #define	FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88
3163 #define	FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1
3164 #define	FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87
3165 #define	FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1
3166 #define	FRF_AZ_RX_DESC_PREF_ACT_LBN 86
3167 #define	FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1
3168 #define	FRF_AZ_RX_DC_HW_RPTR_LBN 80
3169 #define	FRF_AZ_RX_DC_HW_RPTR_WIDTH 6
3170 #define	FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68
3171 #define	FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12
3172 #define	FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56
3173 #define	FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12
3174 #define	FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36
3175 #define	FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20
3176 #define	FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24
3177 #define	FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12
3178 #define	FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10
3179 #define	FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14
3180 #define	FRF_AZ_RX_DESCQ_LABEL_LBN 5
3181 #define	FRF_AZ_RX_DESCQ_LABEL_WIDTH 5
3182 #define	FRF_AZ_RX_DESCQ_SIZE_LBN 3
3183 #define	FRF_AZ_RX_DESCQ_SIZE_WIDTH 2
3184 #define	FFE_AZ_RX_DESCQ_SIZE_4K 3
3185 #define	FFE_AZ_RX_DESCQ_SIZE_2K 2
3186 #define	FFE_AZ_RX_DESCQ_SIZE_1K 1
3187 #define	FFE_AZ_RX_DESCQ_SIZE_512 0
3188 #define	FRF_AZ_RX_DESCQ_TYPE_LBN 2
3189 #define	FRF_AZ_RX_DESCQ_TYPE_WIDTH 1
3190 #define	FRF_AZ_RX_DESCQ_JUMBO_LBN 1
3191 #define	FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1
3192 #define	FRF_AZ_RX_DESCQ_EN_LBN 0
3193 #define	FRF_AZ_RX_DESCQ_EN_WIDTH 1
3194 
3195 
3196 /*
3197  * FR_AA_TX_DESC_PTR_TBL_KER(128bit):
3198  * Transmit descriptor pointer
3199  */
3200 #define	FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900
3201 /* falcona0=net_func_bar2 */
3202 #define	FR_AA_TX_DESC_PTR_TBL_KER_STEP 16
3203 #define	FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8
3204 /*
3205  * FR_AZ_TX_DESC_PTR_TBL(128bit):
3206  * Transmit descriptor pointer
3207  */
3208 #define	FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000
3209 /* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
3210 #define	FR_AZ_TX_DESC_PTR_TBL_STEP 16
3211 #define	FR_AB_TX_DESC_PTR_TBL_ROWS 4096
3212 #define	FR_CZ_TX_DESC_PTR_TBL_ROWS 1024
3213 
3214 #define	FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94
3215 #define	FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2
3216 #define	FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93
3217 #define	FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1
3218 #define	FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92
3219 #define	FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1
3220 #define	FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91
3221 #define	FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1
3222 #define	FRF_BZ_TX_IP_CHKSM_DIS_LBN 90
3223 #define	FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1
3224 #define	FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89
3225 #define	FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1
3226 #define	FRF_AZ_TX_DESCQ_EN_LBN 88
3227 #define	FRF_AZ_TX_DESCQ_EN_WIDTH 1
3228 #define	FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87
3229 #define	FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1
3230 #define	FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86
3231 #define	FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1
3232 #define	FRF_AZ_TX_DC_HW_RPTR_LBN 80
3233 #define	FRF_AZ_TX_DC_HW_RPTR_WIDTH 6
3234 #define	FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68
3235 #define	FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12
3236 #define	FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56
3237 #define	FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12
3238 #define	FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36
3239 #define	FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20
3240 #define	FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24
3241 #define	FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12
3242 #define	FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10
3243 #define	FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14
3244 #define	FRF_AZ_TX_DESCQ_LABEL_LBN 5
3245 #define	FRF_AZ_TX_DESCQ_LABEL_WIDTH 5
3246 #define	FRF_AZ_TX_DESCQ_SIZE_LBN 3
3247 #define	FRF_AZ_TX_DESCQ_SIZE_WIDTH 2
3248 #define	FFE_AZ_TX_DESCQ_SIZE_4K 3
3249 #define	FFE_AZ_TX_DESCQ_SIZE_2K 2
3250 #define	FFE_AZ_TX_DESCQ_SIZE_1K 1
3251 #define	FFE_AZ_TX_DESCQ_SIZE_512 0
3252 #define	FRF_AZ_TX_DESCQ_TYPE_LBN 1
3253 #define	FRF_AZ_TX_DESCQ_TYPE_WIDTH 2
3254 #define	FRF_AZ_TX_DESCQ_FLUSH_LBN 0
3255 #define	FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1
3256 
3257 
3258 /*
3259  * FR_AA_EVQ_PTR_TBL_KER(128bit):
3260  * Event queue pointer table
3261  */
3262 #define	FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00
3263 /* falcona0=net_func_bar2 */
3264 #define	FR_AA_EVQ_PTR_TBL_KER_STEP 16
3265 #define	FR_AA_EVQ_PTR_TBL_KER_ROWS 4
3266 /*
3267  * FR_AZ_EVQ_PTR_TBL(128bit):
3268  * Event queue pointer table
3269  */
3270 #define	FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000
3271 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3272 #define	FR_AZ_EVQ_PTR_TBL_STEP 16
3273 #define	FR_CZ_EVQ_PTR_TBL_ROWS 1024
3274 #define	FR_AB_EVQ_PTR_TBL_ROWS 4096
3275 
3276 #define	FRF_BZ_EVQ_RPTR_IGN_LBN 40
3277 #define	FRF_BZ_EVQ_RPTR_IGN_WIDTH 1
3278 #define	FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39
3279 #define	FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1
3280 #define	FRF_AZ_EVQ_NXT_WPTR_LBN 24
3281 #define	FRF_AZ_EVQ_NXT_WPTR_WIDTH 15
3282 #define	FRF_AZ_EVQ_EN_LBN 23
3283 #define	FRF_AZ_EVQ_EN_WIDTH 1
3284 #define	FRF_AZ_EVQ_SIZE_LBN 20
3285 #define	FRF_AZ_EVQ_SIZE_WIDTH 3
3286 #define	FFE_AZ_EVQ_SIZE_32K 6
3287 #define	FFE_AZ_EVQ_SIZE_16K 5
3288 #define	FFE_AZ_EVQ_SIZE_8K 4
3289 #define	FFE_AZ_EVQ_SIZE_4K 3
3290 #define	FFE_AZ_EVQ_SIZE_2K 2
3291 #define	FFE_AZ_EVQ_SIZE_1K 1
3292 #define	FFE_AZ_EVQ_SIZE_512 0
3293 #define	FRF_AZ_EVQ_BUF_BASE_ID_LBN 0
3294 #define	FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20
3295 
3296 
3297 /*
3298  * FR_AA_BUF_HALF_TBL_KER(64bit):
3299  * Buffer table in half buffer table mode direct access by driver
3300  */
3301 #define	FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000
3302 /* falcona0=net_func_bar2 */
3303 #define	FR_AA_BUF_HALF_TBL_KER_STEP 8
3304 #define	FR_AA_BUF_HALF_TBL_KER_ROWS 4096
3305 /*
3306  * FR_AZ_BUF_HALF_TBL(64bit):
3307  * Buffer table in half buffer table mode direct access by driver
3308  */
3309 #define	FR_AZ_BUF_HALF_TBL_OFST 0x00800000
3310 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3311 #define	FR_AZ_BUF_HALF_TBL_STEP 8
3312 #define	FR_CZ_BUF_HALF_TBL_ROWS 147456
3313 #define	FR_AB_BUF_HALF_TBL_ROWS 524288
3314 
3315 #define	FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44
3316 #define	FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20
3317 #define	FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32
3318 #define	FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12
3319 #define	FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12
3320 #define	FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20
3321 #define	FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0
3322 #define	FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
3323 
3324 
3325 /*
3326  * FR_AA_BUF_FULL_TBL_KER(64bit):
3327  * Buffer table in full buffer table mode direct access by driver
3328  */
3329 #define	FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000
3330 /* falcona0=net_func_bar2 */
3331 #define	FR_AA_BUF_FULL_TBL_KER_STEP 8
3332 #define	FR_AA_BUF_FULL_TBL_KER_ROWS 4096
3333 /*
3334  * FR_AZ_BUF_FULL_TBL(64bit):
3335  * Buffer table in full buffer table mode direct access by driver
3336  */
3337 #define	FR_AZ_BUF_FULL_TBL_OFST 0x00800000
3338 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3339 #define	FR_AZ_BUF_FULL_TBL_STEP 8
3340 
3341 #define	FR_CZ_BUF_FULL_TBL_ROWS 147456
3342 #define	FR_AB_BUF_FULL_TBL_ROWS 917504
3343 
3344 #define	FRF_AZ_BUF_FULL_UNUSED_LBN 51
3345 #define	FRF_AZ_BUF_FULL_UNUSED_WIDTH 13
3346 #define	FRF_AZ_IP_DAT_BUF_SIZE_LBN 50
3347 #define	FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1
3348 #define	FRF_AZ_BUF_ADR_REGION_LBN 48
3349 #define	FRF_AZ_BUF_ADR_REGION_WIDTH 2
3350 #define	FFE_AZ_BUF_ADR_REGN3 3
3351 #define	FFE_AZ_BUF_ADR_REGN2 2
3352 #define	FFE_AZ_BUF_ADR_REGN1 1
3353 #define	FFE_AZ_BUF_ADR_REGN0 0
3354 #define	FRF_AZ_BUF_ADR_FBUF_LBN 14
3355 #define	FRF_AZ_BUF_ADR_FBUF_WIDTH 34
3356 #define	FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14
3357 #define	FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32
3358 #define	FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46
3359 #define	FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2
3360 #define	FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0
3361 #define	FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14
3362 
3363 
3364 /*
3365  * FR_AZ_RX_FILTER_TBL0(128bit):
3366  * TCP/IPv4 Receive filter table
3367  */
3368 #define	FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000
3369 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
3370 #define	FR_AZ_RX_FILTER_TBL0_STEP 32
3371 #define	FR_AZ_RX_FILTER_TBL0_ROWS 8192
3372 /*
3373  * FR_AB_RX_FILTER_TBL1(128bit):
3374  * TCP/IPv4 Receive filter table
3375  */
3376 #define	FR_AB_RX_FILTER_TBL1_OFST 0x00f00010
3377 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
3378 #define	FR_AB_RX_FILTER_TBL1_STEP 32
3379 #define	FR_AB_RX_FILTER_TBL1_ROWS 8192
3380 
3381 #define	FRF_BZ_RSS_EN_LBN 110
3382 #define	FRF_BZ_RSS_EN_WIDTH 1
3383 #define	FRF_BZ_SCATTER_EN_LBN 109
3384 #define	FRF_BZ_SCATTER_EN_WIDTH 1
3385 #define	FRF_AZ_TCP_UDP_LBN 108
3386 #define	FRF_AZ_TCP_UDP_WIDTH 1
3387 #define	FRF_AZ_RXQ_ID_LBN 96
3388 #define	FRF_AZ_RXQ_ID_WIDTH 12
3389 #define	FRF_AZ_DEST_IP_LBN 64
3390 #define	FRF_AZ_DEST_IP_WIDTH 32
3391 #define	FRF_AZ_DEST_PORT_TCP_LBN 48
3392 #define	FRF_AZ_DEST_PORT_TCP_WIDTH 16
3393 #define	FRF_AZ_SRC_IP_LBN 16
3394 #define	FRF_AZ_SRC_IP_WIDTH 32
3395 #define	FRF_AZ_SRC_TCP_DEST_UDP_LBN 0
3396 #define	FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16
3397 
3398 
3399 /*
3400  * FR_CZ_RX_MAC_FILTER_TBL0(128bit):
3401  * Receive Ethernet filter table
3402  */
3403 #define	FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010
3404 /* sienaa0=net_func_bar2 */
3405 #define	FR_CZ_RX_MAC_FILTER_TBL0_STEP 32
3406 #define	FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512
3407 
3408 #define	FRF_CZ_RMFT_RSS_EN_LBN 75
3409 #define	FRF_CZ_RMFT_RSS_EN_WIDTH 1
3410 #define	FRF_CZ_RMFT_SCATTER_EN_LBN 74
3411 #define	FRF_CZ_RMFT_SCATTER_EN_WIDTH 1
3412 #define	FRF_CZ_RMFT_IP_OVERRIDE_LBN 73
3413 #define	FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1
3414 #define	FRF_CZ_RMFT_RXQ_ID_LBN 61
3415 #define	FRF_CZ_RMFT_RXQ_ID_WIDTH 12
3416 #define	FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60
3417 #define	FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1
3418 #define	FRF_CZ_RMFT_DEST_MAC_LBN 12
3419 #define	FRF_CZ_RMFT_DEST_MAC_WIDTH 48
3420 #define	FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12
3421 #define	FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32
3422 #define	FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44
3423 #define	FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16
3424 #define	FRF_CZ_RMFT_VLAN_ID_LBN 0
3425 #define	FRF_CZ_RMFT_VLAN_ID_WIDTH 12
3426 
3427 
3428 /*
3429  * FR_AZ_TIMER_TBL(128bit):
3430  * Timer table
3431  */
3432 #define	FR_AZ_TIMER_TBL_OFST 0x00f70000
3433 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3434 #define	FR_AZ_TIMER_TBL_STEP 16
3435 #define	FR_CZ_TIMER_TBL_ROWS 1024
3436 #define	FR_AB_TIMER_TBL_ROWS 4096
3437 
3438 #define	FRF_CZ_TIMER_Q_EN_LBN 33
3439 #define	FRF_CZ_TIMER_Q_EN_WIDTH 1
3440 #define	FRF_CZ_INT_ARMD_LBN 32
3441 #define	FRF_CZ_INT_ARMD_WIDTH 1
3442 #define	FRF_CZ_INT_PEND_LBN 31
3443 #define	FRF_CZ_INT_PEND_WIDTH 1
3444 #define	FRF_CZ_HOST_NOTIFY_MODE_LBN 30
3445 #define	FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1
3446 #define	FRF_CZ_RELOAD_TIMER_VAL_LBN 16
3447 #define	FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14
3448 #define	FRF_CZ_TIMER_MODE_LBN 14
3449 #define	FRF_CZ_TIMER_MODE_WIDTH 2
3450 #define	FFE_CZ_TIMER_MODE_INT_HLDOFF 3
3451 #define	FFE_CZ_TIMER_MODE_TRIG_START 2
3452 #define	FFE_CZ_TIMER_MODE_IMMED_START 1
3453 #define	FFE_CZ_TIMER_MODE_DIS 0
3454 #define	FRF_AB_TIMER_MODE_LBN 12
3455 #define	FRF_AB_TIMER_MODE_WIDTH 2
3456 #define	FFE_AB_TIMER_MODE_INT_HLDOFF 2
3457 #define	FFE_AB_TIMER_MODE_TRIG_START 2
3458 #define	FFE_AB_TIMER_MODE_IMMED_START 1
3459 #define	FFE_AB_TIMER_MODE_DIS 0
3460 #define	FRF_CZ_TIMER_VAL_LBN 0
3461 #define	FRF_CZ_TIMER_VAL_WIDTH 14
3462 #define	FRF_AB_TIMER_VAL_LBN 0
3463 #define	FRF_AB_TIMER_VAL_WIDTH 12
3464 
3465 
3466 /*
3467  * FR_BZ_TX_PACE_TBL(128bit):
3468  * Transmit pacing table
3469  */
3470 #define	FR_BZ_TX_PACE_TBL_OFST 0x00f80000
3471 /* sienaa0=net_func_bar2,falconb0=net_func_bar2 */
3472 #define	FR_AZ_TX_PACE_TBL_STEP 16
3473 #define	FR_CZ_TX_PACE_TBL_ROWS 1024
3474 #define	FR_BB_TX_PACE_TBL_ROWS 4096
3475 /*
3476  * FR_AA_TX_PACE_TBL(128bit):
3477  * Transmit pacing table
3478  */
3479 #define	FR_AA_TX_PACE_TBL_OFST 0x00f80040
3480 /* falcona0=char_func_bar0 */
3481 /* FR_AZ_TX_PACE_TBL_STEP 16 */
3482 #define	FR_AA_TX_PACE_TBL_ROWS 4092
3483 
3484 #define	FRF_AZ_TX_PACE_LBN 0
3485 #define	FRF_AZ_TX_PACE_WIDTH 5
3486 
3487 
3488 /*
3489  * FR_BZ_RX_INDIRECTION_TBL(7bit):
3490  * RX Indirection Table
3491  */
3492 #define	FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000
3493 /* falconb0,sienaa0=net_func_bar2 */
3494 #define	FR_BZ_RX_INDIRECTION_TBL_STEP 16
3495 #define	FR_BZ_RX_INDIRECTION_TBL_ROWS 128
3496 
3497 #define	FRF_BZ_IT_QUEUE_LBN 0
3498 #define	FRF_BZ_IT_QUEUE_WIDTH 6
3499 
3500 
3501 /*
3502  * FR_CZ_TX_FILTER_TBL0(128bit):
3503  * TCP/IPv4 Transmit filter table
3504  */
3505 #define	FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000
3506 /* sienaa0=net_func_bar2 */
3507 #define	FR_CZ_TX_FILTER_TBL0_STEP 16
3508 #define	FR_CZ_TX_FILTER_TBL0_ROWS 8192
3509 
3510 #define	FRF_CZ_TIFT_TCP_UDP_LBN 108
3511 #define	FRF_CZ_TIFT_TCP_UDP_WIDTH 1
3512 #define	FRF_CZ_TIFT_TXQ_ID_LBN 96
3513 #define	FRF_CZ_TIFT_TXQ_ID_WIDTH 12
3514 #define	FRF_CZ_TIFT_DEST_IP_LBN 64
3515 #define	FRF_CZ_TIFT_DEST_IP_WIDTH 32
3516 #define	FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48
3517 #define	FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16
3518 #define	FRF_CZ_TIFT_SRC_IP_LBN 16
3519 #define	FRF_CZ_TIFT_SRC_IP_WIDTH 32
3520 #define	FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0
3521 #define	FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16
3522 
3523 
3524 /*
3525  * FR_CZ_TX_MAC_FILTER_TBL0(128bit):
3526  * Transmit Ethernet filter table
3527  */
3528 #define	FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000
3529 /* sienaa0=net_func_bar2 */
3530 #define	FR_CZ_TX_MAC_FILTER_TBL0_STEP 16
3531 #define	FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512
3532 
3533 #define	FRF_CZ_TMFT_TXQ_ID_LBN 61
3534 #define	FRF_CZ_TMFT_TXQ_ID_WIDTH 12
3535 #define	FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60
3536 #define	FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1
3537 #define	FRF_CZ_TMFT_SRC_MAC_LBN 12
3538 #define	FRF_CZ_TMFT_SRC_MAC_WIDTH 48
3539 #define	FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12
3540 #define	FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32
3541 #define	FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44
3542 #define	FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16
3543 #define	FRF_CZ_TMFT_VLAN_ID_LBN 0
3544 #define	FRF_CZ_TMFT_VLAN_ID_WIDTH 12
3545 
3546 
3547 /*
3548  * FR_CZ_MC_TREG_SMEM(32bit):
3549  * MC Shared Memory
3550  */
3551 #define	FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000
3552 /* sienaa0=net_func_bar2 */
3553 #define	FR_CZ_MC_TREG_SMEM_STEP 4
3554 #define	FR_CZ_MC_TREG_SMEM_ROWS 512
3555 
3556 #define	FRF_CZ_MC_TREG_SMEM_ROW_LBN 0
3557 #define	FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32
3558 
3559 
3560 /*
3561  * FR_BB_MSIX_VECTOR_TABLE(128bit):
3562  * MSIX Vector Table
3563  */
3564 #define	FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000
3565 /* falconb0=net_func_bar2 */
3566 #define	FR_BZ_MSIX_VECTOR_TABLE_STEP 16
3567 #define	FR_BB_MSIX_VECTOR_TABLE_ROWS 64
3568 /*
3569  * FR_CZ_MSIX_VECTOR_TABLE(128bit):
3570  * MSIX Vector Table
3571  */
3572 #define	FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000
3573 /* sienaa0=pci_f0_bar4 */
3574 /* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */
3575 #define	FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024
3576 
3577 #define	FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97
3578 #define	FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31
3579 #define	FRF_BZ_MSIX_VECTOR_MASK_LBN 96
3580 #define	FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1
3581 #define	FRF_BZ_MSIX_MESSAGE_DATA_LBN 64
3582 #define	FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32
3583 #define	FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32
3584 #define	FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32
3585 #define	FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0
3586 #define	FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32
3587 
3588 
3589 /*
3590  * FR_BB_MSIX_PBA_TABLE(32bit):
3591  * MSIX Pending Bit Array
3592  */
3593 #define	FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000
3594 /* falconb0=net_func_bar2 */
3595 #define	FR_BZ_MSIX_PBA_TABLE_STEP 4
3596 #define	FR_BB_MSIX_PBA_TABLE_ROWS 2
3597 /*
3598  * FR_CZ_MSIX_PBA_TABLE(32bit):
3599  * MSIX Pending Bit Array
3600  */
3601 #define	FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000
3602 /* sienaa0=pci_f0_bar4 */
3603 /* FR_BZ_MSIX_PBA_TABLE_STEP 4 */
3604 #define	FR_CZ_MSIX_PBA_TABLE_ROWS 32
3605 
3606 #define	FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0
3607 #define	FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32
3608 
3609 
3610 /*
3611  * FR_AZ_SRM_DBG_REG(64bit):
3612  * SRAM debug access
3613  */
3614 #define	FR_AZ_SRM_DBG_REG_OFST 0x03000000
3615 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3616 #define	FR_AZ_SRM_DBG_REG_STEP 8
3617 
3618 #define	FR_CZ_SRM_DBG_REG_ROWS 262144
3619 #define	FR_AB_SRM_DBG_REG_ROWS 2097152
3620 
3621 #define	FRF_AZ_SRM_DBG_LBN 0
3622 #define	FRF_AZ_SRM_DBG_WIDTH 64
3623 #define	FRF_AZ_SRM_DBG_DW0_LBN 0
3624 #define	FRF_AZ_SRM_DBG_DW0_WIDTH 32
3625 #define	FRF_AZ_SRM_DBG_DW1_LBN 32
3626 #define	FRF_AZ_SRM_DBG_DW1_WIDTH 32
3627 
3628 
3629 /*
3630  * FR_AA_INT_ACK_CHAR(32bit):
3631  * CHAR interrupt acknowledge register
3632  */
3633 #define	FR_AA_INT_ACK_CHAR_OFST 0x00000060
3634 /* falcona0=char_func_bar0 */
3635 
3636 #define	FRF_AA_INT_ACK_CHAR_FIELD_LBN 0
3637 #define	FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32
3638 
3639 
3640 /* FS_DRIVER_EV */
3641 #define	FSF_AZ_DRIVER_EV_SUBCODE_LBN 56
3642 #define	FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4
3643 #define	FSE_AZ_TX_DSC_ERROR_EV 15
3644 #define	FSE_AZ_RX_DSC_ERROR_EV 14
3645 #define	FSE_AZ_RX_RECOVER_EV 11
3646 #define	FSE_AZ_TIMER_EV 10
3647 #define	FSE_AZ_TX_PKT_NON_TCP_UDP 9
3648 #define	FSE_AZ_WAKE_UP_EV 6
3649 #define	FSE_AZ_SRM_UPD_DONE_EV 5
3650 #define	FSE_AZ_EVQ_NOT_EN_EV 3
3651 #define	FSE_AZ_EVQ_INIT_DONE_EV 2
3652 #define	FSE_AZ_RX_DESCQ_FLS_DONE_EV 1
3653 #define	FSE_AZ_TX_DESCQ_FLS_DONE_EV 0
3654 #define	FSF_AZ_DRIVER_EV_SUBDATA_LBN 0
3655 #define	FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14
3656 
3657 
3658 /* FS_EVENT_ENTRY */
3659 #define	FSF_AZ_EV_CODE_LBN 60
3660 #define	FSF_AZ_EV_CODE_WIDTH 4
3661 #define	FSE_AZ_EV_CODE_USER_EV 8
3662 #define	FSE_AZ_EV_CODE_DRV_GEN_EV 7
3663 #define	FSE_AZ_EV_CODE_GLOBAL_EV 6
3664 #define	FSE_AZ_EV_CODE_DRIVER_EV 5
3665 #define	FSE_AZ_EV_CODE_TX_EV 2
3666 #define	FSE_AZ_EV_CODE_RX_EV 0
3667 #define	FSF_AZ_EV_DATA_LBN 0
3668 #define	FSF_AZ_EV_DATA_WIDTH 60
3669 #define	FSF_AZ_EV_DATA_DW0_LBN 0
3670 #define	FSF_AZ_EV_DATA_DW0_WIDTH 32
3671 #define	FSF_AZ_EV_DATA_DW1_LBN 32
3672 #define	FSF_AZ_EV_DATA_DW1_WIDTH 28
3673 
3674 
3675 /* FS_GLOBAL_EV */
3676 #define	FSF_AA_GLB_EV_RX_RECOVERY_LBN 12
3677 #define	FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1
3678 #define	FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11
3679 #define	FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1
3680 #define	FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10
3681 #define	FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1
3682 #define	FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9
3683 #define	FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1
3684 #define	FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7
3685 #define	FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1
3686 
3687 
3688 /* FS_RX_EV */
3689 #define	FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58
3690 #define	FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1
3691 #define	FSF_CZ_RX_EV_IPV6_PKT_LBN 57
3692 #define	FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1
3693 #define	FSF_AZ_RX_EV_PKT_OK_LBN 56
3694 #define	FSF_AZ_RX_EV_PKT_OK_WIDTH 1
3695 #define	FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55
3696 #define	FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1
3697 #define	FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54
3698 #define	FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
3699 #define	FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53
3700 #define	FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1
3701 #define	FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
3702 #define	FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
3703 #define	FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
3704 #define	FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
3705 #define	FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50
3706 #define	FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1
3707 #define	FSF_AZ_RX_EV_FRM_TRUNC_LBN 49
3708 #define	FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1
3709 #define	FSF_AZ_RX_EV_TOBE_DISC_LBN 47
3710 #define	FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1
3711 #define	FSF_AZ_RX_EV_PKT_TYPE_LBN 44
3712 #define	FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3
3713 #define	FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5
3714 #define	FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4
3715 #define	FSE_AZ_RX_EV_PKT_TYPE_VLAN 3
3716 #define	FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2
3717 #define	FSE_AZ_RX_EV_PKT_TYPE_LLC 1
3718 #define	FSE_AZ_RX_EV_PKT_TYPE_ETH 0
3719 #define	FSF_AZ_RX_EV_HDR_TYPE_LBN 42
3720 #define	FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2
3721 #define	FSE_AZ_RX_EV_HDR_TYPE_OTHER 3
3722 #define	FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2
3723 #define	FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2
3724 #define	FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1
3725 #define	FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1
3726 #define	FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0
3727 #define	FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0
3728 #define	FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41
3729 #define	FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1
3730 #define	FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40
3731 #define	FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1
3732 #define	FSF_AZ_RX_EV_MCAST_PKT_LBN 39
3733 #define	FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1
3734 #define	FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37
3735 #define	FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1
3736 #define	FSF_AZ_RX_EV_Q_LABEL_LBN 32
3737 #define	FSF_AZ_RX_EV_Q_LABEL_WIDTH 5
3738 #define	FSF_AZ_RX_EV_JUMBO_CONT_LBN 31
3739 #define	FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1
3740 #define	FSF_AZ_RX_EV_PORT_LBN 30
3741 #define	FSF_AZ_RX_EV_PORT_WIDTH 1
3742 #define	FSF_AZ_RX_EV_BYTE_CNT_LBN 16
3743 #define	FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14
3744 #define	FSF_AZ_RX_EV_SOP_LBN 15
3745 #define	FSF_AZ_RX_EV_SOP_WIDTH 1
3746 #define	FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14
3747 #define	FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1
3748 #define	FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13
3749 #define	FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1
3750 #define	FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12
3751 #define	FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1
3752 #define	FSF_AZ_RX_EV_DESC_PTR_LBN 0
3753 #define	FSF_AZ_RX_EV_DESC_PTR_WIDTH 12
3754 
3755 
3756 /* FS_RX_KER_DESC */
3757 #define	FSF_AZ_RX_KER_BUF_SIZE_LBN 48
3758 #define	FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14
3759 #define	FSF_AZ_RX_KER_BUF_REGION_LBN 46
3760 #define	FSF_AZ_RX_KER_BUF_REGION_WIDTH 2
3761 #define	FSF_AZ_RX_KER_BUF_ADDR_LBN 0
3762 #define	FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46
3763 #define	FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0
3764 #define	FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32
3765 #define	FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32
3766 #define	FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14
3767 
3768 
3769 /* FS_RX_USER_DESC */
3770 #define	FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20
3771 #define	FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12
3772 #define	FSF_AZ_RX_USER_BUF_ID_LBN 0
3773 #define	FSF_AZ_RX_USER_BUF_ID_WIDTH 20
3774 
3775 
3776 /* FS_TX_EV */
3777 #define	FSF_AZ_TX_EV_PKT_ERR_LBN 38
3778 #define	FSF_AZ_TX_EV_PKT_ERR_WIDTH 1
3779 #define	FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37
3780 #define	FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1
3781 #define	FSF_AZ_TX_EV_Q_LABEL_LBN 32
3782 #define	FSF_AZ_TX_EV_Q_LABEL_WIDTH 5
3783 #define	FSF_AZ_TX_EV_PORT_LBN 16
3784 #define	FSF_AZ_TX_EV_PORT_WIDTH 1
3785 #define	FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15
3786 #define	FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1
3787 #define	FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14
3788 #define	FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1
3789 #define	FSF_AZ_TX_EV_COMP_LBN 12
3790 #define	FSF_AZ_TX_EV_COMP_WIDTH 1
3791 #define	FSF_AZ_TX_EV_DESC_PTR_LBN 0
3792 #define	FSF_AZ_TX_EV_DESC_PTR_WIDTH 12
3793 
3794 
3795 /* FS_TX_KER_DESC */
3796 #define	FSF_AZ_TX_KER_CONT_LBN 62
3797 #define	FSF_AZ_TX_KER_CONT_WIDTH 1
3798 #define	FSF_AZ_TX_KER_BYTE_COUNT_LBN 48
3799 #define	FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14
3800 #define	FSF_AZ_TX_KER_BUF_REGION_LBN 46
3801 #define	FSF_AZ_TX_KER_BUF_REGION_WIDTH 2
3802 #define	FSF_AZ_TX_KER_BUF_ADDR_LBN 0
3803 #define	FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46
3804 #define	FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0
3805 #define	FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32
3806 #define	FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32
3807 #define	FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14
3808 
3809 
3810 /* FS_TX_USER_DESC */
3811 #define	FSF_AZ_TX_USER_SW_EV_EN_LBN 48
3812 #define	FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1
3813 #define	FSF_AZ_TX_USER_CONT_LBN 46
3814 #define	FSF_AZ_TX_USER_CONT_WIDTH 1
3815 #define	FSF_AZ_TX_USER_BYTE_CNT_LBN 33
3816 #define	FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13
3817 #define	FSF_AZ_TX_USER_BUF_ID_LBN 13
3818 #define	FSF_AZ_TX_USER_BUF_ID_WIDTH 20
3819 #define	FSF_AZ_TX_USER_BYTE_OFS_LBN 0
3820 #define	FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13
3821 
3822 
3823 /* FS_USER_EV */
3824 #define	FSF_CZ_USER_QID_LBN 32
3825 #define	FSF_CZ_USER_QID_WIDTH 10
3826 #define	FSF_CZ_USER_EV_REG_VALUE_LBN 0
3827 #define	FSF_CZ_USER_EV_REG_VALUE_WIDTH 32
3828 
3829 
3830 /* FS_NET_IVEC */
3831 #define	FSF_AZ_NET_IVEC_FATAL_INT_LBN 64
3832 #define	FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1
3833 #define	FSF_AZ_NET_IVEC_INT_Q_LBN 40
3834 #define	FSF_AZ_NET_IVEC_INT_Q_WIDTH 4
3835 #define	FSF_AZ_NET_IVEC_INT_FLAG_LBN 32
3836 #define	FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1
3837 #define	FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1
3838 #define	FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1
3839 #define	FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0
3840 #define	FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1
3841 
3842 
3843 /* DRIVER_EV */
3844 /* Sub-fields of an RX flush completion event */
3845 #define	FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12
3846 #define	FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
3847 #define	FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0
3848 #define	FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12
3849 
3850 
3851 
3852 /**************************************************************************
3853  *
3854  * Falcon non-volatile configuration
3855  *
3856  **************************************************************************
3857  */
3858 
3859 
3860 #define	FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST
3861 
3862 
3863 #ifdef	__cplusplus
3864 }
3865 #endif
3866 
3867 
3868 
3869 
3870 #endif /* _SYS_EFX_REGS_H */
3871