1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2024 Oxide Computer Company
14 */
15
16 #ifndef _SYS_AMDZEN_DF_H
17 #define _SYS_AMDZEN_DF_H
18
19 /*
20 * This file contains definitions for the registers that appears in the AMD Zen
21 * Data Fabric. The data fabric is the main component which routes transactions
22 * between entities (e.g. CPUS, DRAM, PCIe, etc.) in the system. The data fabric
23 * itself is made up of up to 8 PCI functions. There can be multiple instances
24 * of the data fabric. There is one instance per die. In most AMD processors
25 * after Zen 1, there is only a single die per socket, for more background see
26 * the uts/i86pc/os/cpuid.c big theory statement. All data fabric instances
27 * appear on PCI bus 0. The first instance shows up on device 0x18. Subsequent
28 * instances simply increment that number by one.
29 *
30 * There are currently four major revisions of the data fabric that are
31 * supported here, which are v2 (Zen 1), v3 (Zen 2/3), v3.5 (Zen 2/3 with DDR5),
32 * and v4 (Zen 4). In many cases, while the same logical thing exists in
33 * different generations, they often have different shapes and sometimes things
34 * with the same shape show up in different locations. As DFv4 has been extended
35 * across several different lines, things haven't been quite as smooth as we'd
36 * like in terms of DF representation. Certain things end up moving around much
37 * more liberally while revving the minor version of the DF, though at least we
38 * can still identify it as such.
39 *
40 * The major (relevant to us) distinction that we have found so far is that
41 * starting in DF 4v2 and greater, the way that DRAM was structured and the
42 * corresponding DRAM channel remap settings were moved. Because the DRAM base
43 * address registers were moved to 0x200, we call this DF_REV_4D2. If this
44 * gets much more nuanced, we should likely figure out if we want to encode
45 * minor versions in these constants and offer function pointers to get common
46 * things rather than forcing it onto clients. Note that this is very much a
47 * rough approximation and not really great. There are many places where the
48 * width of fields has changed slightly between minor revs, but are eating up
49 * more reserved bits, or not using quite as many.
50 *
51 * To make things a little easier for clients, each register definition encodes
52 * enough information to also include which hardware generations it supports,
53 * the actual PCI function it appears upon, and the register offset. This is to
54 * make sure that consumers don't have to guess some of this information in the
55 * latter cases and we can try to guarantee we're not accessing an incorrect
56 * register for our platform (unfortunately at runtime).
57 *
58 * Register definitions have the following form:
59 *
60 * DF_<reg name>_<vers>
61 *
62 * Here <reg name> is something that describes the register. This may not be the
63 * exact same as the PPR (processor programming reference); however, the PPR
64 * name for the register will be included above it in a comment (though these
65 * have sometimes changed from time to time). For example, DF_DRAM_HOLE. If a
66 * given register is the same in all currently supported versions, then there is
67 * no version suffix appended. Otherwise, the first version it is supported in
68 * is appended. For example, DF_DRAM_BASE_V2, DF_DRAM_BASE_V3, DF_DRAM_BASE_V4,
69 * etc. or DF_FIDMASK0_V3P5, etc. If the register offset is the same in multiple
70 * versions, then there they share the earliest version.
71 *
72 * For fields there are currently macros to extract these or chain them together
73 * leveraging bitx32() and bitset32(). Fields have the forms:
74 *
75 * DF_<reg name>_<vers>_GET_<field>
76 * DF_<reg name>_<vers>_SET_<field>
77 *
78 * Like in the above, if there are cases where a single field is the same across
79 * all versions, then the <vers> portion will be elided. There are many cases
80 * where the register definition does not change, but the fields themselves do
81 * change with each version because each hardware rev opts to be slightly
82 * different.
83 *
84 * When adding support for a new chip, please look carefully through the
85 * requisite documentation to ensure that they match what we see here. There are
86 * often cases where there may be a subtle thing or you hit a case like V3P5
87 * that until you dig deeper just seem to be weird.
88 */
89
90 #include <sys/bitext.h>
91
92 #ifdef __cplusplus
93 extern "C" {
94 #endif
95
96 typedef enum df_rev {
97 DF_REV_UNKNOWN = 0,
98 DF_REV_2 = 1 << 0,
99 DF_REV_3 = 1 << 1,
100 DF_REV_3P5 = 1 << 2,
101 DF_REV_4 = 1 << 3,
102 /*
103 * This is a synthetic revision we make up per the theory statement that
104 * covers devices that have an updated DRAM layout.
105 */
106 DF_REV_4D2 = 1 << 4
107 } df_rev_t;
108
109 #define DF_REV_ALL_3 (DF_REV_3 | DF_REV_3P5)
110 #define DF_REV_ALL_23 (DF_REV_2 | DF_REV_ALL_3)
111 #define DF_REV_ALL_4 (DF_REV_4 | DF_REV_4D2)
112 #define DF_REV_ALL (DF_REV_ALL_23 | DF_REV_ALL_4)
113
114 typedef struct df_reg_def {
115 df_rev_t drd_gens;
116 uint8_t drd_func;
117 uint16_t drd_reg;
118 } df_reg_def_t;
119
120 /*
121 * This set of registers provides us access to the count of instances in the
122 * data fabric and then a number of different pieces of information about them
123 * like their type. Note, these registers require indirect access because the
124 * information cannot be broadcast.
125 */
126
127 /*
128 * DF::FabricBlockInstanceCount -- Describes the number of instances in the data
129 * fabric. With v4, also includes versioning information.
130 */
131 /*CSTYLED*/
132 #define DF_FBICNT (df_reg_def_t){ .drd_gens = DF_REV_ALL, \
133 .drd_func = 0, .drd_reg = 0x40 }
134 #define DF_FBICNT_V4_GET_MAJOR(r) bitx32(r, 27, 24)
135 #define DF_FBICNT_V4_GET_MINOR(r) bitx32(r, 23, 16)
136 #define DF_FBICNT_GET_COUNT(r) bitx32(r, 7, 0)
137
138 /*
139 * DF::FabricBlockInstanceInformation0 -- get basic information about a fabric
140 * instance.
141 */
142 /*CSTYLED*/
143 #define DF_FBIINFO0 (df_reg_def_t){ .drd_gens = DF_REV_ALL, \
144 .drd_func = 0, .drd_reg = 0x44 }
145 #define DF_FBIINFO0_GET_SUBTYPE(r) bitx32(r, 26, 24)
146 #define DF_SUBTYPE_NONE 0
147 typedef enum {
148 DF_CAKE_SUBTYPE_GMI = 1,
149 DF_CAKE_SUBTYPE_xGMI = 2
150 } df_cake_subtype_t;
151
152 typedef enum {
153 DF_IOM_SUBTYPE_IOHUB = 1,
154 } df_iom_subtype_t;
155
156 typedef enum {
157 DF_CS_SUBTYPE_UMC = 1,
158 /*
159 * The subtype changed beginning in DFv4. Prior to DFv4, the secondary
160 * type was CCIX. Starting with DFv4, this is now CMP. It is unclear if
161 * these are the same thing or not.
162 */
163 DF_CS_SUBTYPE_CCIX = 2,
164 DF_CS_SUBTYPE_CMP = 2
165 } df_cs_subtype_t;
166
167 /*
168 * Starting in DFv4 they introduced a CCM subtype; however, kept the CPU
169 * compatible with prior DF revisions in v4.0. Starting with v4.1, they moved
170 * this to a value of one and the less asked about the ACM the better.
171 * Unfortunately this doesn't fit nicely with the major DF revisions which we
172 * use for register access.
173 */
174 typedef enum {
175 DF_CCM_SUBTYPE_CPU_V2 = 0,
176 DF_CCM_SUBTYPE_ACM_V4 = 1,
177 DF_CCM_SUBTYPE_CPU_V4P1 = 1
178 } df_ccm_subtype_v4_t;
179
180 typedef enum {
181 DF_NCM_SUBTYPE_MMHUB = 1,
182 DF_NCM_SUBTYPE_DCE = 2,
183 DF_NCM_SUBTYPE_IOMMU = 4
184 } df_ncm_subtype_t;
185
186
187 #define DF_FBIINFO0_GET_HAS_MCA(r) bitx32(r, 23, 23)
188 #define DF_FBIINFO0_GET_FTI_DCNT(r) bitx32(r, 21, 20)
189 #define DF_FBIINFO0_GET_FTI_PCNT(r) bitx32(r, 18, 16)
190 #define DF_FBIINFO0_GET_SDP_RESPCNT(r) bitx32(r, 14, 14)
191 #define DF_FBIINFO0_GET_SDP_PCNT(r) bitx32(r, 13, 12)
192 #define DF_FBIINFO0_GET_FTI_WIDTH(r) bitx32(r, 9, 8)
193 typedef enum {
194 DF_FTI_W_64 = 0,
195 DF_FTI_W_128,
196 DF_FTI_W_256,
197 DF_FTI_W_512
198 } df_fti_width_t;
199 #define DF_FBIINFO0_V3_GET_ENABLED(r) bitx32(r, 6, 6)
200 #define DF_FBIINFO0_GET_SDP_WIDTH(r) bitx32(r, 5, 4)
201 typedef enum {
202 DF_SDP_W_64 = 0,
203 DF_SDP_W_128,
204 DF_SDP_W_256,
205 DF_SDP_W_512
206 } df_sdp_width_t;
207 #define DF_FBIINFO0_GET_TYPE(r) bitx32(r, 3, 0)
208 typedef enum {
209 DF_TYPE_CCM = 0,
210 DF_TYPE_GCM,
211 DF_TYPE_NCM,
212 DF_TYPE_IOMS,
213 DF_TYPE_CS,
214 DF_TYPE_NCS,
215 DF_TYPE_TCDX,
216 DF_TYPE_PIE,
217 DF_TYPE_SPF,
218 DF_TYPE_LLC,
219 DF_TYPE_CAKE,
220 DF_TYPE_ICNG,
221 DF_TYPE_PFX,
222 DF_TYPE_CNLI
223 } df_type_t;
224
225 /*
226 * DF::FabricBlockInstanceInformation1 -- get basic information about a fabric
227 * instance. This appears to have been dropped starting in DF 4D2.
228 */
229 /*CSTYLED*/
230 #define DF_FBIINFO1 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \
231 DF_REV_4, .drd_func = 0, .drd_reg = 0x48 }
232 #define DF_FBINFO1_GET_FTI3_NINSTID(r) bitx32(r, 31, 24)
233 #define DF_FBINFO1_GET_FTI2_NINSTID(r) bitx32(r, 23, 16)
234 #define DF_FBINFO1_GET_FTI1_NINSTID(r) bitx32(r, 15, 8)
235 #define DF_FBINFO1_GET_FTI0_NINSTID(r) bitx32(r, 7, 0)
236
237 /*
238 * DF::FabricBlockInstanceInformation2 -- get basic information about a fabric
239 * instance. This appears to have been dropped starting in DF 4D2.
240 */
241 /*CSTYLED*/
242 #define DF_FBIINFO2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23 | \
243 DF_REV_4, .drd_func = 0, .drd_reg = 0x4c }
244 #define DF_FBINFO2_GET_FTI5_NINSTID(r) bitx32(r, 15, 8)
245 #define DF_FBINFO2_GET_FTI4_NINSTID(r) bitx32(r, 7, 0)
246
247 /*
248 * DF::FabricBlockInstanceInformation3 -- obtain the basic IDs for a given
249 * instance.
250 */
251 /*CSTYLED*/
252 #define DF_FBIINFO3 (df_reg_def_t){ .drd_gens = DF_REV_ALL, \
253 .drd_func = 0, .drd_reg = 0x50 }
254 #define DF_FBIINFO3_V2_GET_BLOCKID(r) bitx32(r, 15, 8)
255 #define DF_FBIINFO3_V3_GET_BLOCKID(r) bitx32(r, 13, 8)
256 #define DF_FBIINFO3_V3P5_GET_BLOCKID(r) bitx32(r, 11, 8)
257 #define DF_FBIINFO3_V4_GET_BLOCKID(r) bitx32(r, 19, 8)
258 #define DF_FBIINFO3_GET_INSTID(r) bitx32(r, 7, 0)
259
260 /*
261 * DF::DfCapability -- Describes the capabilities that the DF has. Note that one
262 * must generally check the DF version prior to considering various bits here.
263 * For example, the extended CS remaper is only valid starting in the 4D2
264 * variant.
265 */
266 /*CSTYLED*/
267 #define DF_CAPAB (df_reg_def_t){ .drd_gens = DF_REV_ALL, \
268 .drd_func = 0, .drd_reg = 0x90 }
269 #define DF_CAPAB_GET_EXTCSREMAP(r) bitx32(r, 2, 2)
270 #define DF_CAPAB_GET_SPF(r) bitx32(r, 1, 1)
271 #define DF_CAPAB_GET_POISON(r) bitx32(r, 0, 0)
272
273 /*
274 * DF::Skt0CsTargetRemap0, DF::Skt0CsTargetRemap1, DF::Skt1CsTargetRemap0,
275 * DF::Skt1CsTargetRemap1 -- The next set of registers provide access to
276 * chip-select remapping. Caution, while these have a documented DF generation
277 * that they are specific to, it seems they still aren't always implemented and
278 * are specific to Milan (v3) and Genoa (v4). The actual remap extraction is the
279 * same between both.
280 */
281 #define DF_CS_REMAP_GET_CSX(r, x) bitx32(r, (3 + (4 * (x))), (4 * ((x))))
282 /*CSTYLED*/
283 #define DF_SKT0_CS_REMAP0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
284 .drd_func = 0, .drd_reg = 0x60 }
285 /*CSTYLED*/
286 #define DF_SKT1_CS_REMAP0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
287 .drd_func = 0, .drd_reg = 0x68 }
288 /*CSTYLED*/
289 #define DF_SKT0_CS_REMAP1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
290 .drd_func = 0, .drd_reg = 0x64 }
291 /*CSTYLED*/
292 #define DF_SKT1_CS_REMAP1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
293 .drd_func = 0, .drd_reg = 0x6c }
294 /*
295 * DF::CsTargetRemap0A, DF::CsTargetRemap0B, etc. -- These registers contain the
296 * remap engines in DFv4. Note, that while v3 used 0/1 as REMAP[01], as
297 * referring to the same logical set of things, here [0-3] is used for different
298 * things and A/B distinguish the different actual CS values. This was redone to
299 * allow for a wider channel selection in the 4D2 parts, see the subsequent
300 * section.
301 */
302 /*CSTYLED*/
303 #define DF_CS_REMAP0A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
304 .drd_func = 7, .drd_reg = 0x180 }
305 /*CSTYLED*/
306 #define DF_CS_REMAP0B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
307 .drd_func = 7, .drd_reg = 0x184 }
308 /*CSTYLED*/
309 #define DF_CS_REMAP1A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
310 .drd_func = 7, .drd_reg = 0x188 }
311 /*CSTYLED*/
312 #define DF_CS_REMAP1B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
313 .drd_func = 7, .drd_reg = 0x18c }
314 /*CSTYLED*/
315 #define DF_CS_REMAP2A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
316 .drd_func = 7, .drd_reg = 0x190 }
317 /*CSTYLED*/
318 #define DF_CS_REMAP2B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
319 .drd_func = 7, .drd_reg = 0x194 }
320 /*CSTYLED*/
321 #define DF_CS_REMAP3A_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
322 .drd_func = 7, .drd_reg = 0x198 }
323 /*CSTYLED*/
324 #define DF_CS_REMAP3B_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
325 .drd_func = 7, .drd_reg = 0x19c }
326
327 /*
328 * DF::CsTargetRemap0A, DF::CsTargetRemap0B, etc. -- D42 edition. This has
329 * changed the actual size of the remap values so that they are now 5 bits wide,
330 * allowing for up to 32 channels. This is indicated by bit 2 (EXTCSREMAP) in
331 * DF::DfCapability. As a result, there are now only 6 remaps per register, so
332 * there are now 3 registers [ABC] per remap target [0123].
333 * changing around where the registers actually are.
334 */
335 #define DF_CS_REMAP_GET_CSX_V4B(r, x) bitx32(r, (4 + (5 * (x))), (5 * ((x))))
336 /*CSTYLED*/
337 #define DF_CS_REMAP0A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
338 .drd_func = 7, .drd_reg = 0x180 }
339 /*CSTYLED*/
340 #define DF_CS_REMAP0B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
341 .drd_func = 7, .drd_reg = 0x184 }
342 /*CSTYLED*/
343 #define DF_CS_REMAP0C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
344 .drd_func = 7, .drd_reg = 0x188 }
345 /*CSTYLED*/
346 #define DF_CS_REMAP1A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
347 .drd_func = 7, .drd_reg = 0x198 }
348 /*CSTYLED*/
349 #define DF_CS_REMAP1B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
350 .drd_func = 7, .drd_reg = 0x19c }
351 /*CSTYLED*/
352 #define DF_CS_REMAP1C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
353 .drd_func = 7, .drd_reg = 0x1a0 }
354 /*CSTYLED*/
355 #define DF_CS_REMAP2A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
356 .drd_func = 7, .drd_reg = 0x1b0 }
357 /*CSTYLED*/
358 #define DF_CS_REMAP2B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
359 .drd_func = 7, .drd_reg = 0x1b4 }
360 /*CSTYLED*/
361 #define DF_CS_REMAP2C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
362 .drd_func = 7, .drd_reg = 0x1b8 }
363 /*CSTYLED*/
364 #define DF_CS_REMAP3A_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
365 .drd_func = 7, .drd_reg = 0x1c8 }
366 /*CSTYLED*/
367 #define DF_CS_REMAP3B_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
368 .drd_func = 7, .drd_reg = 0x1cc }
369 /*CSTYLED*/
370 #define DF_CS_REMAP3C_V4D2 (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
371 .drd_func = 7, .drd_reg = 0x1d0 }
372
373 /*
374 * DF::CfgAddressCntl -- This register contains the information about the
375 * configuration of PCIe buses. We care about finding which one has our BUS A,
376 * which is required to map it to the in-package northbridge instance.
377 */
378 /*CSTYLED*/
379 #define DF_CFG_ADDR_CTL_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
380 .drd_func = 0, \
381 .drd_reg = 0x84 }
382 /*CSTYLED*/
383 #define DF_CFG_ADDR_CTL_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
384 .drd_func = 0, \
385 .drd_reg = 0xc04 }
386 #define DF_CFG_ADDR_CTL_GET_BUS_NUM(r) bitx32(r, 7, 0)
387
388 /*
389 * DF::CfgAddressMap -- This next set of registers covers PCI Bus configuration
390 * address maps. The layout here changes at v4. This routes a given PCI bus to a
391 * device.
392 */
393 /*CSTYLED*/
394 #define DF_CFGMAP_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
395 .drd_func = 0, \
396 .drd_reg = 0xa0 + ((x) * 4) }
397 #define DF_MAX_CFGMAP 8
398 #define DF_MAX_CFGMAP_TURIN 16
399 #define DF_CFGMAP_V2_GET_BUS_LIMIT(r) bitx32(r, 31, 24)
400 #define DF_CFGMAP_V2_GET_BUS_BASE(r) bitx32(r, 23, 16)
401 #define DF_CFGMAP_V2_GET_DEST_ID(r) bitx32(r, 11, 4)
402 #define DF_CFGMAP_V3_GET_DEST_ID(r) bitx32(r, 13, 4)
403 #define DF_CFGMAP_V3P5_GET_DEST_ID(r) bitx32(r, 7, 4)
404 #define DF_CFGMAP_V2_GET_WE(r) bitx32(r, 1, 1)
405 #define DF_CFGMAP_V2_GET_RE(r) bitx32(r, 0, 0)
406
407 /*
408 * DF::CfgBaseAddress, DF::CfgLimitAddress -- DFv4 variants of the above now in
409 * two registers and more possible entries!
410 */
411 /*CSTYLED*/
412 #define DF_CFGMAP_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
413 .drd_func = 0, \
414 .drd_reg = 0xc80 + ((x) * 8) }
415 /*CSTYLED*/
416 #define DF_CFGMAP_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
417 .drd_func = 0, \
418 .drd_reg = 0xc84 + ((x) * 8) }
419 #define DF_CFGMAP_BASE_V4_GET_BASE(r) bitx32(r, 23, 16)
420 #define DF_CFGMAP_BASE_V4_GET_SEG(r) bitx32(r, 15, 8)
421 #define DF_CFGMAP_BASE_V4_GET_WE(r) bitx32(r, 1, 1)
422 #define DF_CFGMAP_BASE_V4_GET_RE(r) bitx32(r, 0, 0)
423 #define DF_CFGMAP_LIMIT_V4_GET_LIMIT(r) bitx32(r, 23, 16)
424 #define DF_CFGMAP_LIMIT_V4_GET_DEST_ID(r) bitx32(r, 11, 0)
425 #define DF_CFGMAP_LIMIT_V4D2_GET_DEST_ID(r) bitx32(r, 7, 0)
426
427 /*
428 * DF::X86IOBaseAddress, DF::X86IOLimitAddress -- Base and limit registers for
429 * routing I/O space. These are fairly similar prior to DFv4. The number of
430 * these was increased in Turin. We expect this'll hold true for future server
431 * parts.
432 */
433 /*CSTYLED*/
434 #define DF_IO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
435 .drd_func = 0, \
436 .drd_reg = 0xc0 + ((x) * 8) }
437 /*CSTYLED*/
438 #define DF_IO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
439 .drd_func = 0, \
440 .drd_reg = 0xd00 + ((x) * 8) }
441 #define DF_MAX_IO_RULES 8
442 #define DF_MAX_IO_RULES_TURIN 16
443 #define DF_IO_BASE_SHIFT 12
444 #define DF_IO_BASE_V2_GET_BASE(r) bitx32(r, 24, 12)
445 #define DF_IO_BASE_V2_GET_IE(r) bitx32(r, 5, 5)
446 #define DF_IO_BASE_V2_GET_WE(r) bitx32(r, 1, 1)
447 #define DF_IO_BASE_V2_GET_RE(r) bitx32(r, 0, 0)
448 #define DF_IO_BASE_V2_SET_BASE(r, v) bitset32(r, 24, 12, v)
449 #define DF_IO_BASE_V2_SET_IE(r, v) bitset32(r, 5, 5, v)
450 #define DF_IO_BASE_V2_SET_WE(r, v) bitset32(r, 1, 1, v)
451 #define DF_IO_BASE_V2_SET_RE(r, v) bitset32(r, 0, 0, v)
452
453 #define DF_IO_BASE_V4_GET_BASE(r) bitx32(r, 28, 16)
454 #define DF_IO_BASE_V4_GET_IE(r) bitx32(r, 5, 5)
455 #define DF_IO_BASE_V4_GET_WE(r) bitx32(r, 1, 1)
456 #define DF_IO_BASE_V4_GET_RE(r) bitx32(r, 0, 0)
457 #define DF_IO_BASE_V4_SET_BASE(r, v) bitset32(r, 28, 16, v)
458 #define DF_IO_BASE_V4_SET_IE(r, v) bitset32(r, 5, 5, v)
459 #define DF_IO_BASE_V4_SET_WE(r, v) bitset32(r, 1, 1, v)
460 #define DF_IO_BASE_V4_SET_RE(r, v) bitset32(r, 0, 0, v)
461
462 /*CSTYLED*/
463 #define DF_IO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
464 .drd_func = 0, \
465 .drd_reg = 0xc4 + ((x) * 8) }
466 /*CSTYLED*/
467 #define DF_IO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
468 .drd_func = 0, \
469 .drd_reg = 0xd04 + ((x) * 8) }
470 #define DF_MAX_IO_LIMIT ((1 << 24) - 1)
471 #define DF_IO_LIMIT_SHIFT 12
472 #define DF_IO_LIMIT_EXCL (1 << DF_IO_LIMIT_SHIFT)
473 #define DF_IO_LIMIT_V2_GET_LIMIT(r) bitx32(r, 24, 12)
474 #define DF_IO_LIMIT_V2_GET_DEST_ID(r) bitx32(r, 7, 0)
475 #define DF_IO_LIMIT_V3_GET_DEST_ID(r) bitx32(r, 9, 0)
476 #define DF_IO_LIMIT_V3P5_GET_DEST_ID(r) bitx32(r, 3, 0)
477 #define DF_IO_LIMIT_V2_SET_LIMIT(r, v) bitset32(r, 24, 12, v)
478 #define DF_IO_LIMIT_V2_SET_DEST_ID(r, v) bitset32(r, 7, 0, v)
479 #define DF_IO_LIMIT_V3_SET_DEST_ID(r, v) bitset32(r, 9, 0, v)
480 #define DF_IO_LIMIT_V3P5_SET_DEST_ID(r, v) bitset32(r, 3, 0, v)
481
482 #define DF_IO_LIMIT_V4_GET_LIMIT(r) bitx32(r, 28, 16)
483 #define DF_IO_LIMIT_V4_GET_DEST_ID(r) bitx32(r, 11, 0)
484 #define DF_IO_LIMIT_V4D2_GET_DEST_ID(r) bitx32(r, 7, 0)
485 #define DF_IO_LIMIT_V4_SET_LIMIT(r, v) bitset32(r, 28, 16, v)
486 #define DF_IO_LIMIT_V4_SET_DEST_ID(r, v) bitset32(r, 11, 0, v)
487 #define DF_IO_LIMIT_V4D2_SET_DEST_ID(r, v) bitset32(r, 7, 0, v)
488
489 /*
490 * DF::DramHoleControl -- This controls MMIO below 4 GiB. Note, both this and
491 * the Top of Memory (TOM) need to be set consistently.
492 */
493 /*CSTYLED*/
494 #define DF_DRAM_HOLE_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
495 .drd_func = 0, \
496 .drd_reg = 0x104 }
497 /*CSTYLED*/
498 #define DF_DRAM_HOLE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
499 .drd_func = 7, \
500 .drd_reg = 0x104 }
501 #define DF_DRAM_HOLE_GET_BASE(r) bitx32(r, 31, 24)
502 #define DF_DRAM_HOLE_BASE_SHIFT 24
503 #define DF_DRAM_HOLE_GET_VALID(r) bitx32(r, 0, 0)
504
505 /*
506 * DF::DramBaseAddress, DF::DramLimitAddress -- DRAM rules, these are split into
507 * a base and limit. While DFv2, 3, and 3.5 all have the same addresses, they
508 * have different bit patterns entirely. DFv4 is in a different location and
509 * further splits this into four registers. We do all of the pre-DFv4 stuff and
510 * follow with DFv4. In DFv2-3.5 the actual values of the bits (e.g. the meaning
511 * of the channel interleave value) are the same, even though where those bits
512 * are in the register changes.
513 *
514 * In DF v2, v3, and v3.5 the set of constants for interleave values are the
515 * same, so we define them once at the v2 version.
516 */
517 /*CSTYLED*/
518 #define DF_DRAM_BASE_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
519 .drd_func = 0, \
520 .drd_reg = 0x110 + ((r) * 8) }
521 #define DF_DRAM_BASE_V2_GET_BASE(r) bitx32(r, 31, 12)
522 #define DF_DRAM_BASE_V2_BASE_SHIFT 28
523 #define DF_DRAM_BASE_V2_GET_ILV_ADDR(r) bitx32(r, 10, 8)
524 #define DF_DRAM_BASE_V2_GET_ILV_CHAN(r) bitx32(r, 7, 4)
525 #define DF_DRAM_BASE_V2_ILV_CHAN_1 0x0
526 #define DF_DRAM_BASE_V2_ILV_CHAN_2 0x1
527 #define DF_DRAM_BASE_V2_ILV_CHAN_4 0x3
528 #define DF_DRAM_BASE_V2_ILV_CHAN_8 0x5
529 #define DF_DRAM_BASE_V2_ILV_CHAN_6 0x6
530 #define DF_DRAM_BASE_V2_ILV_CHAN_COD4_2 0xc
531 #define DF_DRAM_BASE_V2_ILV_CHAN_COD2_4 0xd
532 #define DF_DRAM_BASE_V2_ILV_CHAN_COD1_8 0xe
533 #define DF_DRAM_BASE_V2_GET_HOLE_EN(r) bitx32(r, 1, 1)
534 #define DF_DRAM_BASE_V2_GET_VALID(r) bitx32(r, 0, 0)
535
536 #define DF_DRAM_BASE_V3_GET_ILV_ADDR(r) bitx32(r, 11, 9)
537 #define DF_DRAM_BASE_V3_GET_ILV_SOCK(r) bitx32(r, 8, 8)
538 #define DF_DRAM_BASE_V3_GET_ILV_DIE(r) bitx32(r, 7, 6)
539 #define DF_DRAM_BASE_V3_GET_ILV_CHAN(r) bitx32(r, 5, 2)
540
541 #define DF_DRAM_BASE_V3P5_GET_ILV_ADDR(r) bitx32(r, 11, 9)
542 #define DF_DRAM_BASE_V3P5_GET_ILV_SOCK(r) bitx32(r, 8, 8)
543 #define DF_DRAM_BASE_V3P5_GET_ILV_DIE(r) bitx32(r, 7, 7)
544 #define DF_DRAM_BASE_V3P5_GET_ILV_CHAN(r) bitx32(r, 6, 2)
545
546 /*
547 * Shared definitions for the DF DRAM interleaving address start bits. While the
548 * bitfield / register definition is different between DFv2/3/3.5 and DFv4, the
549 * actual contents of the base address register and the base are shared.
550 */
551 #define DF_DRAM_ILV_ADDR_8 0
552 #define DF_DRAM_ILV_ADDR_9 1
553 #define DF_DRAM_ILV_ADDR_10 2
554 #define DF_DRAM_ILV_ADDR_11 3
555 #define DF_DRAM_ILV_ADDR_12 4
556 #define DF_DRAM_ILV_ADDR_BASE 8
557
558 /*CSTYLED*/
559 #define DF_DRAM_LIMIT_V2(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
560 .drd_func = 0, \
561 .drd_reg = 0x114 + ((r) * 8) }
562 #define DF_DRAM_LIMIT_V2_GET_LIMIT(r) bitx32(r, 31, 12)
563 #define DF_DRAM_LIMIT_V2_LIMIT_SHIFT 28
564 #define DF_DRAM_LIMIT_V2_LIMIT_EXCL (1 << 28)
565 /* These are in the base register for v3, v3.5 */
566 #define DF_DRAM_LIMIT_V2_GET_ILV_DIE(r) bitx32(r, 11, 10)
567 #define DF_DRAM_LIMIT_V2_GET_ILV_SOCK(r) bitx32(r, 8, 8)
568 #define DF_DRAM_LIMIT_V2_GET_DEST_ID(r) bitx32(r, 7, 0)
569
570 #define DF_DRAM_LIMIT_V3_GET_BUS_BREAK(r) bitx32(r, 10, 10)
571 #define DF_DRAM_LIMIT_V3_GET_DEST_ID(r) bitx32(r, 9, 0)
572
573 #define DF_DRAM_LIMIT_V3P5_GET_DEST_ID(r) bitx32(r, 3, 0)
574
575 /*
576 * DF::DramBaseAddress, DF::DramLimitAddress, DF::DramAddressCtl,
577 * DF::DramAddressIntlv -- DFv4 edition. Here all the controls around the
578 * target, interleaving, hashing, and more is split out from the base and limit
579 * registers and put into dedicated control and interleave registers.
580 *
581 * In the 4D2 variant, the base and limit are the same, just at different
582 * addresses. The control register is subtly different with additional
583 * interleave options.
584 */
585 /*CSTYLED*/
586 #define DF_DRAM_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \
587 .drd_func = 7, \
588 .drd_reg = 0xe00 + ((x) * 0x10) }
589 /*CSTYLED*/
590 #define DF_DRAM_BASE_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
591 .drd_func = 7, \
592 .drd_reg = 0x200 + ((x) * 0x10) }
593 #define DF_DRAM_BASE_V4_GET_ADDR(r) bitx32(r, 27, 0)
594 #define DF_DRAM_BASE_V4_BASE_SHIFT 28
595 /*CSTYLED*/
596 #define DF_DRAM_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \
597 .drd_func = 7, \
598 .drd_reg = 0xe04 + ((x) * 0x10) }
599 /*CSTYLED*/
600 #define DF_DRAM_LIMIT_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
601 .drd_func = 7, \
602 .drd_reg = 0x204 + ((x) * 0x10) }
603 #define DF_DRAM_LIMIT_V4_GET_ADDR(r) bitx32(r, 27, 0)
604 #define DF_DRAM_LIMIT_V4_LIMIT_SHIFT 28
605 #define DF_DRAM_LIMIT_V4_LIMIT_EXCL (1 << 28)
606
607 /*CSTYLED*/
608 #define DF_DRAM_CTL_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \
609 .drd_func = 7, \
610 .drd_reg = 0xe08 + ((x) * 0x10) }
611 /*CSTYLED*/
612 #define DF_DRAM_CTL_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
613 .drd_func = 7, \
614 .drd_reg = 0x208 + ((x) * 0x10) }
615 #define DF_DRAM_CTL_V4_GET_DEST_ID(r) bitx32(r, 27, 16)
616 #define DF_DRAM_CTL_V4D2_GET_DEST_ID(r) bitx32(r, 23, 16)
617 #define DF_DRAM_CTL_V4D2_GET_HASH_1T(r) bitx32(r, 15, 15)
618 /*
619 * It seems that this was added in DF V4.1 (no relation to 4D2). It was reserved
620 * prior to this, so we leave it without a version suffix for now.
621 */
622 #define DF_DRAM_CTL_V4_GET_COL_SWIZ(r) bitx32(r, 11, 11)
623 #define DF_DRAM_CTL_V4_GET_HASH_1G(r) bitx32(r, 10, 10)
624 #define DF_DRAM_CTL_V4_GET_HASH_2M(r) bitx32(r, 9, 9)
625 #define DF_DRAM_CTL_V4_GET_HASH_64K(r) bitx32(r, 8, 8)
626 #define DF_DRAM_CTL_V4D2_GET_HASH_4K(r) bitx32(r, 7, 7)
627 #define DF_DRAM_CTL_V4_GET_REMAP_SEL(r) bitx32(r, 7, 5)
628 #define DF_DRAM_CTL_V4D2_GET_REMAP_SEL(r) bitx32(r, 6, 5)
629 #define DF_DRAM_CTL_V4_GET_REMAP_EN(r) bitx32(r, 4, 4)
630 #define DF_DRAM_CTL_V4_GET_SCM(r) bitx32(r, 2, 2)
631 #define DF_DRAM_CTL_V4_GET_HOLE_EN(r) bitx32(r, 1, 1)
632 #define DF_DRAM_CTL_V4_GET_VALID(r) bitx32(r, 0, 0)
633
634 /*CSTYLED*/
635 #define DF_DRAM_ILV_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_4, \
636 .drd_func = 7, \
637 .drd_reg = 0xe0c + ((x) * 0x10) }
638 /*CSTYLED*/
639 #define DF_DRAM_ILV_V4D2(x) (df_reg_def_t){ .drd_gens = DF_REV_4D2, \
640 .drd_func = 7, \
641 .drd_reg = 0x20c + ((x) * 0x10) }
642 #define DF_DRAM_ILV_V4_GET_SOCK(r) bitx32(r, 18, 18)
643 #define DF_DRAM_ILV_V4_GET_DIE(r) bitx32(r, 13, 12)
644 /*
645 * We're cheating a bit here. We combine the various different non-overlapping
646 * values in the 4D2 variants. In particular, most client parts stick to the
647 * first few values while the rest are sometimes used in the moniker "DF 4.5".
648 * The MI300 has a few non-overlapping gaps.
649 */
650 #define DF_DRAM_ILV_V4D2_GET_CHAN(r) bitx32(r, 9, 4)
651 #define DF_DRAM_ILV_V4D2_CHAN_1 0x0
652 #define DF_DRAM_ILV_V4D2_CHAN_2 0x1
653 #define DF_DRAM_ILV_V4D2_CHAN_4 0x3
654 #define DF_DRAM_ILV_V4D2_CHAN_8 0x5
655 #define DF_DRAM_ILV_V4D2_CHAN_16 0x7
656 #define DF_DRAM_ILV_V4D2_CHAN_32 0x8
657 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_16S8CH_1K 0xc
658 #define DF_DRAM_ILV_V4D2_CHAN_NPS0_24CH_1K 0xe
659 #define DF_DRAM_ILV_V4D2_CHAN_NPS4_2CH_1K 0x10
660 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_4CH_1K 0x11
661 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_8S4CH_1K 0x12
662 #define DF_DRAM_ILV_V4D2_CHAN_NPS4_3CH_1K 0x13
663 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_6CH_1K 0x14
664 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_12CH_1K 0x15
665 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_5CH_1K 0x16
666 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_10CH_1K 0x17
667 #define DF_DRAM_ILV_V4D2_CHAN_MI3H_8CH 0x18
668 #define DF_DRAM_ILV_V4D2_CHAN_MI3H_16CH 0x19
669 #define DF_DRAM_ILV_V4D2_CHAN_MI3H_32CH 0x1a
670 #define DF_DRAM_ILV_V4D2_CHAN_NPS4_2CH_2K 0x20
671 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_4CH_2K 0x21
672 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_8S4CH_2K 0x22
673 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_16S8CH_2K 0x23
674 #define DF_DRAM_ILV_V4D2_CHAN_NPS4_3CH_2K 0x24
675 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_6CH_2K 0x25
676 #define DF_DRAM_ILV_V4D2_CHAN_NPS1_12CH_2K 0x26
677 #define DF_DRAM_ILV_V4D2_CHAN_NPS0_24CH_2K 0x27
678 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_5CH_2K 0x28
679 #define DF_DRAM_ILV_V4D2_CHAN_NPS2_10CH_2K 0x29
680 #define DF_DRAM_ILV_V4_GET_CHAN(r) bitx32(r, 8, 4)
681 #define DF_DRAM_ILV_V4_CHAN_1 0x0
682 #define DF_DRAM_ILV_V4_CHAN_2 0x1
683 #define DF_DRAM_ILV_V4_CHAN_4 0x3
684 #define DF_DRAM_ILV_V4_CHAN_8 0x5
685 #define DF_DRAM_ILV_V4_CHAN_16 0x7
686 #define DF_DRAM_ILV_V4_CHAN_32 0x8
687 #define DF_DRAM_ILV_V4_CHAN_NPS4_2CH 0x10
688 #define DF_DRAM_ILV_V4_CHAN_NPS2_4CH 0x11
689 #define DF_DRAM_ILV_V4_CHAN_NPS1_8CH 0x12
690 #define DF_DRAM_ILV_V4_CHAN_NPS4_3CH 0x13
691 #define DF_DRAM_ILV_V4_CHAN_NPS2_6CH 0x14
692 #define DF_DRAM_ILV_V4_CHAN_NPS1_12CH 0x15
693 #define DF_DRAM_ILV_V4_CHAN_NPS2_5CH 0x16
694 #define DF_DRAM_ILV_V4_CHAN_NPS1_10CH 0x17
695 #define DF_DRAM_ILV_V4_GET_ADDR(r) bitx32(r, 2, 0)
696
697 /*
698 * DF::DramOffset -- These exist only for CS entries, e.g. a UMC. There is
699 * generally only one of these in Zen 1-3. This register changes in Zen 4 and
700 * there are up to 3 instances there. This register corresponds to each DRAM
701 * rule that the UMC has starting at the second one. This is because the first
702 * DRAM rule in a channel always is defined to start at offset 0, so there is no
703 * entry here.
704 */
705 /*CSTYLED*/
706 #define DF_DRAM_OFFSET_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
707 .drd_func = 0, \
708 .drd_reg = 0x1b4 }
709 /*CSTYLED*/
710 #define DF_DRAM_OFFSET_V4(r) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
711 .drd_func = 7, \
712 .drd_reg = 0x140 + ((r) * 4) }
713 #define DF_DRAM_OFFSET_V2_GET_OFFSET(r) bitx32(r, 31, 20)
714 #define DF_DRAM_OFFSET_V3_GET_OFFSET(r) bitx32(r, 31, 12)
715 #define DF_DRAM_OFFSET_V4_GET_OFFSET(r) bitx32(r, 24, 1)
716 #define DF_DRAM_OFFSET_SHIFT 28
717 #define DF_DRAM_OFFSET_GET_EN(r) bitx32(r, 0, 0)
718
719 /*
720 * DF::VGAEn -- This controls whether or not the historical x86 VGA
721 * compatibility region is enabled or not.
722 */
723 /*CSTYLED*/
724 #define DF_VGA_EN_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
725 .drd_func = 0, \
726 .drd_reg = 0x80 }
727 /*CSTYLED*/
728 #define DF_VGA_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
729 .drd_func = 0, \
730 .drd_reg = 0xc08 }
731
732 #define DF_VGA_EN_GET_FABID(r) bitx32(r, 15, 4)
733 #define DF_VGA_EN_GET_CPUDIS(r) bitx32(r, 2, 2)
734 #define DF_VGA_EN_GET_NP(r) bitx32(r, 1, 1)
735 #define DF_VGA_EN_GET_EN(r) bitx32(r, 0, 0)
736
737 /*
738 * DF::MmioPciCfgBaseAddr, DF::MmioPciCfgBaseAddrExt, DF::MmioPciCfgLimitAddr,
739 * DF::MmioPciCfgLimitAddrExt -- These are DFv4 additions that control where PCI
740 * extended configuration space is and whether or not the DF honors this. This
741 * must match the values programmed into the CPU. Prior to DFv4, there was not a
742 * DF setting for this. The encoded values of the base and limit are the same.
743 */
744 /*CSTYLED*/
745 #define DF_ECAM_BASE_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
746 .drd_func = 0, \
747 .drd_reg = 0xc10 }
748 /*CSTYLED*/
749 #define DF_ECAM_BASE_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
750 .drd_func = 0, \
751 .drd_reg = 0xc14 }
752 /*CSTYLED*/
753 #define DF_ECAM_LIMIT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
754 .drd_func = 0, \
755 .drd_reg = 0xc18 }
756 /*CSTYLED*/
757 #define DF_ECAM_LIMIT_EXT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
758 .drd_func = 0, \
759 .drd_reg = 0xc1c }
760 #define DF_ECAM_V4_GET_ADDR(r) bitx32(r, 31, 20)
761 #define DF_ECAM_V4_SET_ADDR(r, v) bitset32(r, 31, 20, v)
762 #define DF_ECAM_V4_ADDR_SHIFT 20
763 #define DF_ECAM_LIMIT_EXCL (1 << DF_ECAM_V4_ADDR_SHIFT)
764 #define DF_ECAM_BASE_V4_GET_EN(r) bitx32(r, 0, 0)
765 #define DF_ECAM_BASE_V4_SET_EN(r, v) bitset32(r, 0, 0, v)
766 #define DF_ECAM_EXT_V4_GET_ADDR(r) bitx32(r, 23, 0)
767 #define DF_ECAM_EXT_V4_SET_ADDR(r, v) bitset32(r, 23, 0, v)
768 #define DF_ECAM_EXT_V4_ADDR_SHIFT 32
769
770 /*
771 * DF::MmioBaseAddress, DF::MmioLimitAddress, DF::MmioAddressControl -- These
772 * control the various MMIO rules for a given system.
773 */
774 /*CSTYLED*/
775 #define DF_MMIO_BASE_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
776 .drd_func = 0, \
777 .drd_reg = 0x200 + ((x) * 0x10) }
778 /*CSTYLED*/
779 #define DF_MMIO_LIMIT_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
780 .drd_func = 0, \
781 .drd_reg = 0x204 + ((x) * 0x10) }
782 /*CSTYLED*/
783 #define DF_MMIO_BASE_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
784 .drd_func = 0, \
785 .drd_reg = 0xd80 + ((x) * 0x10) }
786 /*CSTYLED*/
787 #define DF_MMIO_LIMIT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
788 .drd_func = 0, \
789 .drd_reg = 0xd84 + ((x) * 0x10) }
790 #define DF_MMIO_SHIFT 16
791 #define DF_MMIO_LIMIT_EXCL (1 << DF_MMIO_SHIFT)
792 #define DF_MAX_MMIO_RULES 16
793 #define DF_MAX_MMIO_RULES_TURIN 32
794 /*CSTYLED*/
795 #define DF_MMIO_CTL_V2(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
796 .drd_func = 0, \
797 .drd_reg = 0x208 + ((x) * 0x10) }
798 /*CSTYLED*/
799 #define DF_MMIO_CTL_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
800 .drd_func = 0, \
801 .drd_reg = 0xd88 + ((x) * 0x10) }
802 #define DF_MMIO_CTL_V2_GET_NP(r) bitx32(r, 12, 12)
803 #define DF_MMIO_CTL_V2_GET_DEST_ID(r) bitx32(r, 11, 4)
804 #define DF_MMIO_CTL_V2_SET_NP(r, v) bitset32(r, 12, 12, v)
805 #define DF_MMIO_CTL_V2_SET_DEST_ID(r, v) bitset32(r, 11, 4, v)
806
807 #define DF_MMIO_CTL_V3_GET_NP(r) bitx32(r, 16, 16)
808 #define DF_MMIO_CTL_V3_GET_DEST_ID(r) bitx32(r, 13, 4)
809 #define DF_MMIO_CTL_V3P5_GET_DEST_ID(r) bitx32(r, 7, 4)
810 #define DF_MMIO_CTL_V3_SET_NP(r, v) bitset32(r, 16, 16, v)
811 #define DF_MMIO_CTL_V3_SET_DEST_ID(r, v) bitset32(r, 13, 4, v)
812 #define DF_MMIO_CTL_V3P5_SET_DEST_ID(r, v) bitset32(r, 7, 4, v)
813
814 #define DF_MMIO_CTL_V4_GET_DEST_ID(r) bitx32(r, 27, 16)
815 #define DF_MMIO_CTL_V4D2_GET_DEST_ID(r) bitx32(r, 23, 16)
816 #define DF_MMIO_CTL_V4_GET_NP(r) bitx32(r, 3, 3)
817 #define DF_MMIO_CTL_V4_SET_DEST_ID(r, v) bitset32(r, 27, 16, v)
818 #define DF_MMIO_CTL_V4D2_SET_DEST_ID(r, v) bitset32(r, 23, 16, v)
819 #define DF_MMIO_CTL_V4_SET_NP(r, v) bitset32(r, 3, 3, v)
820
821 #define DF_MMIO_CTL_GET_CPU_DIS(r) bitx32(r, 2, 2)
822 #define DF_MMIO_CTL_GET_WE(r) bitx32(r, 1, 1)
823 #define DF_MMIO_CTL_GET_RE(r) bitx32(r, 0, 0)
824 #define DF_MMIO_CTL_SET_CPU_DIS(r, v) bitset32(r, 2, 2, v)
825 #define DF_MMIO_CTL_SET_WE(r, v) bitset32(r, 1, 1, v)
826 #define DF_MMIO_CTL_SET_RE(r, v) bitset32(r, 0, 0, v)
827
828 /*
829 * DF::MmioExtAddress -- New in DFv4, this allows extending the number of bits
830 * used for MMIO.
831 */
832 /*CSTYLED*/
833 #define DF_MMIO_EXT_V4(x) (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
834 .drd_func = 0, \
835 .drd_reg = 0xd8c + ((x) * 0x10) }
836 #define DF_MMIO_EXT_V4_GET_LIMIT(r) bitx32(r, 23, 16)
837 #define DF_MMIO_EXT_V4_GET_BASE(r) bitx32(r, 7, 0)
838 #define DF_MMIO_EXT_V4_SET_LIMIT(r, v) bitset32(r, 23, 16, v)
839 #define DF_MMIO_EXT_V4_SET_BASE(r, v) bitset32(r, 7, 0, v)
840 #define DF_MMIO_EXT_SHIFT 48
841
842 /*
843 * DF::DfGlobalCtrl -- This register we generally only care about in the
844 * DFv3/3.5 timeframe when it has the actual hash controls, hence its current
845 * definition. It technically exists in DFv2/v4, but is not relevant.
846 */
847 /*CSTYLED*/
848 #define DF_GLOB_CTL_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
849 .drd_func = 0, \
850 .drd_reg = 0x3F8 }
851 #define DF_GLOB_CTL_V3_GET_HASH_1G(r) bitx32(r, 22, 22)
852 #define DF_GLOB_CTL_V3_GET_HASH_2M(r) bitx32(r, 21, 21)
853 #define DF_GLOB_CTL_V3_GET_HASH_64K(r) bitx32(r, 20, 20)
854
855 /*
856 * DF::SystemCfg -- This register describes the basic information about the data
857 * fabric that we're talking to. Don't worry, this is different in every
858 * generation, even when the address is the same. Somehow despite all these
859 * differences the actual things like defined types are somehow the same.
860 */
861 typedef enum {
862 DF_DIE_TYPE_CPU = 0,
863 DF_DIE_TYPE_APU,
864 DF_DIE_TYPE_dGPU
865 } df_die_type_t;
866
867 /*CSTYLED*/
868 #define DF_SYSCFG_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \
869 .drd_func = 1, \
870 .drd_reg = 0x200 }
871 #define DF_SYSCFG_V2_GET_SOCK_ID(r) bitx32(r, 27, 27)
872 #define DF_SYSCFG_V2_GET_DIE_ID(r) bitx32(r, 25, 24)
873 #define DF_SYSCFG_V2_GET_MY_TYPE(r) bitx32(r, 22, 21)
874 #define DF_SYSCFG_V2_GET_LOCAL_IS_ME(r) bitx32(r, 19, 16)
875 #define DF_SYSCFG_V2_GET_LOCAL_TYPE3(r) bitx32(r, 13, 12)
876 #define DF_SYSCFG_V2_GET_LOCAL_TYPE2(r) bitx32(r, 11, 10)
877 #define DF_SYSCFG_V2_GET_LOCAL_TYPE1(r) bitx32(r, 9, 8)
878 #define DF_SYSCFG_V2_GET_LOCAL_TYPE0(r) bitx32(r, 7, 6)
879 #define DF_SYSCFG_V2_GET_OTHER_SOCK(r) bitx32(r, 5, 5)
880 #define DF_SYSCFG_V2_GET_DIE_PRESENT(r) bitx32(r, 4, 0)
881 #define DF_SYSCFG_V2_DIE_PRESENT(x) bitx32(r, 3, 0)
882
883 /*CSTYLED*/
884 #define DF_SYSCFG_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
885 .drd_func = 1, \
886 .drd_reg = 0x200 }
887 #define DF_SYSCFG_V3_GET_NODE_ID(r) bitx32(r, 30, 28)
888 #define DF_SYSCFG_V3_GET_OTHER_SOCK(r) bitx32(r, 27, 27)
889 #define DF_SYSCFG_V3_GET_OTHER_TYPE(r) bitx32(r, 26, 25)
890 #define DF_SYSCFG_V3_GET_MY_TYPE(r) bitx32(r, 24, 23)
891 #define DF_SYSCFG_V3_GET_DIE_TYPE(r) bitx32(r, 18, 11)
892 #define DF_SYSCFG_V3_GET_DIE_PRESENT(r) bitx32(r, 7, 0)
893
894 /*CSTYLED*/
895 #define DF_SYSCFG_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \
896 .drd_func = 1, \
897 .drd_reg = 0x140 }
898 #define DF_SYSCFG_V3P5_GET_NODE_ID(r) bitx32(r, 19, 16)
899 #define DF_SYSCFG_V3P5_GET_OTHER_SOCK(r) bitx32(r, 8, 8)
900 #define DF_SYSCFG_V3P5_GET_NODE_MAP(r) bitx32(r, 4, 4)
901 #define DF_SYSCFG_V3P5_GET_OTHER_TYPE(r) bitx32(r, 3, 2)
902 #define DF_SYSCFG_V3P5_GET_MY_TYPE(r) bitx32(r, 1, 0)
903
904 /*CSTYLED*/
905 #define DF_SYSCFG_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
906 .drd_func = 4, \
907 .drd_reg = 0x180 }
908 #define DF_SYSCFG_V4_GET_NODE_ID(r) bitx32(r, 27, 16)
909 #define DF_SYSCFG_V4_GET_OTHER_SOCK(r) bitx32(r, 8, 8)
910 #define DF_SYSCFG_V4_GET_NODE_MAP(r) bitx32(r, 4, 4)
911 #define DF_SYSCFG_V4_GET_OTHER_TYPE(r) bitx32(r, 3, 2)
912 #define DF_SYSCFG_V4_GET_MY_TYPE(r) bitx32(r, 1, 0)
913
914 /*
915 * DF::SystemComponentCnt -- Has a count of how many things are here. However,
916 * this does not seem defined for DFv3.5
917 */
918 /*CSTYLED*/
919 #define DF_COMPCNT_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
920 .drd_func = 1, \
921 .drd_reg = 0x204 }
922 #define DF_COMPCNT_V2_GET_IOMS(r) bitx32(r, 23, 16)
923 #define DF_COMPCNT_V2_GET_GCM(r) bitx32(r, 15, 8)
924 #define DF_COMPCNT_V2_GET_PIE(r) bitx32(r, 7, 0)
925
926 /*CSTYLED*/
927 #define DF_COMPCNT_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
928 .drd_func = 4, \
929 .drd_reg = 0x184 }
930 #define DF_COMPCNT_V4_GET_IOS(r) bitx32(r, 31, 26)
931 #define DF_COMPCNT_V4_GET_GCM(r) bitx32(r, 25, 16)
932 #define DF_COMPCNT_V4_GET_IOM(r) bitx32(r, 15, 8)
933 #define DF_COMPCNT_V4_GET_PIE(r) bitx32(r, 7, 0)
934
935 /*
936 * This next section contains a bunch of register definitions for how to take
937 * apart ID masks. The register names and sets have changed across every DF
938 * revision. This will be done in chunks that define all DFv2, then v3, etc.
939 */
940
941 /*
942 * DF::SystemFabricIdMask -- DFv2 style breakdowns of IDs. Note, unlike others
943 * the socket and die shifts are not relative to a node mask, but are global.
944 */
945 /*CSTYLED*/
946 #define DF_FIDMASK_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \
947 .drd_func = 1, \
948 .drd_reg = 0x208 }
949 #define DF_FIDMASK_V2_GET_SOCK_SHIFT(r) bitx32(r, 31, 28)
950 #define DF_FIDMASK_V2_GET_DIE_SHIFT(r) bitx32(r, 27, 24)
951 #define DF_FIDMASK_V2_GET_SOCK_MASK(r) bitx32(r, 23, 16)
952 #define DF_FIDMASK_V2_GET_DIE_MASK(r) bitx32(r, 15, 8)
953
954 /*
955 * DF::SystemFabricIdMask0, DF::SystemFabricIdMask1 -- The DFv3 variant of
956 * breaking down an ID into bits and shifts. Unlike in DFv2, the socket and die
957 * are relative to a node ID. For more, see amdzen_determine_fabric_decomp() in
958 * uts/intel/io/amdzen/amdzen.c.
959 */
960 /*CSTYLED*/
961 #define DF_FIDMASK0_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
962 .drd_func = 1, \
963 .drd_reg = 0x208 }
964 #define DF_FIDMASK0_V3_GET_NODE_MASK(r) bitx32(r, 25, 16)
965 #define DF_FIDMASK0_V3_GET_COMP_MASK(r) bitx32(r, 9, 0)
966 /*CSTYLED*/
967 #define DF_FIDMASK1_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
968 .drd_func = 1, \
969 .drd_reg = 0x20c }
970 #define DF_FIDMASK1_V3_GET_SOCK_MASK(r) bitx32(r, 26, 24)
971 #define DF_FIDMASK1_V3_GET_DIE_MASK(r) bitx32(r, 18, 16)
972 #define DF_FIDMASK1_V3_GET_SOCK_SHIFT(r) bitx32(r, 9, 8)
973 #define DF_FIDMASK1_V3_GET_NODE_SHIFT(r) bitx32(r, 3, 0)
974
975 /*
976 * DF::SystemFabricIdMask0, DF::SystemFabricIdMask1, DF::SystemFabricIdMask2 --
977 * DFv3.5 and DFv4 have the same format here, but in different registers.
978 */
979 /*CSTYLED*/
980 #define DF_FIDMASK0_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \
981 .drd_func = 1, \
982 .drd_reg = 0x150 }
983 /*CSTYLED*/
984 #define DF_FIDMASK0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
985 .drd_func = 4, \
986 .drd_reg = 0x1b0 }
987 #define DF_FIDMASK0_V3P5_GET_NODE_MASK(r) bitx32(r, 31, 16)
988 #define DF_FIDMASK0_V3P5_GET_COMP_MASK(r) bitx32(r, 15, 0)
989 /*CSTYLED*/
990 #define DF_FIDMASK1_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \
991 .drd_func = 1, \
992 .drd_reg = 0x154 }
993 /*CSTYLED*/
994 #define DF_FIDMASK1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
995 .drd_func = 4, \
996 .drd_reg = 0x1b4 }
997 #define DF_FIDMASK1_V3P5_GET_SOCK_SHIFT(r) bitx32(r, 11, 8)
998 #define DF_FIDMASK1_V3P5_GET_NODE_SHIFT(r) bitx32(r, 3, 0)
999 /*CSTYLED*/
1000 #define DF_FIDMASK2_V3P5 (df_reg_def_t){ .drd_gens = DF_REV_3P5, \
1001 .drd_func = 1, \
1002 .drd_reg = 0x158 }
1003 /*CSTYLED*/
1004 #define DF_FIDMASK2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1005 .drd_func = 4, \
1006 .drd_reg = 0x1b8 }
1007 #define DF_FIDMASK2_V3P5_GET_SOCK_MASK(r) bitx32(r, 31, 16)
1008 #define DF_FIDMASK2_V3P5_GET_DIE_MASK(r) bitx32(r, 15, 0)
1009
1010 /*
1011 * DF::DieFabricIdMask -- This is a Zeppelin, DFv2 special. There are a couple
1012 * instances of this for different types of devices; however, this is where the
1013 * component mask is actually stored. This is replicated for a CPU, APU, and
1014 * dGPU, each with slightly different values. We need to look at DF_SYSCFG_V2 to
1015 * determine which type of die we have and use the appropriate one when looking
1016 * at this. This makes the Zen 1 CPUs and APUs have explicitly different set up
1017 * here. Look, it got better in DFv3.
1018 */
1019 /*CSTYLED*/
1020 #define DF_DIEMASK_CPU_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \
1021 .drd_func = 1, \
1022 .drd_reg = 0x22c }
1023 /*CSTYLED*/
1024 #define DF_DIEMASK_APU_V2 (df_reg_def_t){ .drd_gens = DF_REV_2, \
1025 .drd_func = 1, \
1026 .drd_reg = 0x24c }
1027 #define DF_DIEMASK_V2_GET_SOCK_SHIFT(r) bitx32(r, 31, 28)
1028 #define DF_DIEMASK_V2_GET_DIE_SHIFT(r) bitx32(r, 27, 24)
1029 #define DF_DIEMASK_V2_GET_SOCK_MASK(r) bitx32(r, 23, 16)
1030 #define DF_DIEMASK_V2_GET_DIE_MASK(r) bitx32(r, 15, 8)
1031 #define DF_DIEMASK_V2_GET_COMP_MASK(r) bitx32(r, 7, 0)
1032
1033 /*
1034 * DF::CCDEnable -- This register is present for CCMs and ACMs. Despite its
1035 * name, the interpretation is not quite straightforward. That is, it only
1036 * indirectly tells us about whether or not there are two CCDs or not. A CCM
1037 * port can be in wide mode where its two SDPs (Scalable Data Ports) are in fact
1038 * instead connected to a single CCD. If wide mode is enabled in DF::CCMConfig4,
1039 * then a value of 0x3 just indicates that both SDP ports are connected to a
1040 * single CCD. For DFv4D2, the wide mode bit is moved from DF::CCMConfig4 to
1041 * this register itself.
1042 *
1043 * The CCX related fields are only valid when the dense mode is enabled in the
1044 * global DF controls. If a CPU doesn't support that, then that field is
1045 * reserved. We don't generally recommend this as a way of determining if
1046 * multiple CCX units are present on the CCD because it is tied to DFv4.
1047 */
1048 #define DF_MAX_CCDS_PER_CCM 2
1049 /*CSTYLED*/
1050 #define DF_CCD_EN_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1051 .drd_func = 1, \
1052 .drd_reg = 0x104 }
1053 #define DF_CCD_EN_V4D2_GET_WIDE_EN(r) bitx32(r, 31, 31)
1054 #define DF_CCD_EN_V4_GET_CCX_EN(r) bitx32(r, 17, 16)
1055 #define DF_CCD_EN_V4_GET_CCD_EN(r) bitx32(r, 1, 0)
1056
1057
1058 /*
1059 * DF::PhysicalCoreEnable0, etc. -- These registers can be used to tell us which
1060 * cores are actually enabled. This appears to have been introduced in DFv3.
1061 * DFv4 expanded this from two registers to several more. The number that are
1062 * valid vary based upon the CPU family.
1063 */
1064 /*CSTYLED*/
1065 #define DF_PHYS_CORE_EN0_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
1066 .drd_func = 1, \
1067 .drd_reg = 0x300 }
1068 /*CSTYLED*/
1069 #define DF_PHYS_CORE_EN1_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
1070 .drd_func = 1, \
1071 .drd_reg = 0x304 }
1072 /*CSTYLED*/
1073 #define DF_PHYS_CORE_EN0_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1074 .drd_func = 1, \
1075 .drd_reg = 0x140 }
1076 /*CSTYLED*/
1077 #define DF_PHYS_CORE_EN1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1078 .drd_func = 1, \
1079 .drd_reg = 0x144 }
1080 /*CSTYLED*/
1081 #define DF_PHYS_CORE_EN2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1082 .drd_func = 1, \
1083 .drd_reg = 0x148 }
1084 /*CSTYLED*/
1085 #define DF_PHYS_CORE_EN3_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1086 .drd_func = 1, \
1087 .drd_reg = 0x14c }
1088 /*CSTYLED*/
1089 #define DF_PHYS_CORE_EN4_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1090 .drd_func = 1, \
1091 .drd_reg = 0x150 }
1092 /*CSTYLED*/
1093 #define DF_PHYS_CORE_EN5_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1094 .drd_func = 1, \
1095 .drd_reg = 0x154 }
1096
1097 /*
1098 * DF::Np2ChannelConfig -- This is used in Milan to contain information about
1099 * how non-power of 2 based channel configuration works. Note, we only know that
1100 * this exists in Milan (and its ThreadRipper equivalent). We don't believe it
1101 * is in other DFv3 products like Rome, Matisse, Vermeer, or the APUs.
1102 */
1103 /*CSTYLED*/
1104 #define DF_NP2_CONFIG_V3 (df_reg_def_t){ .drd_gens = DF_REV_3, \
1105 .drd_func = 2, \
1106 .drd_reg = 0x90 }
1107 #define DF_NP2_CONFIG_V3_GET_SPACE1(r) bitx32(r, 13, 8)
1108 #define DF_NP2_CONFIG_V3_GET_SPACE0(r) bitx32(r, 5, 0)
1109
1110 /*
1111 * DF::CCMConfig4 -- This is one of several CCM configuration related registers.
1112 * This varies in each DF revision. That is, while we've found it does exist in
1113 * DFv3, it is at a different address and the bits have rather different
1114 * meanings. A subset of the bits are defined below based upon our needs.
1115 * The wide mode bit is moved to DF::CCDEnable in DFv4D2.
1116 */
1117 /*CSTYLED*/
1118 #define DF_CCMCFG4_V4 (df_reg_def_t){ .drd_gens = DF_REV_4, \
1119 .drd_func = 3, \
1120 .drd_reg = 0x510 }
1121 #define DF_CCMCFG4_V4_GET_WIDE_EN(r) bitx32(r, 26, 26)
1122
1123 /*
1124 * DF::FabricIndirectConfigAccessAddress, DF::FabricIndirectConfigAccessDataLo,
1125 * DF::FabricIndirectConfigAccessDataHi -- These registers are used to define
1126 * Indirect Access, commonly known as FICAA and FICAD for the system. While
1127 * there are multiple copies of the indirect access registers in device 4, we're
1128 * only allowed access to one set of those (which are the ones present here).
1129 * Specifically the OS is given access to set 3.
1130 */
1131 /*CSTYLED*/
1132 #define DF_FICAA_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
1133 .drd_func = 4, \
1134 .drd_reg = 0x5c }
1135 #define DF_FICAA_V2_REG_MASK 0x7fc
1136 /*CSTYLED*/
1137 #define DF_FICAA_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1138 .drd_func = 4, \
1139 .drd_reg = 0x8c }
1140 #define DF_FICAA_V4_REG_MASK 0xffc
1141 /*
1142 * Across all current versions, the register ignores the lower 2 bits.
1143 * That is we can only address and encode things in units of 4 bytes.
1144 */
1145 #define DF_FICAA_REG_SHIFT 2
1146
1147 #define DF_FICAA_V2_SET_INST(r, v) bitset32(r, 23, 16, v)
1148 #define DF_FICAA_V2_SET_64B(r, v) bitset32(r, 14, 14, v)
1149 #define DF_FICAA_V2_SET_FUNC(r, v) bitset32(r, 13, 11, v)
1150 #define DF_FICAA_V2_SET_REG(r, v) bitset32(r, 10, 2, v)
1151 #define DF_FICAA_V2_SET_TARG_INST(r, v) bitset32(r, 0, 0, v)
1152
1153 #define DF_FICAA_V4_SET_REG(r, v) bitset32(r, 10, 1, v)
1154
1155 /*CSTYLED*/
1156 #define DF_FICAD_LO_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
1157 .drd_func = 4, \
1158 .drd_reg = 0x98}
1159 /*CSTYLED*/
1160 #define DF_FICAD_HI_V2 (df_reg_def_t){ .drd_gens = DF_REV_ALL_23, \
1161 .drd_func = 4, \
1162 .drd_reg = 0x9c}
1163 /*CSTYLED*/
1164 #define DF_FICAD_LO_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1165 .drd_func = 4, \
1166 .drd_reg = 0xb8}
1167 /*CSTYLED*/
1168 #define DF_FICAD_HI_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1169 .drd_func = 4, \
1170 .drd_reg = 0xbc}
1171
1172 /*
1173 * Check whether a given register definition is valid for the given DF revision.
1174 */
1175 static inline boolean_t
df_reg_valid(const df_rev_t rev,const df_reg_def_t def)1176 df_reg_valid(const df_rev_t rev, const df_reg_def_t def)
1177 {
1178 uint16_t mask;
1179
1180 switch (rev) {
1181 case DF_REV_2:
1182 case DF_REV_3:
1183 case DF_REV_3P5:
1184 mask = DF_FICAA_V2_REG_MASK;
1185 break;
1186 case DF_REV_4:
1187 case DF_REV_4D2:
1188 mask = DF_FICAA_V4_REG_MASK;
1189 break;
1190 default:
1191 return (B_FALSE);
1192 }
1193
1194 return ((def.drd_gens & rev) == rev && (def.drd_reg & ~mask) == 0);
1195 }
1196
1197 /*
1198 * DF::SpecialSysFunctionFabricID1, DF::SpecialSysFunctionFabricID2 -- These
1199 * registers are used to look up the FabricID of various functional groups.
1200 * These exist in DFv3 and DFv4 at different addresses with slightly different
1201 * field widths.
1202 */
1203 /*CSTYLED*/
1204 #define DF_SYS_FUN_FID1_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
1205 .drd_func = 1, \
1206 .drd_reg = 0x60 }
1207 #define DF_SYS_FUN_FID1_V3_GET_MSTR_PIE_FID(r) bitx32(r, 21, 16)
1208 #define DF_SYS_FUN_FID1_V3_GET_LCL_PIE_FID(r) bitx32(r, 5, 0)
1209
1210 /*CSTYLED*/
1211 #define DF_SYS_FUN_FID1_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1212 .drd_func = 4, \
1213 .drd_reg = 0x190 }
1214 #define DF_SYS_FUN_FID1_V4_GET_MSTR_PIE_FID(r) bitx32(r, 27, 16)
1215 #define DF_SYS_FUN_FID1_V4D2_GET_MSTR_PIE_FID(r) bitx32(r, 23, 16)
1216 #define DF_SYS_FUN_FID1_V4_GET_LCL_PIE_FID(r) bitx32(r, 11, 0)
1217 #define DF_SYS_FUN_FID1_V4D2_GET_LCL_PIE_FID(r) bitx32(r, 7, 0)
1218
1219 /*CSTYLED*/
1220 #define DF_SYS_FUN_FID2_V3 (df_reg_def_t){ .drd_gens = DF_REV_ALL_3, \
1221 .drd_func = 1, \
1222 .drd_reg = 0x64 }
1223 #define DF_SYS_FUN_FID2_V3_GET_FCH_IOMS_FID(r) bitx32(r, 21, 16)
1224 #define DF_SYS_FUN_FID2_V3_GET_LCL_IOMS_FID(r) bitx32(r, 5, 0)
1225
1226 /*CSTYLED*/
1227 #define DF_SYS_FUN_FID2_V4 (df_reg_def_t){ .drd_gens = DF_REV_ALL_4, \
1228 .drd_func = 4, \
1229 .drd_reg = 0x194 }
1230 #define DF_SYS_FUN_FID2_V4_GET_FCH_IOS_FID(r) bitx32(r, 27, 16)
1231 #define DF_SYS_FUN_FID2_V4D2_GET_FCH_IOS_FID(r) bitx32(r, 23, 16)
1232
1233 #ifdef __cplusplus
1234 }
1235 #endif
1236
1237 #endif /* _SYS_AMDZEN_DF_H */
1238