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Searched refs:CSR_FR (Results 1 – 4 of 4) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_csr.h50 #define CSR_FR(base, off, bit) \ macro
H A Dpx_hlib.c740 link_width = CSR_FR(csr_base, TLU_LINK_STATUS, WIDTH); in lpu_init()
767 max_payload = ((CSR_FR(csr_base, TLU_CONTROL, CONFIG) & in lpu_init()
2518 *msiq_id = CSR_FR((caddr_t)dev_hdl, PM_PME_MAPPING, EQNUM); in hvio_msg_getmsiq()
2521 *msiq_id = CSR_FR((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, in hvio_msg_getmsiq()
2525 *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_COR_MAPPING, EQNUM); in hvio_msg_getmsiq()
2528 *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, in hvio_msg_getmsiq()
2532 *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_FATAL_MAPPING, EQNUM); in hvio_msg_getmsiq()
3020 ltssm_state = CSR_FR(csr_base, LPU_LTSSM_STATUS1, LTSSM_STATE); in px_link_wait4l1idle()
H A Dpx_err.c1522 (caddr_t)CSR_FR(csr_base, DMCINT_ODCD_ERROR_LOG, ADDRESS); in px_jbc_pcitool_addr_match()
1795 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID); in px_err_mmu_rbne_handle()
1825 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID); in px_err_mmu_tfa_handle()
1856 bdf = (pcie_req_id_t)CSR_FR(csr_base, MMU_TRANSLATION_FAULT_STATUS, ID); in px_err_mmu_parity_handle()
H A Dpx_lib4u.c2693 link_width = CSR_FR(csr_base, TLU_LINK_STATUS, WIDTH); in px_lib_set_root_complex_mps()