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Searched refs:write_reg (Results 1 – 25 of 36) sorted by relevance

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/freebsd/sys/dev/flash/flexspi/
H A Dflex_spi.c140 write_reg(struct flex_spi_softc *sc, uint32_t offset, uint32_t value) in write_reg() function
198 write_reg(sc, FSPI_LUTKEY, FSPI_LUTKEY_VALUE); in flex_spi_prepare_lut()
199 write_reg(sc, FSPI_LCKCR, FSPI_LCKER_UNLOCK); in flex_spi_prepare_lut()
208 write_reg(sc, FSPI_LUT_REG(lut_id), lut); in flex_spi_prepare_lut()
209 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0); in flex_spi_prepare_lut()
214 write_reg(sc, FSPI_LUT_REG(lut_id), lut); in flex_spi_prepare_lut()
217 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, lut); in flex_spi_prepare_lut()
218 write_reg(sc, FSPI_LUT_REG(lut_id) + 8, 0); in flex_spi_prepare_lut()
223 write_reg(sc, FSPI_LUT_REG(lut_id), lut); in flex_spi_prepare_lut()
224 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0); in flex_spi_prepare_lut()
[all …]
/freebsd/sys/dev/e1000/
H A De1000_82541.c106 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82541()
713 ret_val = phy->ops.write_reg(hw, in e1000_config_dsp_after_link_change_82541()
744 ret_val = phy->ops.write_reg(hw, in e1000_config_dsp_after_link_change_82541()
768 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); in e1000_config_dsp_after_link_change_82541()
774 ret_val = phy->ops.write_reg(hw, 0x0000, in e1000_config_dsp_after_link_change_82541()
788 ret_val = phy->ops.write_reg(hw, in e1000_config_dsp_after_link_change_82541()
795 ret_val = phy->ops.write_reg(hw, 0x0000, in e1000_config_dsp_after_link_change_82541()
803 ret_val = phy->ops.write_reg(hw, 0x2F5B, in e1000_config_dsp_after_link_change_82541()
825 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); in e1000_config_dsp_after_link_change_82541()
831 ret_val = phy->ops.write_reg(hw, 0x0000, in e1000_config_dsp_after_link_change_82541()
[all …]
H A De1000_phy.c93 phy->ops.write_reg = e1000_null_write_reg; in e1000_init_phy_ops_generic()
271 if (!hw->phy.ops.write_reg) in e1000_phy_reset_dsp_generic()
274 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); in e1000_phy_reset_dsp_generic()
278 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); in e1000_phy_reset_dsp_generic()
1045 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); in e1000_set_master_slave_mode()
1079 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); in e1000_copper_link_setup_82577()
1105 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); in e1000_copper_link_setup_82577()
1178 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, in e1000_copper_link_setup_m88()
1193 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); in e1000_copper_link_setup_m88()
1222 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, in e1000_copper_link_setup_m88()
[all …]
H A De1000_82575.c201 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; in e1000_init_phy_params_82575()
208 phy->ops.write_reg = e1000_write_phy_reg_82580; in e1000_init_phy_params_82575()
213 phy->ops.write_reg = e1000_write_phy_reg_gs40g; in e1000_init_phy_params_82575()
217 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82575()
285 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2); in e1000_init_phy_params_82575()
724 if (!(hw->phy.ops.write_reg)) in e1000_phy_hw_reset_sgmii_82575()
731 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); in e1000_phy_hw_reset_sgmii_82575()
775 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
784 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_82575()
790 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82575()
[all …]
H A De1000_82540.c84 phy->ops.write_reg = e1000_write_phy_reg_m88; in e1000_init_phy_params_82540()
435 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, in e1000_setup_copper_link_82540()
513 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL, in e1000_adjust_serdes_amplitude_82540()
544 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); in e1000_set_vco_speed_82540()
553 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); in e1000_set_vco_speed_82540()
559 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); in e1000_set_vco_speed_82540()
568 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); in e1000_set_vco_speed_82540()
572 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, in e1000_set_vco_speed_82540()
605 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, in e1000_set_phy_mode_82540()
611 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, in e1000_set_phy_mode_82540()
H A De1000_80003es2lan.c120 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; in e1000_init_phy_params_80003es2lan()
608 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
623 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); in e1000_phy_force_speed_duplex_80003es2lan()
671 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, in e1000_phy_force_speed_duplex_80003es2lan()
985 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1025 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1058 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); in e1000_copper_link_setup_gg82563_80003es2lan()
1077 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1088 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, in e1000_copper_link_setup_gg82563_80003es2lan()
1102 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); in e1000_copper_link_setup_gg82563_80003es2lan()
[all …]
H A De1000_82543.c116 phy->ops.write_reg = (hw->mac.type == e1000_82543) in e1000_init_phy_params_82543()
774 if (!(hw->phy.ops.write_reg)) in e1000_polarity_reversal_workaround_82543()
781 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); in e1000_polarity_reversal_workaround_82543()
784 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); in e1000_polarity_reversal_workaround_82543()
788 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); in e1000_polarity_reversal_workaround_82543()
820 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); in e1000_polarity_reversal_workaround_82543()
824 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); in e1000_polarity_reversal_workaround_82543()
828 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); in e1000_polarity_reversal_workaround_82543()
832 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); in e1000_polarity_reversal_workaround_82543()
836 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); in e1000_polarity_reversal_workaround_82543()
H A De1000_ich8lan.c478 phy->ops.write_reg = e1000_write_phy_reg_hv; in e1000_init_phy_params_pchlan()
572 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_ich8lan()
581 phy->ops.write_reg = e1000_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
623 phy->ops.write_reg = e1000_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
1089 ret_val = hw->phy.ops.write_reg(hw, I217_INBAND_CTRL, reg); in e1000_k1_workaround_lpt_lp()
1788 hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); in e1000_check_for_copper_link_ich8lan()
2628 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_MODE_CTRL, data); in e1000_set_mdio_slow_mode_hv()
2659 ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2664 ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, in e1000_hv_phy_workarounds_ich8lan()
2676 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, in e1000_hv_phy_workarounds_ich8lan()
[all …]
H A De1000_82571.c124 phy->ops.write_reg = e1000_write_phy_reg_igp; in e1000_init_phy_params_82571()
137 phy->ops.write_reg = e1000_write_phy_reg_m88; in e1000_init_phy_params_82571()
152 phy->ops.write_reg = e1000_write_phy_reg_bm2; in e1000_init_phy_params_82571()
887 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82571()
898 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_82571()
904 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, in e1000_set_d0_lplu_state_82571()
919 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82571()
932 ret_val = phy->ops.write_reg(hw, in e1000_set_d0_lplu_state_82571()
H A De1000_api.c1061 if (hw->phy.ops.write_reg) in e1000_write_phy_reg()
1062 return hw->phy.ops.write_reg(hw, offset, data); in e1000_write_phy_reg()
/freebsd/sys/dev/iicbus/rtc/
H A Dnxprtc.c298 write_reg(struct nxprtc_softc *sc, uint8_t reg, uint8_t val) in write_reg() function
379 err = write_reg(sc, PCF2127_R_AGING_OFFSET, sc->freqadj); in freqadj_sysctl()
414 err = write_reg(sc, PCF8523_R_CS3, PCF8523_B_CS3_PM_STD); in pcf8523_battery_check()
424 err = write_reg(sc, PCF8523_R_CS3, PCF8523_B_CS3_PM_DSNBM); in pcf8523_battery_check()
478 err = write_reg(sc, PCF85xx_R_CS1, 0); in pcf8523_start()
485 err = write_reg(sc, PCF2127_R_TS_CTL, PCF2127_B_TSOFF); in pcf8523_start()
493 err = write_reg(sc, PCF8523_R_TMR_CLKOUT, clkout); in pcf8523_start()
495 err = write_reg(sc, PCF8523_R_TMR_CLKOUT, in pcf8523_start()
507 if ((err = write_reg(sc, PCF8523_R_TMR_CLKOUT, clkout)) != 0) { in pcf8523_start()
575 if ((err = write_reg(sc, sc->tmcaddr, 0)) != 0) in pcf8523_start_timer()
[all …]
H A Dds13rtc.c211 write_reg(struct ds13rtc_softc *sc, uint8_t reg, uint8_t val) in write_reg() function
305 write_reg(sc, ctlreg, 0); in ds13rtc_start()
461 err = write_reg(sc, sc->osfaddr, statreg); in ds13rtc_settime()
/freebsd/sys/dev/igc/
H A Digc_phy.c37 phy->ops.write_reg = igc_null_write_reg; in igc_init_phy_ops_generic()
441 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); in igc_phy_setup_autoneg()
448 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, in igc_phy_setup_autoneg()
452 ret_val = phy->ops.write_reg(hw, in igc_phy_setup_autoneg()
505 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); in igc_copper_link_autoneg()
671 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, in igc_set_d3_lplu_state_generic()
688 ret_val = phy->ops.write_reg(hw, in igc_set_d3_lplu_state_generic()
701 ret_val = phy->ops.write_reg(hw, in igc_set_d3_lplu_state_generic()
711 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, in igc_set_d3_lplu_state_generic()
723 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG, in igc_set_d3_lplu_state_generic()
[all …]
H A Digc_api.c473 if (hw->phy.ops.write_reg) in igc_write_phy_reg()
474 return hw->phy.ops.write_reg(hw, offset, data); in igc_write_phy_reg()
H A Digc_hw.h394 s32 (*write_reg)(struct igc_hw *, u32, u16); member
/freebsd/sys/dev/sume/
H A Dif_sume.c173 write_reg(struct sume_adapter *adapter, int offset, uint32_t val) in write_reg() function
456 write_reg(adapter, RIFFA_CHNL_REG(ch, in sume_intr_handler()
459 write_reg(adapter, RIFFA_CHNL_REG(ch, in sume_intr_handler()
462 write_reg(adapter, RIFFA_CHNL_REG(ch, in sume_intr_handler()
702 write_reg(adapter, RIFFA_CHNL_REG(SUME_RIFFA_CHANNEL_REG, in sume_modreg_write_locked()
704 write_reg(adapter, RIFFA_CHNL_REG(SUME_RIFFA_CHANNEL_REG, in sume_modreg_write_locked()
716 write_reg(adapter, RIFFA_CHNL_REG(SUME_RIFFA_CHANNEL_REG, in sume_modreg_write_locked()
719 write_reg(adapter, RIFFA_CHNL_REG(SUME_RIFFA_CHANNEL_REG, in sume_modreg_write_locked()
722 write_reg(adapter, RIFFA_CHNL_REG(SUME_RIFFA_CHANNEL_REG, in sume_modreg_write_locked()
1067 write_reg(adapter, RIFFA_CHNL_REG(SUME_RIFFA_CHANNEL_DATA, in sume_if_start_locked()
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_phy.c257 phy->ops.write_reg = ixgbe_write_phy_reg_generic; in ixgbe_init_phy_ops_generic()
521 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, in ixgbe_reset_phy_generic()
585 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, in ixgbe_restart_auto_neg()
825 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, in ixgbe_setup_phy_link_generic()
854 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, in ixgbe_setup_phy_link_generic()
869 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, in ixgbe_setup_phy_link_generic()
1062 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, in ixgbe_setup_phy_link_tnx()
1077 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, in ixgbe_setup_phy_link_tnx()
1092 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, in ixgbe_setup_phy_link_tnx()
1162 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, in ixgbe_reset_phy_nl()
[all …]
H A Dixgbe_x550.c502 hw->phy.ops.write_reg = NULL; in ixgbe_identify_phy_fw()
2016 status = hw->phy.ops.write_reg(hw, in ixgbe_enable_lasi_ext_t_x550em()
2035 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, in ixgbe_enable_lasi_ext_t_x550em()
2053 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, in ixgbe_enable_lasi_ext_t_x550em()
2070 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, in ixgbe_enable_lasi_ext_t_x550em()
2236 hw->phy.ops.write_reg = NULL; in ixgbe_init_phy_ops_X550em()
2247 hw->phy.ops.write_reg = ixgbe_write_phy_reg_x550a; in ixgbe_init_phy_ops_X550em()
2280 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
2285 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
2296 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; in ixgbe_init_phy_ops_X550em()
[all …]
/freebsd/sys/compat/linuxkpi/common/src/
H A Dlinux_mhi.c77 CHECK_FIELD(write_reg); in linuxkpi_mhi_register_controller()
/freebsd/sys/compat/linuxkpi/common/include/linux/
H A Dmhi.h97 void (*write_reg)(struct mhi_controller *, void __iomem *, uint32_t); member
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dmmio.c236 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, in mt7996_dual_hif_set_irq_mask() argument
247 if (write_reg) { in mt7996_dual_hif_set_irq_mask()
/freebsd/sys/dev/flash/
H A Dqspi_if.m61 METHOD int write_reg {
/freebsd/sys/contrib/dev/athk/ath11k/
H A Dmhi.c437 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; in ath11k_mhi_register()
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dmmio.c864 bool write_reg, in mt7915_dual_hif_set_irq_mask() argument
875 if (write_reg) { in mt7915_dual_hif_set_irq_mask()
/freebsd/sys/contrib/dev/athk/ath12k/
H A Dmhi.c389 mhi_ctrl->write_reg = ath12k_mhi_op_write_reg; in ath12k_mhi_register()

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