Searched refs:virtRegIndex (Results 1 – 20 of 20) sorted by relevance
124 auto I = VReg.virtRegIndex(); in stackifyVReg()130 auto I = VReg.virtRegIndex(); in unstackifyVReg()135 auto I = VReg.virtRegIndex(); in isVRegStackified()144 auto I = VReg.virtRegIndex(); in setWAReg()149 auto I = VReg.virtRegIndex(); in getWAReg()
96 << Register(VReg).virtRegIndex() << ")\n"; in runOnMachineFunction()
68 << Register(Reg).virtRegIndex() << '\n'; in checkFrameBase()369 if (UseEmpty[OldReg.virtRegIndex()]) { in runOnMachineFunction()
121 unsigned MORegIdx = MOReg.virtRegIndex(); in addUsedLanesOnOperand()150 DefinedByCopy[MI.getOperand(0).getReg().virtRegIndex()]); in transferUsedLanes()207 unsigned DefRegIdx = DefReg.virtRegIndex(); in transferDefinedLanesStep()279 unsigned RegIdx = Register(Reg).virtRegIndex(); in determineInitialDefinedLanes()443 unsigned DefRegIdx = DefReg.virtRegIndex(); in isUndefInput()516 unsigned RegIdx = Reg.virtRegIndex(); in modifySubRegisterOperandStatus()
211 unsigned getSparseSetIndex() const { return VirtReg.virtRegIndex(); } in getSparseSetIndex()351 return LiveVirtRegs.find(VirtReg.virtRegIndex()); in findLiveVirtReg()355 return LiveVirtRegs.find(VirtReg.virtRegIndex()); in findLiveVirtReg()510 if (MayLiveAcrossBlocks.test(VirtReg.virtRegIndex())) { in mayLiveOut()523 MayLiveAcrossBlocks.set(VirtReg.virtRegIndex()); in mayLiveOut()531 MayLiveAcrossBlocks.set(VirtReg.virtRegIndex()); in mayLiveOut()542 MayLiveAcrossBlocks.set(VirtReg.virtRegIndex()); in mayLiveOut()552 MayLiveAcrossBlocks.set(VirtReg.virtRegIndex()); in mayLiveOut()563 if (MayLiveAcrossBlocks.test(VirtReg.virtRegIndex())) in mayLiveIn()571 MayLiveAcrossBlocks.set(VirtReg.virtRegIndex()); in mayLiveIn()
415 if (!Reg.isVirtual() || Reg.virtRegIndex() >= InitialNumVirtRegs) in scavengeFrameVirtualRegsInBlock()434 if (!Reg.isVirtual() || Reg.virtRegIndex() >= InitialNumVirtRegs) in scavengeFrameVirtualRegsInBlock()
152 DeadLaneDetector::VRegInfo Info = DLD.getVRegInfo(Reg.virtRegIndex()); in handleSubReg()
119 OS << '%' << Reg.virtRegIndex(); in printReg()164 OS << '%' << Register(Unit).virtRegIndex(); in printVRegOrUnit()
3178 unsigned Index = Reg.virtRegIndex(); in filterAndAdd()3201 unsigned Index = Reg.virtRegIndex(); in filterAndAdd()
513 return ~Reg.virtRegIndex(); in getPriority()
139 if (MayLiveAcrossBlocks.test(VirtReg.virtRegIndex())) in mayLiveOut()144 MayLiveAcrossBlocks.set(VirtReg.virtRegIndex()); in mayLiveOut()153 MayLiveAcrossBlocks.set(VirtReg.virtRegIndex()); in mayLiveOut()358 MayLiveAcrossBlocks.set(InTileReg.virtRegIndex()); in convertPHI()
82 unsigned virtRegIndex() const { in virtRegIndex() function
63 return VirtReg.virtRegIndex(); in getSparseSetIndex()
284 return Reg.virtRegIndex() + NumRegUnits; in getSparseIndexFromReg()
1400 unsigned operator()(Register Reg) const { return Reg.virtRegIndex(); } in operator()
171 return Register(v).virtRegIndex(); in v2x()275 unsigned RInd = Register(VR).virtRegIndex(); in lookup()1577 unsigned Idx = Register(I->first).virtRegIndex(); in runOnMachineFunction()
82 OS << 'v' << Register(PV.R).virtRegIndex(); in operator <<()
261 unsigned u = T.virtRegIndex(); in partitionRegisters()
157 return Register(v).virtRegIndex(); in v2x()
3178 << Base.virtRegIndex() << "\n"); in DistributeIncrements()3209 << "indexed VirtualReg " << Base.virtRegIndex() << "\n"); in DistributeIncrements()