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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td405 [(set v8i16:$VD, (int_ppc_altivec_mfvscr))]>;
417 [(set v8i16:$RST, (int_ppc_altivec_lvehx ForceXForm:$addr))]>;
444 [(int_ppc_altivec_stvehx v8i16:$RST, ForceXForm:$addr)]>;
470 def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>;
472 v8i16>;
474 def VMLADDUHM : VA1a_Int_Ty<34, "vmladduhm", int_ppc_altivec_vmladduhm, v8i16>;
498 [(set v8i16:$VD, (add v8i16:$VA, v8i16:$VB))]>;
505 def VADDSHS : VX1_Int_Ty<832, "vaddshs", int_ppc_altivec_vaddshs, v8i16>;
508 def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
564 def VAVGSH : VX1_Int_Ty<1346, "vavgsh", int_ppc_altivec_vavgsh, v8i16>;
[all …]
H A DPPCInstrVSX.td2264 dag LE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 0)), i16));
2265 dag LE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 2)), i16));
2266 dag LE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 4)), i16));
2267 dag LE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 6)), i16));
2268 dag BE_A0 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 1)), i16));
2269 dag BE_A1 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 3)), i16));
2270 dag BE_A2 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 5)), i16));
2271 dag BE_A3 = (i32 (sext_inreg (i32 (vector_extract v8i16:$A, 7)), i16));
2276 (i64 (anyext (i32 (vector_extract v8i16:$A, 0)))), i16));
2278 (i64 (anyext (i32 (vector_extract v8i16:$A, 4)))), i16));
[all …]
H A DREADME_P9.txt15 (set v2i64:$vD, (int_ppc_altivec_vextractuh v8i16:$vA, imm:$UIMM))
24 (set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
29 (set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
34 (set v8i16:$vD, (int_ppc_altivec_vinsertd v8i16:$vA, imm:$UIMM))
47 (set v8i16:$vD, (cttz v8i16:$vB)) // vctzh
476 (set v8i16:$XT, (int_ppc_vsx_xxbrh v8i16:$XB))
550 . (set v8i16:$XT, (int_ppc_vsx_lxvh8x xoaddr:$src))
560 . (store v8i16:$XT, xoaddr:$dst)
H A DPPCInstrP10.td1453 [(set v8i16:$VT,
1454 (int_ppc_altivec_vstrihr v8i16:$VB))]>;
1457 [(set v8i16:$VT,
1458 (int_ppc_altivec_vstrihl v8i16:$VB))]>;
1483 [(set v8i16:$VD,
1484 (int_ppc_altivec_vinshvlx v8i16:$VDi, i32:$VA,
1485 v8i16:$VB))]>;
1488 [(set v8i16:$VD,
1489 (int_ppc_altivec_vinshvrx v8i16:$VDi, i32:$VA,
1490 v8i16:$VB))]>;
[all …]
H A DPPCCallingConv.td64 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
100 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
147 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],
150 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],
190 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
249 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>,
266 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrInfo.td184 (v8i16 (build_vector node:$e0, node:$e0,
1203 def PseudoVBNZ_H : VecCond<loongarch_vall_nonzero, v8i16>;
1209 def PseudoVBZ_H : VecCond<loongarch_vall_zero, v8i16>;
1219 def : Pat<(v8i16 (OpNode (v8i16 LSX128:$vj))),
1237 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),
1255 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),
1266 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_simm5 simm5:$imm))),
1277 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm5 uimm5:$imm))),
1288 def : Pat<(OpNode (v8i16 LSX128:$vd), (v8i16 LSX128:$vj), (v8i16 LSX128:$vk)),
1300 def : Pat<(OpNode (v8i16 LSX128:$vj), (and vsplati16_imm_eq_15,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp461 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw in getArithmeticInstrCost()
462 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
463 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // psraw in getArithmeticInstrCost()
502 { ISD::SHL, MVT::v8i16, { 1, 2, 1, 1 } }, // psllw. in getArithmeticInstrCost()
503 { ISD::SRL, MVT::v8i16, { 1, 2, 1, 1 } }, // psrlw. in getArithmeticInstrCost()
504 { ISD::SRA, MVT::v8i16, { 1, 2, 1, 1 } }, // psraw. in getArithmeticInstrCost()
542 { ISD::SHL, MVT::v8i16, { 1, 1, 1, 1 } }, // psllw. in getArithmeticInstrCost()
543 { ISD::SRL, MVT::v8i16, { 1, 1, 1, 1 } }, // psrlw. in getArithmeticInstrCost()
544 { ISD::SRA, MVT::v8i16, { 1, 1, 1, 1 } }, // psraw. in getArithmeticInstrCost()
670 { ISD::SDIV, MVT::v8i16, { 6 } }, // pmulhw sequence in getArithmeticInstrCost()
[all …]
H A DX86InstrXOP.td129 defm VPROTW : xop3op<0x91, "vprotw", rotl, v8i16, SchedWriteVarVecShift.XMM>;
133 defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16, SchedWriteVarVecShift.XMM>;
137 defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16, SchedWriteVarVecShift.XMM>;
163 defm VPROTW : xop3opimm<0xC1, "vprotw", X86vrotli, v8i16,
217 def : Pat<(v8i16 (add (mul (v8i16 VR128:$src1), (v8i16 VR128:$src2)),
218 (v8i16 VR128:$src3))),
230 def : Pat<(v4i32 (add (X86vpmaddwd (v8i16 VR128:$src1), (v8i16 VR12
[all...]
H A DX86CallingConv.td148 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
180 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
225 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
266 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
274 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64],
586 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
592 CCIfType<[f16, f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64],
620 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCAssignToStack<16, 16>>,
658 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>,
721 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
[all …]
H A DX86InstrSSE.td142 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
633 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
641 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2497 def : Pat<(v8i16 (and VR128:$src1, VR128:$src2)),
2504 def : Pat<(v8i16 (or VR128:$src1, VR128:$src2)),
2511 def : Pat<(v8i16 (xor VR128:$src1, VR128:$src2)),
2518 def : Pat<(v8i16 (X86andnp VR128:$src1, VR128:$src2)),
2555 def : Pat<(v8i16 (and VR128:$src1, VR128:$src2)),
2562 def : Pat<(v8i16 (or VR128:$src1, VR128:$src2)),
2569 def : Pat<(v8i16 (xor VR128:$src1, VR128:$src2)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrMVE.td288 def MVE_v16i8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "i", ?>;
289 def MVE_v8i16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "i", ?>;
296 def MVE_v16s8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "s", 0b0>;
297 def MVE_v8s16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "s", 0b0>;
300 def MVE_v16u8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "u", 0b1>;
301 def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "u", 0b1>;
311 def MVE_v16p8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b11, "p", 0b0>;
312 def MVE_v8p16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b11, "p", 0b1>;
955 def : Pat<(i32 (vecreduce_smax (v8i16 MQPR:$src))),
961 def : Pat<(i32 (vecreduce_umax (v8i16 MQP
[all...]
H A DARMTargetTransformInfo.cpp545 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
546 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
550 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1}, in getCastInstrCost()
551 {ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1}, in getCastInstrCost()
580 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
581 {ISD::TRUNCATE, MVT::v8i32, MVT::v8i16, 1}, in getCastInstrCost()
611 { ISD::ADD, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
614 { ISD::SUB, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
617 { ISD::MUL, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
620 { ISD::SHL, MVT::v8i16, MVT::v8i8, 0 }, in getCastInstrCost()
[all …]
H A DARMInstrNEON.td1073 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1105 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
1408 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,
2197 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, ARMvgetlaneu>;
2247 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,ARMvgetlaneu>;
3363 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3366 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8i16 QPR:$Vm), fc)))]>;
3380 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8f16 QPR:$Vm), fc)))]>,
3431 def v8i16 : N3VQ_cmp<op24, op23, 0b01, op11_8, op4, itinQ16,
3433 v8i16, v8i16, fc, Commutable>;
[all …]
H A DARMCallingConv.td34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
169 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
187 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
214 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
237 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td645 (instregex "^ML(A|S)(v16i8|v8i16|v4i32|v2i64)(_indexed)?$")>;
719 def : InstRW<[FalkorWr_2VXVY_6cyc], (instregex "^(SQR?SHRN|UQR?SHRN|SQR?SHRUN)(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32)_shift?$")>;
722 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^ADD(v16i8|v8i16|v4i32|v2i64)$")>;
725 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIC|ORR)(v8i16|v4i32)$")>;
726 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(NEG|SUB)(v16i8|v8i16|v4i32|v2i64)$")>;
729 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v16i8|v2i64|v4i32|v8i16)(_v.*)?$")>;
730 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHLL(v16i8|v8i16|v4i32|v8i8|v4i16|v2i32)(_shift)?$")>;
731 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^(S|U)SHR(v16i8|v8i16|v4i32|v2i64)_shift$")>;
733 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS)(v16i8|v2i64|v4i32|v8i16)$")>;
734 def : InstRW<[FalkorWr_2VXVY_2cyc], (instregex "^ADDP(v4i32|v8i16|v16i
[all...]
H A DAArch64InstrInfo.td1471 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3u, v8i16>;
1480 def : EOR3_pattern<v8i16>;
1489 def : BCAX_pattern<v8i16>;
1494 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxu, v8i16>;
1499 def : SHA3_pattern<EOR3, int_aarch64_crypto_eor3s, v8i16>;
1504 def : SHA3_pattern<BCAX, int_aarch64_crypto_bcaxs, v8i16>;
3331 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
3390 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
3497 def : Pat <(v8i16 (scalar_to_vector (i32
3499 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
[all …]
H A DAArch64SchedKryoDetails.td26 (instregex "(S|U)R?SRA(v2i64|v4i32|v8i16|v16i8)_shift")>;
39 (instregex "(S|U)ABA(v16i8|v8i16|v4i32)")>;
51 (instregex "(S|U)(ABD|QSUB|RHADD)(v16i8|v8i16|v4i32|v2i64)")>;
75 (instregex "(S|U)ADALP(v16i8|v8i16|v4i32)_v.*")>;
93 (instregex "((S|U)ADDLP|ABS)(v2i64|v4i32|v8i16|v16i8)(_v.*)?")>;
165 (instregex "(S|U)H(ADD|SUB)(v16i8|v8i16|v4i32)")>;
207 (instregex "^(S|U)QADD(v16i8|v8i16|v4i32|v2i64)")>;
225 (instregex "(S|U)(QSHLU?|RSHR)(v16i8|v8i16|v4i32|v2i64)_shift$")>;
237 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v16i8|v8i16|v4i32|v2i64)$")>;
243 (instregex "((S|U)QR?SHRN|SQR?SHRUN)(v16i8|v8i16|v4i32)_shift$")>;
[all …]
H A DAArch64InstrFormats.td159 BinOpFrag<(extract_subvector (v8i16 (AArch64duplane16 (v8i16 node:$LHS), node:$RHS)), (i64 4))>;
165 … [(v4i16 (extract_subvector (v8i16 (AArch64duplane16 (v8i16 node:$LHS), node:$RHS)), (i64 0))),
166 (v4i16 (AArch64duplane16 (v8i16 node:$LHS), node:$RHS))]>;
5844 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
5845 (v8i16 V128:$RHS))),
5870 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
5872 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5894 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
5895 (!cast<Instruction>(inst#"v8i16") V128:$LHS, V128:$RHS)>;
5914 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
[all …]
H A DAArch64SchedA57.td351 // Q form - v16i8, v8i16, v4i32
353 // Q form - v16i8, v8i16, v4i32, v2i64
364 def : InstRW<[A57Write_5cyc_2X_NonMul_Forward, A57ReadIVA3], (instregex "^[SU]ABA(v16i8|v8i16|v4i32)$")>;
371 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
378 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU](MIN|MAX)V(v8i8|v8i16)v$")>;
390 def : InstRW<[A57Write_6cyc_2W_Mul_Forward], (instregex "^MUL(v16i8|v8i16|v4i32)(_indexed)?$")>;
392 def : InstRW<[A57Write_6cyc_2W], (instregex "^(PMUL|SQR?DMULH)(v16i8|v8i16|v4i32)(_indexed)?$")>;
401 def : InstRW<[A57Write_6cyc_2W_Mul_Forward, A57ReadIVMA4], (instregex "^ML[AS](v16i8|v8i16|v4i32)(_indexed)?$")>;
425 def : InstRW<[A57Write_4cyc_2X], (instregex "^[SU]SHL(v16i8|v8i16|v4i32|v2i64)")>;
431 def : InstRW<[A57Write_5cyc_2X], (instregex "^[SU][QR]{1,2}SHL(v16i8|v8i16|v4i3
[all...]
H A DAArch64CallingConvention.td39 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
107 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
115 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
141 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
153 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
187 CCIfType<[f128, v2f64, v2i64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
248 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>,
328 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64],
396 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
412 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td60 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
80 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
125 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
132 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
137 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
199 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
235 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
258 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
261 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
282 CCIfType<[v16i8, v8i16, v4i3
[all...]
H A DSystemZInstrVector.td50 def : VectorExtractSubreg<v8i16, VLGVH>;
202 defm : ReplicatePeephole<VLREPH, v8i16, z_anyextloadi16, i32>;
417 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>;
463 defm : GenericVectorOps<v8i16, v8i16>;
893 defm : BitwiseVectorOps<v8i16, z_vnot>;
930 defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>;
955 defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>;
961 defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>;
1696 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
1704 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp31 .Case("v8i16", MVT::v8i16) in parseMVT()
51 case MVT::v8i16: in toValType()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td94 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
103 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
163 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
167 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
171 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
175 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
179 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
193 (v8i16 (build_vector node:$e0, node:$e0,
265 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
269 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp67 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
93 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
162 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
199 for (auto T : {MVT::v16i8, MVT::v8i16}) in WebAssemblyTargetLowering()
203 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
207 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
212 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
217 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
223 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64}) in WebAssemblyTargetLowering()
228 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, in WebAssemblyTargetLowering()
[all …]

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