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Searched refs:v4f32 (Results 1 – 25 of 96) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td55 SDTCisVT<0, v4f32>, SDTCisPtrTy<1>
59 SDTCisVT<0, v2f64>, SDTCisVT<1, v4f32>, SDTCisPtrTy<2>
370 [(set v4f32:$XT, (any_fadd v4f32:$XA, v4f32:$XB))]>;
380 [(set v4f32:$XT, (any_fmul v4f32:$XA, v4f32:$XB))]>;
396 [(set v4f32:$XT, (any_fsub v4f32:$XA, v4f32:$XB))]>;
484 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
516 [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
548 [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
580 … [(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
632 [(set i32:$CR, (PPCftsqrt v4f32:$XB))]>;
[all …]
H A DPPCInstrAltivec.td316 [(set v4f32:$VD, (IntID v4f32:$VB))]>;
461 [(set v4f32:$RT,
462 (fma v4f32:$RA, v4f32:$RC, v4f32:$RB))]>;
467 [(set v4f32:$RT, (fneg (fma v4f32:$RA, v4f32:$RC,
468 (fneg v4f32:$RB))))]>;
491 [(set v4f32:$VD, (fadd v4f32:$VA, v4f32:$VB))]>;
523 [(set v4f32:$VD,
527 [(set v4f32:$VD,
532 (int_ppc_altivec_vctsxs v4f32:$VB, timm:$VA))]>;
536 (int_ppc_altivec_vctuxs v4f32:$VB, timm:$VA))]>;
[all …]
H A DREADME_P9.txt414 - Not useful for extraction of f32 from v4f32 (the current pattern is better -
431 (set v4f32:$XT, (int_ppc_vsx_xviexpsp v4f32:$XA, v4f32:$XB))
436 (set v4f32:$XT, (int_ppc_vsx_xvxexpsp v4f32:$XB))
438 (set v4f32:$XT, (int_ppc_vsx_xvxsigsp v4f32:$XB))
451 (set v4f32:$XT, (int_ppc_vsx_xvtstdcsp v4f32:$XB, i7:$DCMX))
H A DPPCCallingConv.td62 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
98 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
145 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],
148 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],
188 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
247 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>,
264 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrInfo.td223 (v4f32 (build_vector node:$e0, node:$e0,
1299 def : Pat<(v4f32 (OpNode (v4f32 LSX128:$vj))),
1317 def : Pat<(OpNode (v4f32 LSX128:$vj), (v4f32 LSX128:$vk)),
1457 def : Pat<(v4i32 (setcc (v4f32 LSX128:$vj), (v4f32 LSX128:$vk), CC)),
1564 foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32,
1569 foreach vt = [v16i8, v8i16, v4i32, v2i64, v4f32,
1703 def : Pat<(fma v4f32:$vj, v4f32:$vk, v4f32:$va),
1704 (VFMADD_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;
1709 def : Pat<(fma v4f32:$vj, v4f32:$vk, (fneg v4f32:$va)),
1710 (VFMSUB_S v4f32:$vj, v4f32:$vk, v4f32:$va)>;
[all …]
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dlsxintrin.h30 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
1638 return (__m128)__builtin_lsx_vfadd_s((v4f32)_1, (v4f32)_2); in __lsx_vfadd_s()
1650 return (__m128)__builtin_lsx_vfsub_s((v4f32)_1, (v4f32)_2); in __lsx_vfsub_s()
1662 return (__m128)__builtin_lsx_vfmul_s((v4f32)_1, (v4f32)_2); in __lsx_vfmul_s()
1674 return (__m128)__builtin_lsx_vfdiv_s((v4f32)_1, (v4f32)_2); in __lsx_vfdiv_s()
1686 return (__m128i)__builtin_lsx_vfcvt_h_s((v4f32)_1, (v4f32)_2); in __lsx_vfcvt_h_s()
1698 return (__m128)__builtin_lsx_vfmin_s((v4f32)_1, (v4f32)_2); in __lsx_vfmin_s()
1710 return (__m128)__builtin_lsx_vfmina_s((v4f32)_1, (v4f32)_2); in __lsx_vfmina_s()
1722 return (__m128)__builtin_lsx_vfmax_s((v4f32)_1, (v4f32)_2); in __lsx_vfmax_s()
1734 return (__m128)__builtin_lsx_vfmaxa_s((v4f32)_1, (v4f32)_2); in __lsx_vfmaxa_s()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA.td126 loadv4f32, loadv8f32, any_fma, v4f32, v8f32,
129 loadv4f32, loadv8f32, X86any_Fmsub, v4f32, v8f32,
132 loadv4f32, loadv8f32, X86Fmaddsub, v4f32, v8f32,
135 loadv4f32, loadv8f32, X86Fmsubadd, v4f32, v8f32,
157 loadv8f32, X86any_Fnmadd, v4f32, v8f32, SchedWriteFMA>;
159 loadv8f32, X86any_Fnmsub, v4f32, v8f32, SchedWriteFMA>;
375 defm : scalar_fma_patterns<any_fma, "VFMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
376 defm : scalar_fma_patterns<X86any_Fmsub, "VFMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
377 defm : scalar_fma_patterns<X86any_Fnmadd, "VFNMADD", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
378 defm : scalar_fma_patterns<X86any_Fnmsub, "VFNMSUB", "SS", X86Movss, v4f32, f32, FR32, loadf32>;
[all …]
H A DX86TargetTransformInfo.cpp973 { ISD::FMUL, MVT::v4f32, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
977 { ISD::FDIV, MVT::v4f32, { 3, 11, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1077 { ISD::FDIV, MVT::v4f32, { 35, 36, 1, 1 } }, // divps in getArithmeticInstrCost()
1093 { ISD::FMUL, MVT::v4f32, { 2, 5, 1, 1 } }, // mulps in getArithmeticInstrCost()
1095 { ISD::FDIV, MVT::v4f32, { 39, 39, 1, 6 } }, // divps in getArithmeticInstrCost()
1159 { ISD::FADD, MVT::v4f32, { 1, 4, 1, 1 } }, // vaddps in getArithmeticInstrCost()
1166 { ISD::FSUB, MVT::v4f32, { 1, 4, 1, 1 } }, // vsubps in getArithmeticInstrCost()
1173 { ISD::FMUL, MVT::v4f32, { 1, 5, 1, 1 } }, // vmulps in getArithmeticInstrCost()
1178 { ISD::FDIV, MVT::v4f32, { 7, 13, 1, 1 } }, // vdivps in getArithmeticInstrCost()
1261 { ISD::FADD, MVT::v4f32, { 1, 5, 1, 1 } }, // BDVER2 from http://www.agner.org/ in getArithmeticInstrCost()
[all …]
H A DX86InstrVecCompiler.td22 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
23 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
32 def : Pat<(f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
33 (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X)>;
42 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
53 def : Pat<(v4f32 (scalar_to_vector FR32X:$src)),
80 defm : subvector_subreg_lowering<VR128, v4f32, VR256, v8f32, sub_xmm>;
93 defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>;
129 defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, sub_xmm>;
141 defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, sub_xmm>;
[all …]
H A DX86InstrSSE.td137 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
270 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
276 defm MOVSS : sse12_move_rm<FR32, v4f32, f32mem, loadf32, X86vzload32, "movss",
284 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
300 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
301 (VMOVSSrr (v4f32 (V_SET0)), VR128:$src)>;
308 (v4f32 (VMOVSSrr (v4f32 (V_SET0)),
309 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)))), sub_xmm)>;
319 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
320 (MOVSSrr (v4f32 (V_SET0)), VR128:$src)>;
[all …]
H A DX86InstrFragmentsSIMD.td114 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
115 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
438 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
439 SDTCisVT<1, v4f32>,
440 SDTCisVT<2, v4f32>]>>;
448 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
449 SDTCisVT<1, v4f32>,
450 SDTCisVT<2, v4f32>]>>;
452 SDTypeProfile<1, 2, [SDTCisVT<0, v4f32>,
453 SDTCisVT<1, v4f32>,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td61 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
81 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
127 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
134 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
139 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
201 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
239 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
262 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
265 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
286 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
H A DSystemZInstrVector.td136 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)),
172 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
209 defm : ReplicatePeephole<VLREPF, v4f32, z_load, f32>;
232 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
282 def : Pat<(v4f32 (z_loadeswap bdxaddr12only:$addr)),
323 def : Pat<(z_storeeswap (v4f32 VR128:$val), bdxaddr12only:$addr),
351 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>;
360 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>;
379 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16_timm:$index)),
500 defm : GenericVectorOps<v4f32, v4i32>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td39 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
45 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
113 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
121 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
132 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
141 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
153 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
189 CCIfType<[f128, v2f64, v2i64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
250 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>,
330 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64],
[all …]
H A DAArch64InstrInfo.td1675 def : Pat<(concat_vectors (v4bf16 V64:$Rd), (any_fpround (v4f32 V128:$Rn))),
1892 foreach Ty = [v4f32, v2f64] in {
1934 defm : FCMLA_PATS<v4f32, V128>;
1937 defm : FCMLA_LANE_PATS<v4f32, V128,
1938 … (v4f32 (bitconvert (v2i64 (AArch64duplane64 (v2i64 V128:$Rm), VectorIndexD:$idx))))>;
3739 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
3855 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
4052 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
4270 defm : LoadInsertPatterns<load, v4f32, v2f32, nxv4f32, f32,
4528 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
[all …]
H A DAArch64SchedA57.td439 // Q form - v4f32, v2f64
448 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
453 def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
458 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>;
465 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;
485 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
489 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
496 def : InstRW<[A57Write_5cyc_2V_FP_Forward], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
509 def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA6], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
514 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f6
[all...]
H A DAArch64ISelDAGToDAG.cpp4980 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
5007 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
5034 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
5061 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
5088 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
5115 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
5142 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
5169 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
5196 } else if (VT == MVT::v4i32 || VT == MVT::v4f32) { in Select()
5215 } else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 || in Select()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
170 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
188 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
215 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
238 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
H A DARMInstrNEON.td1092 def : Pat<(vector_insert (v4f32 QPR:$src),
1103 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
1414 def : Pat<(v4f32 (ARMvdup (f32 (load addrmode6dup:$addr)))),
2203 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
3371 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3374 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
4271 v4f32, v4f32, fadd, 1>;
4334 v4f32, v4f32, fmul, 1>;
4343 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4364 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
[all …]
H A DARMInstrMVE.td307 def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1, v4i1, 0b01, "f", ?>;
308 def MVE_v4f32 : MVEVectorVTInfo<v4f32, v2f64, v4i1, v2i1, 0b10, "f", ?>;
1862 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4i32 MQPR:$src1), MQPR)),
1863 … (f32 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4i32 MQPR:$src2), MQPR)),
1890 (COPY_TO_REGCLASS (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)),
1904 def : Pat<(extractelt (v4f32 MQPR:$src), imm:$lane),
1906 def : Pat<(insertelt (v4f32 MQPR:$src1), (f32 SPR:$src2), imm:$lane),
1907 …(INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), SPR:$src2, (SSubReg_f32_reg imm:$lane)…
1913 (COPY_TO_REGCLASS (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)),
1929 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
[all …]
H A DARMTargetTransformInfo.cpp586 {ISD::FP_EXTEND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
614 {ISD::FP_ROUND, MVT::v4f32, MVT::v4f16, 1}, in getCastInstrCost()
662 {ISD::FP_EXTEND, MVT::v4f32, 4}}; in getCastInstrCost()
705 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
706 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
714 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
715 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
716 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
717 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
718 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600Instructions.td408 multiclass TexPattern<bits<32> TextureOp, Instruction inst, ValueType vt = v4f32> {
499 def : R600Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
510 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
515 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
520 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
525 def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src),
1081 [(set v4f32:$dst, (int_r600_cube v4f32:$src0))],
1695 def : ExtractVerticalPat <R600_EXTRACT_ELT_V4, v4f32, f32>;
1706 def : InsertVerticalPat <R600_INSERT_ELT_V4, v4f32, f3
[all...]
H A DSIInstrInfo.td1927 !eq(SrcVT.Value, v4f32.Value),
2948 def VOP_V4F32_F32_F32_V4F32 : VOPProfile <[v4f32, f32, f32, v4f32]>;
2951 def VOP_V4F32_V4F16_V4F16_V4F32 : VOPProfile <[v4f32, v4f16, v4f16, v4f32]>;
2954 def VOP_V4F32_V2I16_V2I16_V4F32 : VOPProfile <[v4f32, v2i16, v2i16, v4f32]>;
2967 def VOP_V4F32_V4I16_V4I16_V4F32 : VOPProfile <[v4f32, v4i16, v4i16, v4f32]>;
2973 def VOP_V4F32_V2F32_V2F32_V4F32 : VOPProfile <[v4f32, v2f32, v2f32, v4f32]>;
2975 def VOP_V4F32_I64_I64_V4F32 : VOPProfile <[v4f32, i64, i64, v4f32]>;
2978 def VOP_V4F32_V4F16_V8F16_I32 : VOPProfile <[v4f32, v4f16, v8f16, i32]>;
2979 def VOP_V4F32_V8F16_V16F16_I32 : VOPProfile <[v4f32, v8f16, v16f16, i32]>;
2980 def VOP_V4F32_V8BF16_V16BF16_I32 : VOPProfile <[v4f32, v8bf16, v16bf16, i32]>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td114 def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
116 def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
118 def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
120 def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
122 def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
124 def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
126 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
128 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
130 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
132 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrSIMD.td54 defm "" : ARGUMENT<V128, v4f32>;
133 let vt = v4f32;
140 let splat = PatFrag<(ops node:$x), (v4f32 (splat_vector (f32 $x)))>;
663 def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)),
733 def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
812 def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1250 def : Pat<(v4f32 (frint (v4f32 V128:$src))), (NEAREST_F32x4 V128:$src)>;
1255 def : Pat<(v4f32 (froundeven (v4f32 V128:$src))), (NEAREST_F32x4 V128:$src)>;
1334 def : Pat<(v4f32 (int_wasm_pmin (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
1336 def : Pat<(v4f32 (int_wasm_pmax (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
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