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Searched refs:v2f64 (Results 1 – 25 of 90) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallingConv.td32 // Handle all vector types as either f64 or v2f64.
34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
37 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
44 CCIfType<[v2f64], CCAssignToStack<16, 4>>
58 // Handle all vector types as either f64 or v2f64.
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
62 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
73 // Handle all vector types as either f64 or v2f64.
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v8bf16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
[all …]
H A DARMCallingConv.cpp54 if (LocVT == MVT::v2f64 && in CC_ARM_APCS_Custom_f64()
107 if (LocVT == MVT::v2f64 && in CC_ARM_AAPCS_Custom_f64()
139 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) in RetCC_ARM_APCS_Custom_f64()
223 case MVT::v2f64: in CC_ARM_AAPCS_Custom_Aggregate()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td59 SDTCisVT<0, v2f64>, SDTCisVT<1, v4f32>, SDTCisPtrTy<2>
68 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
71 SDTCisVT<0, v2f64>, SDTCisPtrTy<1>
87 SDTCisVT<0, v2f64>, SDTCisVT<1, v2f64>,
88 SDTCisVT<2, v2f64>, SDTCisVT<3, v4i32>]>;
365 [(set v2f64:$XT, (any_fadd v2f64:$XA, v2f64:$XB))]>;
375 [(set v2f64:$XT, (any_fmul v2f64:$XA, v2f64:$XB))]>;
392 [(set v2f64:$XT, (any_fsub v2f64:$XA, v2f64:$XB))]>;
468 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
500 [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
[all …]
H A DREADME_P9.txt323 int_ppc_vsx_xvcmpeqdp, v2i64, v2f64>;
430 (set v2f64:$XT, (int_ppc_vsx_xviexpdp v2f64:$XA, v2f64:$XB))
435 (set v2f64:$XT, (int_ppc_vsx_xvxexpdp v2f64:$XB))
437 (set v2f64:$XT, (int_ppc_vsx_xvxsigdp v2f64:$XB))
452 (set v2f64:$XT, (int_ppc_vsx_xvtstdcdp v2f64:$XB, i7:$DCMX))
548 [(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>;
558 [(store v2f64:$XT, xoaddr:$dst)]>;
H A DPPCCallingConv.td62 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
98 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
145 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],
148 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v1i128],
188 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
247 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>,
264 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
H A DPPCInstrP10.td1366 // Load v2f64
1367 def : Pat<(v2f64 (load (PPCmatpcreladdr PCRelForm:$addr))), (PLXVpc $addr, 0)>;
1369 // Store v2f64
1370 def : Pat<(store v2f64:$XS, (PPCmatpcreladdr PCRelForm:$ga)),
1390 [(set v2f64:$XT,
2117 def : Pat<(store (f64 (extractelt v2f64:$src, 0)), ForceXForm:$dst),
2292 // Load / Store v2f64
2293 def : Pat<(v2f64 (load PDForm:$src)), (PLXV memri34:$src)>;
2294 def : Pat<(store v2f64:$XS, PDForm:$dst), (PSTXV $XS, memri34:$dst)>;
2385 // Prefixed fpext to v2f64
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrInfo.td226 (v2f64 (build_vector node:$e0, node:$e0))>;
1301 def : Pat<(v2f64 (OpNode (v2f64 LSX128:$vj))),
1319 def : Pat<(OpNode (v2f64 LSX128:$vj), (v2f64 LSX128:$vk)),
1459 def : Pat<(v2i64 (setcc (v2f64 LSX128:$vj), (v2f64 LSX128:$vk), CC)),
1565 v2f64] in def : Pat<(loongarch_vbsll(vt LSX128:$vj), uimm5:$imm),
1570 v2f64] in def : Pat<(loongarch_vbsrl(vt LSX128:$vj), uimm5:$imm),
1705 def : Pat<(fma v2f64:$vj, v2f64:$vk, v2f64:$va),
1706 (VFMADD_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;
1711 def : Pat<(fma v2f64:$vj, v2f64:$vk, (fneg v2f64:$va)),
1712 (VFMSUB_D v2f64:$vj, v2f64:$vk, v2f64:$va)>;
[all …]
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dlsxintrin.h32 typedef double v2f64 __attribute__((vector_size(16), aligned(16))); typedef
1644 return (__m128d)__builtin_lsx_vfadd_d((v2f64)_1, (v2f64)_2); in __lsx_vfadd_d()
1656 return (__m128d)__builtin_lsx_vfsub_d((v2f64)_1, (v2f64)_2); in __lsx_vfsub_d()
1668 return (__m128d)__builtin_lsx_vfmul_d((v2f64)_1, (v2f64)_2); in __lsx_vfmul_d()
1680 return (__m128d)__builtin_lsx_vfdiv_d((v2f64)_1, (v2f64)_2); in __lsx_vfdiv_d()
1692 return (__m128)__builtin_lsx_vfcvt_s_d((v2f64)_1, (v2f64)_2); in __lsx_vfcvt_s_d()
1704 return (__m128d)__builtin_lsx_vfmin_d((v2f64)_1, (v2f64)_2); in __lsx_vfmin_d()
1716 return (__m128d)__builtin_lsx_vfmina_d((v2f64)_1, (v2f64)_2); in __lsx_vfmina_d()
1728 return (__m128d)__builtin_lsx_vfmax_d((v2f64)_1, (v2f64)_2); in __lsx_vfmax_d()
1740 return (__m128d)__builtin_lsx_vfmaxa_d((v2f64)_1, (v2f64)_2); in __lsx_vfmaxa_d()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA.td141 loadv2f64, loadv4f64, any_fma, v2f64,
144 loadv2f64, loadv4f64, X86any_Fmsub, v2f64,
148 v2f64, v4f64, SchedWriteFMA>, REX_W;
151 v2f64, v4f64, SchedWriteFMA>, REX_W;
163 loadv4f64, X86any_Fnmadd, v2f64, v4f64, SchedWriteFMA>, REX_W;
165 loadv4f64, X86any_Fnmsub, v2f64, v4f64, SchedWriteFMA>, REX_W;
380 defm : scalar_fma_patterns<any_fma, "VFMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>;
381 defm : scalar_fma_patterns<X86any_Fmsub, "VFMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>;
382 defm : scalar_fma_patterns<X86any_Fnmadd, "VFNMADD", "SD", X86Movsd, v2f64, f64, FR64, loadf64>;
383 defm : scalar_fma_patterns<X86any_Fnmsub, "VFNMSUB", "SD", X86Movsd, v2f64, f64, FR64, loadf64>;
[all …]
H A DX86TargetTransformInfo.cpp958 { ISD::FMUL, MVT::v2f64, { 1, 4, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
962 { ISD::FDIV, MVT::v2f64, { 4, 14, 1, 1 } }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1079 { ISD::FDIV, MVT::v2f64, { 65, 66, 1, 1 } }, // divpd in getArithmeticInstrCost()
1092 { ISD::FMUL, MVT::v2f64, { 4, 7, 1, 1 } }, // mulpd in getArithmeticInstrCost()
1097 { ISD::FDIV, MVT::v2f64, { 69, 69, 1, 6 } }, // divpd in getArithmeticInstrCost()
1098 { ISD::FADD, MVT::v2f64, { 2, 4, 1, 1 } }, // addpd in getArithmeticInstrCost()
1099 { ISD::FSUB, MVT::v2f64, { 2, 4, 1, 1 } }, // subpd in getArithmeticInstrCost()
1158 { ISD::FADD, MVT::v2f64, { 1, 4, 1, 1 } }, // vaddpd in getArithmeticInstrCost()
1165 { ISD::FSUB, MVT::v2f64, { 1, 4, 1, 1 } }, // vsubpd in getArithmeticInstrCost()
1172 { ISD::FMUL, MVT::v2f64, { 1, 5, 1, 1 } }, // vmulpd in getArithmeticInstrCost()
[all …]
H A DX86InstrVecCompiler.td24 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
25 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
34 def : Pat<(f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
35 (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X)>;
45 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
56 def : Pat<(v2f64 (scalar_to_vector FR64X:$src)),
82 defm : subvector_subreg_lowering<VR128, v2f64, VR256, v4f64, sub_xmm>;
95 defm : subvector_subreg_lowering<VR128, v2f64, VR512, v8f64, sub_xmm>;
128 defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, sub_xmm>;
140 defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, sub_xmm>;
[all …]
H A DX86InstrSSE.td146 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
272 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
278 defm MOVSD : sse12_move_rm<FR64, v2f64, f64mem, loadf64, X86vzload64, "movsd",
286 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
326 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
405 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>,
413 [(store (v2f64 VR128:$src), addr:$dst)]>,
503 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
509 [(store (v2f64 VR128:$src), addr:$dst)]>;
675 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
[all …]
H A DX86InstrAVX10.td444 (v2i64 (OpNode (bc_v4f32 (v2f64
446 (v2i64 (MaskOpNode (bc_v4f32 (v2f64
517 def : Pat<(v4i32(X86fp2sisat(v2f64 VR128X:$src))),
525 def : Pat<(v2i64(fp_to_sint_sat(v2f64 VR128X:$src), i64)),
533 def : Pat<(v4i32(X86fp2uisat(v2f64 VR128X:$src))),
541 def : Pat<(v2i64(fp_to_uint_sat(v2f64 VR128X:$src), i64)),
580 def : Pat<(v4i32 (X86cvttp2sis (v2f64 VR128X:$src))),
584 def : Pat<(v4i32 (X86cvttp2sis (v2f64 (X86VBroadcastld64 addr:$src)))),
586 def : Pat<(X86mcvttp2sis (v2f64 VR128X:$src), (v4i32 VR128X:$src0),
589 def : Pat<(X86mcvttp2sis (v2f64 VR128X:$src), v4i32x_info.ImmAllZerosV,
[all …]
H A DX86CallingConv.td148 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
176 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
221 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
270 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64],
330 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
573 CCIfType<[f16, f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64],
601 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64], CCAssignToStack<16, 16>>,
639 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64], CCPassIndirect<i64>>,
700 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
743 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v8bf16, v4f32, v2f64],
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td61 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
81 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
127 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
134 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
139 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
201 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
239 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
262 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
265 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
286 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
H A DSystemZInstrVector.td138 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)),
174 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
210 defm : ReplicatePeephole<VLREPG, v2f64, z_load, f64>;
235 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
284 def : Pat<(v2f64 (z_loadeswap bdxaddr12only:$addr)),
325 def : Pat<(z_storeeswap (v2f64 VR128:$val), bdxaddr12only:$addr),
352 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>;
361 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>;
381 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16_timm:$index)),
501 defm : GenericVectorOps<v2f64, v2i64>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td39 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
45 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
95 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
113 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
121 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
132 CCIfType<[v2f64, v4f32], CCBitConvertToType<v2i64>>,
141 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
153 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16, v8bf16],
189 CCIfType<[f128, v2f64, v2i64, v4i32, v4f32, v8i16, v8f16, v8bf16, v16i8],
250 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>,
[all …]
H A DAArch64SchedA57.td439 // Q form - v4f32, v2f64
448 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FABD|FADD|FSUB)(v4f32|v2f64|v2i64p)")>;
453 def : InstRW<[A57Write_9cyc_3V], (instregex "^FADDP(v4f32|v2f64|v2i64)")>;
458 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v4f32|v2f64|v4i32|v2i64)")>;
465 def : InstRW<[A57Write_5cyc_2V], (instregex "^[FSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;
485 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
489 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
496 def : InstRW<[A57Write_5cyc_2V_FP_Forward], (instregex "^FMULX?(v4f32|v2f64|v4i32|v2i64)")>;
509 def : InstRW<[A57WriteFPVMAQ, A57ReadFPVMA6], (instregex "^FML[AS](v4f32|v2f64|v4i32|v2i64)")>;
514 def : InstRW<[A57Write_5cyc_2V], (instregex "^FRINT[AIMNPXZ](v4f32|v2f64)")>;
[all...]
H A DAArch64InstrInfo.td1892 foreach Ty = [v4f32, v2f64] in {
1935 defm : FCMLA_PATS<v2f64, V128>;
3737 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
3857 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
4048 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
4273 defm : LoadInsertPatterns<load, v2f64, isVoid, nxv2f64, f64,
4526 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
4560 defm : VecROStoreLane0Pat<ro64, store, v2f64, f64, i64, dsub, STRDroW, STRDroX>;
4643 def : Pat<(store (v2f64 FPR128:$Rt),
4696 defm : VecStoreLane0Pat<am_indexed64, store, v2f64, f64, i64, dsub, uimm12s8, STRDui>;
[all …]
H A DAArch64ISelDAGToDAG.cpp4986 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { in Select()
5013 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { in Select()
5040 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { in Select()
5067 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { in Select()
5094 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { in Select()
5121 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { in Select()
5148 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { in Select()
5175 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { in Select()
5202 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) { in Select()
5219 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
[all …]
H A DAArch64TargetTransformInfo.cpp799 LT.second == MVT::v2f64)) { in getIntrinsicInstrCost()
3093 {ISD::FP_ROUND, MVT::v2bf16, MVT::v2f64, 2}, // bfcvtn+fcvtn in getCastInstrCost()
3191 {ISD::FP_EXTEND, MVT::v2f64, MVT::v2f32, 1}, // fcvtl in getCastInstrCost()
3198 {ISD::FP_EXTEND, MVT::v2f64, MVT::v2f16, 2}, // fcvtl+fcvtl in getCastInstrCost()
3206 {ISD::FP_EXTEND, MVT::v2f64, MVT::v2bf16, 2}, // shll+fcvtl in getCastInstrCost()
3211 {ISD::FP_ROUND, MVT::v2f32, MVT::v2f64, 1}, // fcvtn in getCastInstrCost()
3218 {ISD::FP_ROUND, MVT::v2f16, MVT::v2f64, 2}, // fcvtn+fcvtn in getCastInstrCost()
3227 {ISD::FP_ROUND, MVT::v2bf16, MVT::v2f64, 9}, in getCastInstrCost()
3234 {ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1}, in getCastInstrCost()
3237 {ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1}, in getCastInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.td40 def vfID : RegisterClass<"SPIRV", [v2f64], 64, (add vfID0)>;
45 [i64, f64, p64, v2i64, v2f64, v2p64],
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td115 def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>;
117 def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>;
119 def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>;
121 def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>;
123 def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
125 def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>;
127 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
129 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
131 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
133 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrSIMD.td55 defm "" : ARGUMENT<V128, v2f64>;
145 let vt = v2f64;
152 let splat = PatFrag<(ops node:$x), (v2f64 (splat_vector (f64 $x)))>;
667 def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)),
735 def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
817 def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1251 def : Pat<(v2f64 (frint (v2f64 V128:$src))), (NEAREST_F64x2 V128:$src)>;
1256 def : Pat<(v2f64 (froundeven (v2f64 V128:$src))), (NEAREST_F64x2 V128:$src)>;
1338 def : Pat<(v2f64 (int_wasm_pmin (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
1340 def : Pat<(v2f64 (int_wasm_pmax (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp56 case MVT::v2f64: in toValType()

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