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Searched refs:v27 (Results 1 – 25 of 25) sorted by relevance

/freebsd/sys/crypto/openssl/aarch64/
H A Dchacha-armv8.S371 dup v27.4s,v3.s[2]
401 eor v27.16b,v27.16b,v24.16b
409 rev32 v27.8h,v27.8h
417 add v26.4s,v26.4s,v27.4s
457 eor v6.16b,v27.16b,v24.16b
465 tbl v27.16b,{v6.16b},v9.16b
473 add v26.4s,v26.4s,v27.4s
507 eor v27.16b,v27.16b,v28.16b
515 rev32 v27.8h,v27.8h
523 add v22.4s,v22.4s,v27.4s
[all …]
H A Daesv8-armx.S540 ld1 {v27.16b},[x0],#16
552 orr v24.16b,v27.16b,v27.16b
571 orr v0.16b,v27.16b,v27.16b
647 ld1 {v27.16b},[x0],#16
662 orr v24.16b,v27.16b,v27.16b
853 ld1 {v27.16b},[x0],#16
865 orr v24.16b,v27.16b,v27.16b
884 orr v0.16b,v27.16b,v27.16b
960 ld1 {v27.16b},[x0],#16
975 orr v24.16b,v27.16b,v27.16b
[all …]
H A Daes-gcm-armv8_64.S143 ld1 {v27.4s}, [x8], #16 //load rk9
214 aese v2.16b, v27.16b //AES block 2 - round 9
216 aese v0.16b, v27.16b //AES block 0 - round 9
220 aese v1.16b, v27.16b //AES block 1 - round 9
222 aese v3.16b, v27.16b //AES block 3 - round 9
503 aese v0.16b, v27.16b //AES block 4k+4 - round 9
511 aese v1.16b, v27.16b //AES block 4k+5 - round 9
538 aese v2.16b, v27.16b //AES block 4k+6 - round 9
543 aese v3.16b, v27.16b //AES block 4k+7 - round 9
740 aese v3.16b, v27.16b //AES block 4k+7 - round 9
[all …]
H A Dpoly1305-armv8.S591 add v12.2s,v12.2s,v27.2s
636 xtn v27.2s,v22.2d
640 bic v27.2s,#0xfc,lsl#24 // &=0x03ffffff
656 add v27.2s,v27.2s,v30.2s // h2 -> h3
661 ushr v30.2s,v27.2s,#26
662 bic v27.2s,#0xfc,lsl#24
681 add v17.2s,v12.2s,v27.2s
739 add v12.2s,v12.2s,v27.2s
H A Dvpaes-armv8.S109 ld1 {v24.2d,v25.2d,v26.2d,v27.2d}, [x10] // .Lk_sb1, .Lk_sb2
153 tbl v5.16b, {v27.16b}, v2.16b // vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
249 tbl v5.16b, {v27.16b}, v2.16b // vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
250 tbl v13.16b, {v27.16b}, v10.16b
328 ld1 {v24.2d,v25.2d,v26.2d,v27.2d}, [x11],#64 // .Lk_dsb9, .Lk_dsbd
379 tbl v1.16b, {v27.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sbdt
502 tbl v1.16b, {v27.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sbdt
503 tbl v9.16b, {v27.16b}, v11.16b
598 ld1 {v24.2d,v25.2d,v26.2d,v27.2d}, [x10],#64 // .Lk_dksd, .Lk_dksb
952 tbl v3.16b, {v27.16b}, v1.16b // vpshufb %xmm1, %xmm3, %xmm3
H A Dghashv8-armx.S280 ld1 {v26.2d,v27.2d,v28.2d},[x1] //load twisted H^3, ..., H^4
312 pmull v5.1q,v27.1d,v5.1d
339 pmull2 v1.1q,v27.2d,v16.2d
375 pmull v5.1q,v27.1d,v5.1d
393 pmull2 v1.1q,v27.2d,v16.2d
449 pmull v1.1q,v27.1d,v16.1d
H A Dsha512-armv8.S1121 orr v27.16b,v1.16b,v1.16b
1598 add v1.2d,v1.2d,v27.2d
/freebsd/sys/contrib/openzfs/module/icp/asm-aarch64/blake3/
H A Db3_aarch64_sse41.S819 zip2 v3.4s, v27.4s, v9.4s
820 zip1 v7.4s, v27.4s, v9.4s
866 tbl v6.16b, { v6.16b }, v27.16b
867 tbl v7.16b, { v7.16b }, v27.16b
868 tbl v16.16b, { v16.16b }, v27.16b
869 tbl v0.16b, { v0.16b }, v27.16b
951 tbl v4.16b, { v4.16b }, v27.16b
952 tbl v25.16b, { v25.16b }, v27.16b
957 tbl v6.16b, { v6.16b }, v27.16b
958 tbl v16.16b, { v16.16b }, v27
[all...]
H A Db3_aarch64_sse2.S791 zip1 v11.4s, v27.4s, v9.4s
792 zip2 v9.4s, v27.4s, v9.4s
793 zip2 v27.2d, v21.2d, v4.2d
818 add v0.4s, v0.4s, v27.4s
823 mov v27.16b, v16.16b
993 add v17.4s, v17.4s, v27.4s
1162 add v19.4s, v19.4s, v27.4s
1270 mov v12.16b, v27.16b
1271 mov v27.16b, v9.16b
1416 add v17.4s, v17.4s, v27
[all...]
/freebsd/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_ppc_regs.h92 #define v27 27 macro
H A Dtsan_rtl_ppc64.S119 stvx v27,0,r6
264 stvx v27,0,r6
/freebsd/contrib/llvm-project/lldb/source/Utility/
H A DARM64_DWARF_Registers.h108 v27, enumerator
H A DARM64_ehframe_Registers.h107 v27, enumerator
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterContextFreeBSD_powerpc.cpp161 uint32_t v27[4]; member
H A DRegisterInfos_arm64.h643 DEFINE_VREG(v27),
677 DEFINE_FPU_PSEUDO(s27, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v27),
710 DEFINE_FPU_PSEUDO(d27, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v27),
H A DRegisterInfos_powerpc.h157 DEFINE_VMX(v27, LLDB_INVALID_REGNUM), \
H A DRegisterInfos_riscv64.h179 DEFINE_VPR(v27, LLDB_INVALID_REGNUM),
H A DRegisterContextDarwin_arm64.cpp828 case arm64_dwarf::v27: in ConvertRegisterKindToRegisterNumber()
H A DRegisterInfos_arm64_sve.h438 DEFINE_VREG_SVE(v27, z27),
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td245 def W13 : Rd<26, "v27:26", [V26, V27, VF13]>, DwarfRegNum<[125]>;
278 def VQ6 : Rd<24, "v27:24", [W12, W13]>, DwarfRegNum<[258]>;
H A DHexagonPatternsHVX.td939 // v27.b = vadd(Inp.b,v29.b) ; x + masks
940 // Abs = vxor(v27,v29) ; ^ masks
/freebsd/sys/contrib/openzfs/module/icp/asm-aarch64/sha2/
H A Dsha512-armv8.S1082 orr v27.16b,v1.16b,v1.16b
1559 add v1.2d,v1.2d,v27.2d
/freebsd/sys/contrib/openzfs/module/icp/asm-ppc64/blake3/
H A Db3_ppc64le_sse2.S1616 .cfi_offset v27, -240
H A Db3_ppc64le_sse41.S1716 .cfi_offset v27, -256
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td410 def D27 : AArch64Reg<27, "d27", [S27], ["v27", ""]>, DwarfRegAlias<B27>;
445 def Q27 : AArch64Reg<27, "q27", [D27], ["v27", ""]>, DwarfRegAlias<B27>;