Home
last modified time | relevance | path

Searched refs:uimm4 (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrFormats.td52 : LAInst<(outs), (ins GPR:$rj, uimm4:$imm4),
65 : LAInst<(outs GPR:$rd), (ins uimm4:$imm4),
91 : LAInst<(outs), (ins GPR:$rj, uimm5:$imm5, uimm4:$imm4),
160 : LAInst<(outs), (ins GPR:$rj, GPR:$rk, uimm4:$imm4),
190 : LAInst<(outs GPR:$rd), (ins GPR:$rj, uimm4:$imm4),
H A DLoongArchLSXInstrInfo.td244 class LSX2RI4_VVI<bits<32> op, Operand ImmOpnd = uimm4>
248 class LSX2RI4_RVI<bits<32> op, Operand ImmOpnd = uimm4>
280 Operand IdxOpnd = uimm4>
309 class LSX2RI4_VVRI<bits<32> op, Operand ImmOpnd = uimm4>
313 class LSX2RI4_VVVI<bits<32> op, Operand ImmOpnd = uimm4>
1314 def : Pat<(OpNode (v8i16 LSX128:$vj), (v8i16 (SplatPat_uimm4 uimm4:$imm))),
1315 (!cast<LAInst>(Inst#"_H") LSX128:$vj, uimm4:$imm)>;
1505 def : Pat<(and (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_inv_pow2 uimm4:$imm))),
1506 (VBITCLRI_H LSX128:$vj, uimm4:$imm)>;
1533 def : Pat<(or (v8i16 LSX128:$vj), (v8i16 (vsplat_uimm_pow2 uimm4:$imm))),
[all …]
H A DLoongArchLASXInstrInfo.td82 class LASX2RI4_XXI<bits<32> op, Operand ImmOpnd = uimm4>
86 class LASX2RI4_XRI<bits<32> op, Operand ImmOpnd = uimm4>
90 class LASX2RI4_RXI<bits<32> op, Operand ImmOpnd = uimm4>
117 Operand IdxOpnd = uimm4>
156 class LASX2RI4_XXXI<bits<32> op, Operand ImmOpnd = uimm4>
1085 : Pseudo<(outs LASX256:$dst), (ins LASX256:$xd, GPR:$rj, uimm4:$imm)>;
1192 def : Pat<(OpNode (v16i16 LASX256:$xj), (v16i16 (SplatPat_uimm4 uimm4:$imm))),
1193 (!cast<LAInst>(Inst#"_H") LASX256:$xj, uimm4:$imm)>;
1383 def : Pat<(and (v16i16 LASX256:$xj), (v16i16 (vsplat_uimm_inv_pow2 uimm4:$imm))),
1384 (XVBITCLRI_H LASX256:$xj, uimm4:$imm)>;
[all …]
H A DLoongArchInstrInfo.td246 def uimm4 : Operand<GRLenVT>, ImmLeaf<GRLenVT, [{return isUInt<4>(Imm);}]> {
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaOperands.td54 // uimm4 predicate - Immediate in the range [0,15]
56 def uimm4 : Immediate<i32, [{ return Imm >= 0 && Imm <= 15; }], "Uimm4_AsmOperand"> {
H A DXtensaInstrInfo.td159 def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa),
161 [(set AR:$r, (srl AR:$t, uimm4:$sa))]> {
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsDSPInstrInfo.td226 "shll.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>,
229 "shll_s.ph", int_mips_shll_s_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>,
242 "shra.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>;
244 "shra_r.ph", int_mips_shra_r_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>;
250 "shrl.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>;
H A DMicroMipsInstrInfo.td474 MicroMipsInst16<(outs), (ins uimm4:$code_),
1028 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>,
1030 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>,
1032 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>,
1034 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>,
1036 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>,
1038 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>,
H A DMipsDSPInstrInfo.td695 NoItinerary, DSPROpnd, uimm4>,
704 uimm4>,
712 NoItinerary, DSPROpnd, uimm4>;
719 uimm4>;
1091 NoItinerary, DSPROpnd, uimm4>;
H A DMipsMSAInstrInfo.td2241 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4,
2285 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, timmZExt4,
2515 class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4,
2524 class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4,
2541 MSA128BOpnd, MSA128BOpnd, uimm4,
2606 class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4,
2634 class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4,
H A DMipsInstrInfo.td641 // uimm4 < uimm5 < uimm6
644 // simm4 < uimm4 < simm5 < uimm5
647 // uimm3 < simm4 < uimm4 < simm4
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp393 int uimm4 = Imm & 0xf; in isExtImm6() local
395 return isShiftedUInt<6, 0>(Imm) && uimm4 >= 0 && uimm4 <= 14; in isExtImm6()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td764 uimm4:$funct4,
818 (InsnCR AnyReg:$rd, uimm2_opcode:$opcode, uimm4:$funct4,
H A DRISCVInstrInfoXCV.td369 def CV_ # NAME # _SCI_H : CVSIMDRU<funct5, F, 0b110, "cv." # mnemonic # ".sci.h", uimm4>;
H A DRISCVInstrInfo.td228 def uimm4 : RISCVUImmOp<4>;
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td328 def uimm4 : uimm<4>;
1021 def SCE32 : I_5_IMM5<0x30, 0b000110, 0b00001, "sce32", uimm4, []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.td160 // uimm4 - Generic immediate value.
164 def uimm4 : Operand<i32>, PatLeaf<(imm), [{
H A DVEInstrVec.td735 Operand SIMM = uimm4> {