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Searched refs:timm (Results 1 – 25 of 92) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrConditionalCompare.td81 def : Pat<(X86ccmp GR8:$src1, GR8:$src2, timm:$dcf, timm:$cond, EFLAGS),
82 (CCMP8rr GR8:$src1, GR8:$src2, timm:$dcf, timm:$cond)>;
83 def : Pat<(X86ccmp GR16:$src1, GR16:$src2, timm:$dcf, timm:$cond, EFLAGS),
84 (CCMP16rr GR16:$src1, GR16:$src2, timm:$dcf, timm:$cond)>;
85 def : Pat<(X86ccmp GR32:$src1, GR32:$src2, timm:$dcf, timm:$cond, EFLAGS),
86 (CCMP32rr GR32:$src1, GR32:$src2, timm:$dcf, timm:$cond)>;
87 def : Pat<(X86ccmp GR64:$src1, GR64:$src2, timm:$dcf, timm:$cond, EFLAGS),
88 (CCMP64rr GR64:$src1, GR64:$src2, timm:$dcf, timm:$cond)>;
90 def : Pat<(X86ccmp GR8:$src1, (i8 imm:$src2), timm:$dcf, timm:$cond, EFLAGS),
91 (CCMP8ri GR8:$src1, imm:$src2, timm:$dcf, timm:$cond)>;
[all …]
H A DX86InstrCMovSetCC.td22 … t.RegClass:$src2, timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
28 … (t.LoadNode addr:$src2), timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
38 (X86cmov 0, t.RegClass:$src1, timm:$cond, EFLAGS))]>, UseEFLAGS, NF;
93 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
94 (CMOV16rm GR16:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
95 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
96 (CMOV32rm GR32:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
97 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, timm:$cond, EFLAGS),
98 (CMOV64rm GR64:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
102 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
[all …]
H A DX86InstrAMX.td93 [(int_x86_tilezero timm:$src)]>;
152 [(int_x86_tdpbssd timm:$src1,
153 timm:$src2, timm:$src3)]>;
156 [(int_x86_tdpbsud timm:$src1,
157 timm:$src2, timm:$src3)]>;
160 [(int_x86_tdpbusd timm:$src1,
161 timm:$src2, timm:$src3)]>;
164 [(int_x86_tdpbuud timm:$src1,
165 timm:$src2, timm:$src3)]>;
193 [(int_x86_tdpbf16ps timm:$src1,
[all …]
H A DX86InstrCompiler.td45 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
48 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
63 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
66 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
89 (X86vaarg64 addr:$ap, timm:$size, timm:$mode, timm:$align))]>,
96 (X86vaargx32 addr:$ap, timm:$size, timm:$mode, timm:$align))]>,
291 [(int_asan_check_memaccess GR64PLTSafe:$addr, (i32 timm:$accessinfo))]>,
571 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, timm:$cond,
629 def : Pat<(f128 (X86cmov VR128:$t, VR128:$f, timm:$cond, EFLAGS)),
630 (CMOV_VR128 VR128:$t, VR128:$f, timm:$cond)>;
[all …]
H A DX86InstrSSE.td1849 VR128:$src2, timm:$cc))]>,
1855 (mem_frags addr:$src2), timm:$cc))]>,
1862 [(set RC:$dst, (OpNode RC:$src1, RC:$src2, timm:$cc))]>,
1867 (ld_frag addr:$src2), timm:$cc))]>,
1984 [(set RC:$dst, (VT (X86any_cmpp RC:$src1, RC:$src2, timm:$cc)))], d>,
1989 (VT (X86any_cmpp RC:$src1, (ld_frag addr:$src2), timm:$cc)))], d>,
2014 def CommutableCMPCC : PatLeaf<(timm), [{
2023 (VCMPPDYrmi VR256:$src1, addr:$src2, timm:$cc)>;
2027 (VCMPPSYrmi VR256:$src1, addr:$src2, timm:$cc)>;
2031 (VCMPPDrmi VR128:$src1, addr:$src2, timm:$cc)>;
[all …]
H A DX86InstrAVX512.td663 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, timm:$src3))]>,
670 timm:$src3))]>,
1953 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc),
1954 … (OpNode_su (_.VT _.RC:$src1), (_.VT _.RC:$src2), timm:$cc), 0, "_Int">,
1963 timm:$cc),
1965 … timm:$cc), 0, "_Int">, EVEX, VVVV, VEX_LIG, EVEX_CD8<_.EltSize, CD8VT1>,
1975 timm:$cc),
1977 timm:$cc), 0, "_Int">,
1988 timm:$cc))]>,
1997 timm:$cc))]>,
[all …]
H A DX86InstrXOP.td146 (vt128 (OpNode (vt128 VR128:$src1), timm:$src2)))]>,
152 (vt128 (OpNode (vt128 (load addr:$src1)), timm:$src2)))]>,
254 timm:$cc)))]>,
263 timm:$cc)))]>,
268 (vt128 VR128:$src1), timm:$cc),
270 (CommuteVPCOMCC timm:$cc))>;
425 (VT (X86vpermil2 RC:$src1, RC:$src2, RC:$src3, (i8 timm:$src4))))]>,
433 (i8 timm:$src4))))]>, REX_W,
441 RC:$src3, (i8 timm:$src4))))]>,
H A DX86InstrMMX.td68 [(set VR64:$dst, (IntId2 VR64:$src1, timm:$src2))]>,
113 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,
119 (i8 timm:$src3)))]>,
476 (int_x86_sse_pshuf_w VR64:$src1, timm:$src2))]>,
483 timm:$src2))]>,
516 timm:$src2))]>,
525 GR32orGR64:$src2, timm:$src3))]>,
534 timm:$src3))]>,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrCDE.td219 def : Pat<(i32 (int_arm_cde_cx1 timm:$coproc, timm:$imm)),
221 def : Pat<(i32 (int_arm_cde_cx1a timm:$coproc, GPRwithAPSR_NZCVnosp:$acc,
222 timm:$imm)),
225 def : Pat<(i32 (int_arm_cde_cx2 timm:$coproc, GPRwithAPSR_NZCVnosp:$n,
226 timm:$imm)),
229 def : Pat<(i32 (int_arm_cde_cx2a timm:$coproc, GPRwithAPSR_NZCVnosp:$acc,
230 GPRwithAPSR_NZCVnosp:$n, timm:$imm)),
233 def : Pat<(i32 (int_arm_cde_cx3 timm:$coproc, GPRwithAPSR_NZCVnosp:$n,
234 GPRwithAPSR_NZCVnosp:$m, timm:$imm)),
237 def : Pat<(i32 (int_arm_cde_cx3a timm:$coproc,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td142 (int_amdgcn_exp timm:$tgt, timm:$en,
145 done_val, timm:$vm),
146 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
147 ExpSrc2:$src2, ExpSrc3:$src3, timm:$vm, 0, timm:$en)
151 (int_amdgcn_exp_row timm:$tgt, timm:$en,
155 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
156 ExpSrc2:$src2, ExpSrc3:$src3, 0, 0, timm:$en)
160 (int_amdgcn_exp_compr timm:$tgt, timm:$en,
162 done_val, timm:$vm),
163 (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
[all …]
H A DDSDIRInstructions.td138 (f32 (int_amdgcn_lds_param_load timm:$attrchan, timm:$attr, M0)),
139 (LDS_PARAM_LOAD timm:$attr, timm:$attrchan, 0)
155 (f32 (int_amdgcn_lds_param_load timm:$attrchan, timm:$attr, M0)),
156 (DS_PARAM_LOAD timm:$attr, timm:$attrchan, 0, 1)
H A DBUFInstructions.td1337 (vt (st v4i32:$rsrc, 0, 0, (BUFSOffset i32:$soffset), timm:$offset,
1338 timm:$auxiliary, 0)),
1339 (!cast<MUBUF_Pseudo>(opcode # _OFFSET) SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset,
1344 (vt (st v4i32:$rsrc, 0, i32:$voffset, (BUFSOffset i32:$soffset), timm:$offset,
1345 timm:$auxiliary, 0)),
1346 …<MUBUF_Pseudo>(opcode # _OFFEN) VGPR_32:$voffset, SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$offset,
1351 (vt (st v4i32:$rsrc, i32:$vindex, 0, (BUFSOffset i32:$soffset), timm:$offset,
1352 timm:$auxiliary, timm)),
1353 …(!cast<MUBUF_Pseudo>(opcode # _IDXEN) VGPR_32:$vindex, SReg_128:$rsrc, SCSrc_b32:$soffset, timm:$o…
1358 (vt (st v4i32:$rsrc, i32:$vindex, i32:$voffset, (BUFSOffset i32:$soffset), timm:$offset,
[all …]
H A DLDSDIRInstructions.td
H A DVOP3Instructions.td413 (i32 timm:$attrchan),
414 (i32 timm:$attr),
415 (i1 timm:$high),
437 (i32 timm:$attrchan),
438 (i32 timm:$attr),
439 (i1 timm:$high), M0))]>;
792 i32:$old, timm:$byte_sel)),
953 def opsel_i1timm : SDNodeXForm<timm, [{
961 class SrcAndDstSelToOpSelXForm<int modifier_idx, bit dest_sel> : SDNodeXForm<timm, [{
993 def DstSelToOpSelXForm : SDNodeXForm<timm, [{
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfh.td500 def : Pat<(i32 (riscv_fcvt_x (f16 FPR16:$rs1), timm:$frm)), (FCVT_W_H $rs1, timm:$frm)>;
501 def : Pat<(i32 (riscv_fcvt_xu (f16 FPR16:$rs1), timm:$frm)), (FCVT_WU_H $rs1, timm:$frm)>;
520 def : Pat<(i32 (riscv_fcvt_x FPR16INX:$rs1, timm:$frm)), (FCVT_W_H_INX $rs1, timm:$frm)>;
521 def : Pat<(i32 (riscv_fcvt_xu FPR16INX:$rs1, timm:$frm)), (FCVT_WU_H_INX $rs1, timm:$frm)>;
538 def : Pat<(riscv_any_fcvt_w_rv64 (f16 FPR16:$rs1), timm:$frm), (FCVT_W_H $rs1, timm:$frm)>;
539 def : Pat<(riscv_any_fcvt_wu_rv64 (f16 FPR16:$rs1), timm:$frm), (FCVT_WU_H $rs1, timm:$frm)>;
546 def : Pat<(i64 (riscv_fcvt_x (f16 FPR16:$rs1), timm:$frm)), (FCVT_L_H $rs1, timm:$frm)>;
547 def : Pat<(i64 (riscv_fcvt_xu (f16 FPR16:$rs1), timm:$frm)), (FCVT_LU_H $rs1, timm:$frm)>;
568 def : Pat<(riscv_any_fcvt_w_rv64 FPR16INX:$rs1, timm:$frm), (FCVT_W_H_INX $rs1, timm:$frm)>;
569 def : Pat<(riscv_any_fcvt_wu_rv64 FPR16INX:$rs1, timm:$frm), (FCVT_WU_H_INX $rs1, timm:$frm)>;
[all …]
H A DRISCVInstrInfoZicbo.td74 timm, timm, (i32 0)),
77 (i32 0), timm, (i32 1)),
80 (i32 1), timm, (i32 1)),
H A DRISCVInstrInfoD.td550 def : Pat<(i32 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_W_D $rs1, timm:$frm)>;
551 def : Pat<(i32 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_WU_D $rs1, timm:$frm)>;
571 def : Pat<(i32 (riscv_fcvt_x FPR64IN32X:$rs1, timm:$frm)), (FCVT_W_D_IN32X $rs1, timm:$frm)>;
572 def : Pat<(i32 (riscv_fcvt_xu FPR64IN32X:$rs1, timm:$frm)), (FCVT_WU_D_IN32X $rs1, timm:$frm)>;
594 def : Pat<(riscv_any_fcvt_w_rv64 FPR64:$rs1, timm:$frm), (FCVT_W_D $rs1, timm:$frm)>;
595 def : Pat<(riscv_any_fcvt_wu_rv64 FPR64:$rs1, timm:$frm), (FCVT_WU_D $rs1, timm:$frm)>;
602 def : Pat<(i64 (riscv_fcvt_x FPR64:$rs1, timm:$frm)), (FCVT_L_D $rs1, timm:$frm)>;
603 def : Pat<(i64 (riscv_fcvt_xu FPR64:$rs1, timm:$frm)), (FCVT_LU_D $rs1, timm:$frm)>;
631 def : Pat<(riscv_any_fcvt_w_rv64 FPR64INX:$rs1, timm:$frm), (FCVT_W_D_INX $rs1, timm:$frm)>;
632 def : Pat<(riscv_any_fcvt_wu_rv64 FPR64INX:$rs1, timm:$frm), (FCVT_WU_D_INX $rs1, timm:$frm)>;
[all …]
H A DRISCVInstrInfoF.td319 [(set Ty:$rd, (vt (riscv_fround Ty:$rs1, Ty:$rs2, timm:$rm)))]> {
757 def : Pat<(i32 (riscv_fcvt_x FPR32:$rs1, timm:$frm)), (FCVT_W_S $rs1, timm:$frm)>;
758 def : Pat<(i32 (riscv_fcvt_xu FPR32:$rs1, timm:$frm)), (FCVT_WU_S $rs1, timm:$frm)>;
777 def : Pat<(i32 (riscv_fcvt_x FPR32INX:$rs1, timm:$frm)), (FCVT_W_S_INX $rs1, timm:$frm)>;
778 def : Pat<(i32 (riscv_fcvt_xu FPR32INX:$rs1, timm:$frm)), (FCVT_WU_S_INX $rs1, timm:$frm)>;
799 def : Pat<(riscv_any_fcvt_w_rv64 FPR32:$rs1, timm:$frm), (FCVT_W_S $rs1, timm:$frm)>;
800 def : Pat<(riscv_any_fcvt_wu_rv64 FPR32:$rs1, timm:$frm), (FCVT_WU_S $rs1, timm:$frm)>;
807 def : Pat<(i64 (riscv_fcvt_x FPR32:$rs1, timm:$frm)), (FCVT_L_S $rs1, timm:$frm)>;
808 def : Pat<(i64 (riscv_fcvt_xu FPR32:$rs1, timm:$frm)), (FCVT_LU_S $rs1, timm:$frm)>;
833 def : Pat<(riscv_any_fcvt_w_rv64 FPR32INX:$rs1, timm:$frm), (FCVT_W_S_INX $rs1, timm:$frm)>;
[all …]
H A DRISCVInstrInfoA.td281 : Pat<(intrin GPR:$addr, GPR:$incr, GPR:$mask, timm:$ordering),
282 (AMOInst GPR:$addr, GPR:$incr, GPR:$mask, timm:$ordering)>;
286 timm:$ordering),
288 timm:$ordering)>;
428 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
430 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;
435 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
437 GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;
H A DRISCVInstrInfoZfa.td244 def: Pat<(f32 (riscv_fli timm:$imm)), (FLI_S timm:$imm)>;
269 def: Pat<(f64 (riscv_fli timm:$imm)), (FLI_D timm:$imm)>;
299 def: Pat<(f16 (riscv_fli timm:$imm)), (FLI_H timm:$imm)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsics.td25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
32 def: Pat<(int_hexagon_A2_subri timm:$s10, IntRegs:$Rs),
48 def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$Rs, timm:$u5),
50 def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$Rs, timm:$u5),
52 def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$Rs, timm:$u5),
54 def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$Rs, timm:$u6),
56 def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$Rs, timm:$u6),
58 def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$Rs, timm:$u6),
63 def: Pat<(int_hexagon_A2_andir IntRegs:$Rs, timm:$s10),
67 def: Pat<(int_hexagon_A2_orir IntRegs:$Rs, timm:$s10),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrCall.td21 [(WebAssemblycallseq_start timm:$amt, timm:$amt2)]>;
23 [(WebAssemblycallseq_end timm:$amt, timm:$amt2)]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrInfo.td2046 // Pat<(Intrinsic timm:$imm)
2047 // (LAInst timm:$imm)>;
2048 def : Pat<(int_loongarch_lasx_xvldi timm:$imm),
2049 (XVLDI (to_valid_timm timm:$imm))>;
2051 def : Pat<(deriveLASXIntrinsic<Inst>.ret timm:$imm),
2052 (!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>;
2055 // Pat<(Intrinsic vty:$xj, timm:$imm)
2056 // (LAInst vty:$xj, timm:$imm)>;
2061 def : Pat<(deriveLASXIntrinsic<Inst>.ret (v32i8 LASX256:$xj), timm:$imm),
2062 (!cast<LAInst>(Inst) LASX256:$xj, (to_valid_timm timm:$imm))>;
[all …]
H A DLoongArchLSXInstrInfo.td228 def to_valid_timm : SDNodeXForm<timm, [{
2213 // Pat<(Intrinsic timm:$imm)
2214 // (LAInst timm:$imm)>;
2215 def : Pat<(int_loongarch_lsx_vldi timm:$imm),
2216 (VLDI (to_valid_timm timm:$imm))>;
2218 def : Pat<(deriveLSXIntrinsic<Inst>.ret timm:$imm),
2219 (!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>;
2222 // Pat<(Intrinsic vty:$vj, timm:$imm)
2223 // (LAInst vty:$vj, timm:$imm)>;
2228 def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj), timm:$imm),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrCompiler.td81 [(MxCallSeqStart timm:$amt1, timm:$amt2)]>;
85 [(MxCallSeqEnd timm:$amt1, timm:$amt2)]>;

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