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Searched refs:tfe (Results 1 – 22 of 22) sorted by relevance

/freebsd/sbin/ipfw/
H A Dtables.c1194 struct tflow_entry *tfe; in tentry_fill_key_type() local
1277 tfe = &tentry->k.flow; in tentry_fill_key_type()
1290 memcpy(&tfe->a.a4.sip, &tmp, 4); in tentry_fill_key_type()
1296 memcpy(&tfe->a.a6.sip6, &tmp, 16); in tentry_fill_key_type()
1321 tfe->proto = key; in tentry_fill_key_type()
1340 tfe->sport = port; in tentry_fill_key_type()
1356 memcpy(&tfe->a.a4.dip, &tmp, 4); in tentry_fill_key_type()
1362 memcpy(&tfe->a.a6.dip6, &tmp, 16); in tentry_fill_key_type()
1382 tfe->dport = port; in tentry_fill_key_type()
1386 tfe->af = af; in tentry_fill_key_type()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td427 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
429 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da"
452 R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
454 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
465 R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
467 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
477 R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
479 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
490 R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe),
492 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe"
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H A DSIInstrFormats.td344 bits<1> tfe;
370 let Inst{16} = tfe;
397 let Inst{16} = tfe;
409 bits<1> tfe;
434 let Inst{53} = tfe;
441 bits<1> tfe;
475 let Inst{3} = tfe;
486 let Inst{55} = tfe;
H A DBUFInstructions.td89 bits<1> tfe = 0;
155 // Bit supersedes tfe.
367 // Bit supersedes tfe.
455 string TFE = !if(isTFE, " tfe", "");
511 let tfe = isTFE;
617 let tfe = isTFE;
2348 let Inst{53} = ps.tfe;
2364 let Inst{55} = ps.tfe;
2455 let Inst{22} = ps.tfe;
2910 let Inst{53} = ps.tfe;
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H A DSIShrinkInstructions.cpp365 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in shrinkMIMG()
H A DFLATInstructions.td128 // We don't use tfe right now, and it was removed in gfx9.
129 bits<1> tfe = 0;
H A DSILoadStoreOptimizer.cpp927 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
H A DSIInstrInfo.td1094 def TFE : NamedBitOperand<"tfe">;
H A DSIInstrInfo.cpp4879 const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe); in verifyInstruction()
6885 getNamedOperand(MI, AMDGPU::OpName::tfe)) { in legalizeOperands()
H A DSIISelLowering.cpp14831 unsigned TFEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::tfe) - 1; in adjustWritemask()
15130 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe); in AddMemOpInit()
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dnvidia,tegra-vde.txt17 - tfe
54 "tfe", "ppb", "vdma", "frameid";
/freebsd/sys/netpfil/ipfw/
H A Dip_fw_table_algo.c3356 struct tflow_entry *tfe; in ta_dump_fhash_tentry() local
3359 tfe = &tent->k.flow; in ta_dump_fhash_tentry()
3361 tfe->af = ent->af; in ta_dump_fhash_tentry()
3362 tfe->proto = ent->proto; in ta_dump_fhash_tentry()
3363 tfe->dport = htons(ent->dport); in ta_dump_fhash_tentry()
3364 tfe->sport = htons(ent->sport); in ta_dump_fhash_tentry()
3370 tfe->a.a4.sip.s_addr = htonl(fe4->sip.s_addr); in ta_dump_fhash_tentry()
3371 tfe->a.a4.dip.s_addr = htonl(fe4->dip.s_addr); in ta_dump_fhash_tentry()
3376 tfe->a.a6.sip6 = fe6->sip6; in ta_dump_fhash_tentry()
3377 tfe->a.a6.dip6 = fe6->dip6; in ta_dump_fhash_tentry()
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/freebsd/sys/net/
H A Dif_vxlan.c608 struct vxlan_ftable_entry *fe, *tfe; in vxlan_ftable_flush()
612 LIST_FOREACH_SAFE(fe, &sc->vxl_ftable[i], vxlfe_hash, tfe) { in vxlan_ftable_flush()
622 struct vxlan_ftable_entry *fe, *tfe; in vxlan_ftable_expire()
628 LIST_FOREACH_SAFE(fe, &sc->vxl_ftable[i], vxlfe_hash, tfe) { in vxlan_ftable_expire()
606 struct vxlan_ftable_entry *fe, *tfe; vxlan_ftable_flush() local
620 struct vxlan_ftable_entry *fe, *tfe; vxlan_ftable_expire() local
/freebsd/sys/dts/arm/
H A Dimx51x.dtsi539 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */
H A Dimx53x.dtsi620 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp671 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in getInstruction()
962 AMDGPU::OpName::tfe); in convertMIMGInst()
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra114.dtsi279 "tfe", "ppb", "vdma", "frameid";
H A Dtegra20.dtsi346 "tfe", "ppb", "vdma", "frameid";
H A Dtegra30.dtsi525 "tfe", "ppb", "vdma", "frameid";
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp330 bool tfe; member
489 return Info ? Info->tfe : false; in getMUBUFTfe()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td863 [llvm_i32_ty, // texfailctrl(imm; bit 0 = tfe, bit 1 = lwe)
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3869 int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe); in validateMIMGDataSize()