/freebsd/sbin/ipfw/ |
H A D | tables.c | 1194 struct tflow_entry *tfe; in tentry_fill_key_type() local 1277 tfe = &tentry->k.flow; in tentry_fill_key_type() 1290 memcpy(&tfe->a.a4.sip, &tmp, 4); in tentry_fill_key_type() 1296 memcpy(&tfe->a.a6.sip6, &tmp, 16); in tentry_fill_key_type() 1321 tfe->proto = key; in tentry_fill_key_type() 1340 tfe->sport = port; in tentry_fill_key_type() 1356 memcpy(&tfe->a.a4.dip, &tmp, 4); in tentry_fill_key_type() 1362 memcpy(&tfe->a.a6.dip6, &tmp, 16); in tentry_fill_key_type() 1382 tfe->dport = port; in tentry_fill_key_type() 1386 tfe->af = af; in tentry_fill_key_type() [all …]
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | MIMGInstructions.td | 427 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da), 429 let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$cpol$r128$tfe$lwe$da" 452 R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe), 454 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 465 R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe), 467 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 477 R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe), 479 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" 490 R128A16:$r128, A16:$a16, TFE:$tfe, LWE:$lwe), 492 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$cpol$r128$a16$tfe$lwe" [all …]
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H A D | SIInstrFormats.td | 344 bits<1> tfe; 370 let Inst{16} = tfe; 397 let Inst{16} = tfe; 409 bits<1> tfe; 434 let Inst{53} = tfe; 441 bits<1> tfe; 475 let Inst{3} = tfe; 486 let Inst{55} = tfe;
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H A D | BUFInstructions.td | 89 bits<1> tfe = 0; 155 // Bit supersedes tfe. 367 // Bit supersedes tfe. 455 string TFE = !if(isTFE, " tfe", ""); 511 let tfe = isTFE; 617 let tfe = isTFE; 2348 let Inst{53} = ps.tfe; 2364 let Inst{55} = ps.tfe; 2455 let Inst{22} = ps.tfe; 2910 let Inst{53} = ps.tfe; [all …]
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H A D | SIShrinkInstructions.cpp | 365 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in shrinkMIMG()
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H A D | FLATInstructions.td | 128 // We don't use tfe right now, and it was removed in gfx9. 129 bits<1> tfe = 0;
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H A D | SILoadStoreOptimizer.cpp | 927 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
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H A D | SIInstrInfo.td | 1094 def TFE : NamedBitOperand<"tfe">;
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H A D | SIInstrInfo.cpp | 4879 const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe); in verifyInstruction() 6885 getNamedOperand(MI, AMDGPU::OpName::tfe)) { in legalizeOperands()
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H A D | SIISelLowering.cpp | 14831 unsigned TFEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::tfe) - 1; in adjustWritemask() 15130 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe); in AddMemOpInit()
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/freebsd/sys/contrib/device-tree/Bindings/media/ |
H A D | nvidia,tegra-vde.txt | 17 - tfe 54 "tfe", "ppb", "vdma", "frameid";
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/freebsd/sys/netpfil/ipfw/ |
H A D | ip_fw_table_algo.c | 3356 struct tflow_entry *tfe; in ta_dump_fhash_tentry() local 3359 tfe = &tent->k.flow; in ta_dump_fhash_tentry() 3361 tfe->af = ent->af; in ta_dump_fhash_tentry() 3362 tfe->proto = ent->proto; in ta_dump_fhash_tentry() 3363 tfe->dport = htons(ent->dport); in ta_dump_fhash_tentry() 3364 tfe->sport = htons(ent->sport); in ta_dump_fhash_tentry() 3370 tfe->a.a4.sip.s_addr = htonl(fe4->sip.s_addr); in ta_dump_fhash_tentry() 3371 tfe->a.a4.dip.s_addr = htonl(fe4->dip.s_addr); in ta_dump_fhash_tentry() 3376 tfe->a.a6.sip6 = fe6->sip6; in ta_dump_fhash_tentry() 3377 tfe->a.a6.dip6 = fe6->dip6; in ta_dump_fhash_tentry() [all …]
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/freebsd/sys/net/ |
H A D | if_vxlan.c | 608 struct vxlan_ftable_entry *fe, *tfe; in vxlan_ftable_flush() 612 LIST_FOREACH_SAFE(fe, &sc->vxl_ftable[i], vxlfe_hash, tfe) { in vxlan_ftable_flush() 622 struct vxlan_ftable_entry *fe, *tfe; in vxlan_ftable_expire() 628 LIST_FOREACH_SAFE(fe, &sc->vxl_ftable[i], vxlfe_hash, tfe) { in vxlan_ftable_expire() 606 struct vxlan_ftable_entry *fe, *tfe; vxlan_ftable_flush() local 620 struct vxlan_ftable_entry *fe, *tfe; vxlan_ftable_expire() local
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/freebsd/sys/dts/arm/ |
H A D | imx51x.dtsi | 539 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */
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H A D | imx53x.dtsi | 620 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
H A D | AMDGPUDisassembler.cpp | 671 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); in getInstruction() 962 AMDGPU::OpName::tfe); in convertMIMGInst()
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/freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
H A D | tegra114.dtsi | 279 "tfe", "ppb", "vdma", "frameid";
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H A D | tegra20.dtsi | 346 "tfe", "ppb", "vdma", "frameid";
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H A D | tegra30.dtsi | 525 "tfe", "ppb", "vdma", "frameid";
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
H A D | AMDGPUBaseInfo.cpp | 330 bool tfe; member 489 return Info ? Info->tfe : false; in getMUBUFTfe()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | IntrinsicsAMDGPU.td | 863 [llvm_i32_ty, // texfailctrl(imm; bit 0 = tfe, bit 1 = lwe)
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 3869 int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe); in validateMIMGDataSize()
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