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Searched refs:stageScheduled (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp712 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
1108 Stages[MI] = Schedule.stageScheduled(SU); in computeScheduledInsts()
2678 int DefStageNum = Schedule.stageScheduled(getSUnit(LoopDef)); in applyInstrChange()
2680 int BaseStageNum = Schedule.stageScheduled(SU); in applyInstrChange()
2985 int StageInst1 = stageScheduled(SU); in orderDependence()
3003 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) { in orderDependence()
3007 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) { in orderDependence()
3011 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) { in orderDependence()
3020 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) { in orderDependence()
3028 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) { in orderDependence()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachinePipeliner.h613 return (stageScheduled(SU) == (int)StageNum); in isScheduledAtStage()
618 int stageScheduled(SUnit *SU) const { in stageScheduled() function
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp6862 int Stg = SMS.stageScheduled(const_cast<SUnit *>(&SU)); in tooMuchRegisterPressure()
6870 int OStg = SMS.stageScheduled(S.getSUnit()); in tooMuchRegisterPressure()
6948 auto Stg = SMS.stageScheduled(SU); in tooMuchRegisterPressure()
6953 auto Stg2 = SMS.stageScheduled(const_cast<SUnit *>(S.getSUnit())); in tooMuchRegisterPressure()