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Searched refs:ssub (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td406 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
407 ssub))>;
417 ssub)),
427 ssub)),
438 ssub)),
448 ssub)),
456 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
457 ssub))>;
467 ssub))>;
480 ssub))>;
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H A DAArch64InstrInfo.td3336 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
3337 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
3339 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
3340 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
3504 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
3508 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
3921 am_indexed32, am_unscaled32, uimm12s4, ssub>;
3929 am_indexed32, am_unscaled32, uimm12s4, ssub>;
4171 defm : VecROStoreLane0Pat<ro32, store, v4i32, i32, i32, ssub, STRSroW, STRSroX>;
4172 defm : VecROStoreLane0Pat<ro32, store, v4f32, f32, i32, ssub, STRSroW, STRSroX>;
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H A DAArch64MIPeepholeOpt.cpp259 SrcMI->getOperand(1).getSubReg() != AArch64::ssub)) in visitORR()
262 if (SrcMI->getOperand(1).getSubReg() == AArch64::ssub) { in visitORR()
H A DAArch64SVEInstrInfo.td827 (DUP_ZZI_S (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$src, ssub), 0)>;
829 (DUP_ZZI_S (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$src, ssub), 0)>;
1991 (LASTB_VPZ_S (PTRUE_S 31), ZPR:$Z1), ssub))>;
3169 (INSERT_SUBREG (nxv16i8 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
3171 (INSERT_SUBREG (nxv8i16 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
3173 (INSERT_SUBREG (nxv4i32 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
3190 (INSERT_SUBREG (nxv4f32 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
3192 (INSERT_SUBREG (nxv2f32 (IMPLICIT_DEF)), FPR32:$src, ssub)>;
3211 (SEL_ZPZZ_S (PTRUE_S 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$src, ssub), ZPR:$vec)>;
3327 (EXTRACT_SUBREG (DUP_ZZI_B ZPR:$vec, sve_elm_idx_extdup_b:$index), ssub)>;
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H A DAArch64RegisterInfo.td26 def ssub : SubRegIndex<32>;
382 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
H A DAArch64InstrFormats.td5539 FPR32:$Rn, (EXTRACT_SUBREG V128:$Rm, ssub), FPR32:$Ra)>;
5545 (EXTRACT_SUBREG V128:$Rn, ssub), FPR32:$Rm, FPR32:$Ra)>;
8937 (EXTRACT_SUBREG V128:$Rn, ssub), V128:$Rm, VectorIndexS:$idx)>;
8985 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
8997 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
H A DAArch64InstrInfo.cpp5630 case AArch64::ssub: in foldMemoryOperandImpl()
H A DAArch64ISelLowering.cpp9998 SetVecVal(AArch64::ssub); in LowerFCOPYSIGN()
10024 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, BSP); in LowerFCOPYSIGN()
H A DSVEInstrFormats.td1715 (!cast<Instruction>(NAME # _S) $Zn, (INSERT_SUBREG (IMPLICIT_DEF), $Vm, ssub))>;
/freebsd/contrib/nvi/regex/
H A Dengine.c302 sopno ssub; /* start sop of subsubRE */ in dissect() local
362 ssub = ss + 1; in dissect()
365 if (slow(m, sp, rest, ssub, esub) != NULL) { in dissect()
366 dp = dissect(m, sp, rest, ssub, esub); in dissect()
386 ssub = ss + 1; in dissect()
391 sep = slow(m, ssp, rest, ssub, esub); in dissect()
403 assert(slow(m, ssp, sep, ssub, esub) == rest); in dissect()
404 dp = dissect(m, ssp, sep, ssub, esub); in dissect()
422 ssub = ss + 1; in dissect()
426 if (slow(m, sp, rest, ssub, esub) == rest) in dissect()
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/freebsd/lib/libc/regex/
H A Dengine.c424 sopno ssub; /* start sop of subsubRE */ in dissect() local
488 ssub = ss + 1; in dissect()
491 if (walk(m, sp, rest, ssub, esub, false) != NULL) { in dissect()
492 dp = dissect(m, sp, rest, ssub, esub); in dissect()
512 ssub = ss + 1; in dissect()
517 sep = walk(m, ssp, rest, ssub, esub, false); in dissect()
529 assert(walk(m, ssp, sep, ssub, esub, false) == rest); in dissect()
530 dp = dissect(m, ssp, sep, ssub, esub); in dissect()
548 ssub = ss + 1; in dissect()
552 if (walk(m, sp, rest, ssub, esub, false) == rest) in dissect()
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/freebsd/contrib/llvm-project/llvm/lib/Support/
H A Dregengine.inc346 sopno ssub; /* start sop of subsubRE */
405 ssub = ss + 1;
408 if (slow(m, sp, rest, ssub, esub) != NULL) {
409 const char *dp = dissect(m, sp, rest, ssub, esub);
430 ssub = ss + 1;
435 sep = slow(m, ssp, rest, ssub, esub);
447 assert(slow(m, ssp, sep, ssub, esub) == rest);
449 const char *dp = dissect(m, ssp, sep, ssub, esub);
469 ssub = ss + 1;
473 if (slow(m, sp, rest, ssub, esub) == rest)
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp662 SubReg = AArch64::ssub; in getSubRegForClass()
3752 return BuildFn(AArch64::ssub); in emitScalarToVector()
3774 if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) { in emitNarrowVector()
3869 ExtractSubReg = AArch64::ssub; in getLaneCopyOpcode()
4220 SubregIdx = AArch64::ssub; in getInsertVecEltOpInfo()
4223 SubregIdx = AArch64::ssub; in getInsertVecEltOpInfo()
4239 SubregIdx = AArch64::ssub; in getInsertVecEltOpInfo()
5813 if (SubReg != AArch64::ssub && SubReg != AArch64::dsub) { in selectBuildVector()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def318 // llvm.vp.ssub.sat(x,y,mask,vlen)