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Searched refs:simm (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DAMDGPU.cpp169 int64_t simm = (static_cast<int64_t>(val) - 4) / 4; in relocate() local
170 checkInt(ctx, loc, simm, 16, rel); in relocate()
171 write16le(loc, simm); in relocate()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXqci.td556 (ins GPRNoX0:$rd, GPRNoX0:$rs1, InTyRs2:$rs2, simm5:$simm),
557 opcodestr, "$rd, $rs1, $rs2, $simm"> {
559 bits<5> simm;
561 let Inst{31-25} = {simm, funct2};
1341 …: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), (XLenVT GPRNoX0:$rs2), Cond)), simm5:$simm, (X…
1342 (Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm)>;
1345 …VT (setcc (XLenVT GPRNoX0:$rs1), (XLenVT GPRNoX0:$rs2), Cond)), (XLenVT GPRNoX0:$rd), simm5:$simm),
1346 (Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm)>;
1349 …: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), InTyImm:$imm, Cond)), simm5:$simm, (XLenVT GPR…
1350 (Inst GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm:$imm, simm5:$simm)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrMVE.td1717 defvar UnpredPat = (VTI.Vec (op (VTI.Vec MQPR:$src), timm:$simm));
1721 (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm))>;
1724 (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm,
2568 def : Pat<(v16i8 (ARMvmovImm timm:$simm)),
2569 (v16i8 (MVE_VMOVimmi8 nImmSplatI8:$simm))>;
2570 def : Pat<(v8i16 (ARMvmovImm timm:$simm)),
2571 (v8i16 (MVE_VMOVimmi16 nImmSplatI16:$simm))>;
2572 def : Pat<(v4i32 (ARMvmovImm timm:$simm)),
2573 (v4i32 (MVE_VMOVimmi32 nImmVMOVI32:$simm))>;
2574 def : Pat<(v2i64 (ARMvmovImm timm:$simm)),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td1034 def simm # I : Operand<i32> {
1048 def simm # I # _64 : Operand<i64> {
1067 def simm # I : Operand<i32> {
1167 let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm" # I));
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.td127 class simm<int num, int shift = 0> : Operand<i32>,
429 def simm8_2 : simm<8, 2>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td10606 …oreUnscaledOffset<0b00, 0b00, FPR8 , (outs), (ins FPR8 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;
10607 …oreUnscaledOffset<0b01, 0b00, FPR16 , (outs), (ins FPR16 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;
10608 …oreUnscaledOffset<0b10, 0b00, FPR32 , (outs), (ins FPR32 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;
10609 …oreUnscaledOffset<0b11, 0b00, FPR64 , (outs), (ins FPR64 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;
10610 …oreUnscaledOffset<0b00, 0b10, FPR128, (outs), (ins FPR128:$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">;
10611 …oreUnscaledOffset<0b00, 0b01, FPR8 , (outs FPR8 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;
10612 …oreUnscaledOffset<0b01, 0b01, FPR16 , (outs FPR16 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;
10613 …oreUnscaledOffset<0b10, 0b01, FPR32 , (outs FPR32 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;
10614 …oreUnscaledOffset<0b11, 0b01, FPR64 , (outs FPR64 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;
10615 …oreUnscaledOffset<0b00, 0b11, FPR128, (outs FPR128:$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;
H A DAArch64InstrFormats.td12833 def i : BaseLRCPC3<size, /*V*/1, opc, oops, iops, asm, "\t$Rt, [$Rn{, $simm}]", /*cstr*/""> {
12834 bits<9> simm; // signed immediate encoded in imm9=Rt2:imm4
12835 let Inst{20-12} = simm;