Searched refs:simm (Results 1 – 6 of 6) sorted by relevance
/freebsd/contrib/llvm-project/lld/ELF/Arch/ |
H A D | AMDGPU.cpp | 169 int64_t simm = (static_cast<int64_t>(val) - 4) / 4; in relocate() local 170 checkInt(loc, simm, 16, rel); in relocate() 171 write16le(loc, simm); in relocate()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMInstrMVE.td | 1716 defvar UnpredPat = (VTI.Vec (op (VTI.Vec MQPR:$src), timm:$simm)); 1720 (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm))>; 1723 (VTI.Vec (Inst (VTI.Vec MQPR:$src), imm_type:$simm, 2634 def : Pat<(v16i8 (ARMvmovImm timm:$simm)), 2635 (v16i8 (MVE_VMOVimmi8 nImmSplatI8:$simm))>; 2636 def : Pat<(v8i16 (ARMvmovImm timm:$simm)), 2637 (v8i16 (MVE_VMOVimmi16 nImmSplatI16:$simm))>; 2638 def : Pat<(v4i32 (ARMvmovImm timm:$simm)), 2639 (v4i32 (MVE_VMOVimmi32 nImmVMOVI32:$simm))>; 2640 def : Pat<(v2i64 (ARMvmovImm timm:$simm)), [all...] |
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.td | 1024 def simm # I : Operand<i32> { 1038 def simm # I # _64 : Operand<i64> { 1057 def simm # I : Operand<i32> { 1157 let MIOperandInfo = (ops ptr_rc, !cast<Operand>("simm" # I));
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYInstrInfo.td | 127 class simm<int num, int shift = 0> : Operand<i32>, 429 def simm8_2 : simm<8, 2>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64InstrInfo.td | 10029 …oreUnscaledOffset<0b00, 0b00, FPR8 , (outs), (ins FPR8 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; 10030 …oreUnscaledOffset<0b01, 0b00, FPR16 , (outs), (ins FPR16 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; 10031 …oreUnscaledOffset<0b10, 0b00, FPR32 , (outs), (ins FPR32 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; 10032 …oreUnscaledOffset<0b11, 0b00, FPR64 , (outs), (ins FPR64 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; 10033 …oreUnscaledOffset<0b00, 0b10, FPR128, (outs), (ins FPR128:$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; 10034 …oreUnscaledOffset<0b00, 0b01, FPR8 , (outs FPR8 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">; 10035 …oreUnscaledOffset<0b01, 0b01, FPR16 , (outs FPR16 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">; 10036 …oreUnscaledOffset<0b10, 0b01, FPR32 , (outs FPR32 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">; 10037 …oreUnscaledOffset<0b11, 0b01, FPR64 , (outs FPR64 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">; 10038 …oreUnscaledOffset<0b00, 0b11, FPR128, (outs FPR128:$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">;
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H A D | AArch64InstrFormats.td | 12246 def i : BaseLRCPC3<size, /*V*/1, opc, oops, iops, asm, "\t$Rt, [$Rn{, $simm}]", /*cstr*/""> { 12247 bits<9> simm; // signed immediate encoded in imm9=Rt2:imm4 12248 let Inst{20-12} = simm;
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