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Searched refs:shift_type (Results 1 – 3 of 3) sorted by relevance

/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.h445 ARM_ShifterType shift_type);
449 ARM_ShifterType shift_type);
H A DEmulateInstructionARM.cpp3743 ARM_ShifterType shift_type) { in EmulateShiftImm() argument
3762 if (shift_type == SRType_ROR && use_encoding == eEncodingT1) { in EmulateShiftImm()
3779 if (shift_type == SRType_RRX) in EmulateShiftImm()
3800 if (shift_type == SRType_ROR && imm5 == 0) in EmulateShiftImm()
3801 shift_type = SRType_RRX; in EmulateShiftImm()
3810 (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5)); in EmulateShiftImm()
3812 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success); in EmulateShiftImm()
3829 ARM_ShifterType shift_type) { in EmulateShiftReg() argument
3883 uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success); in EmulateShiftReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td2561 class BaseShift<bit size, bits<2> shift_type, RegisterClass regtype, string asm,
2565 let Inst{11-10} = shift_type;
2568 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
2569 def Wr : BaseShift<0b0, shift_type, GPR32, asm>;
2571 def Xr : BaseShift<0b1, shift_type, GPR64, asm, OpNode>;