Searched refs:set_masked (Results 1 – 2 of 2) sorted by relevance
| /freebsd/sys/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_pll.c | 480 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) in set_masked() function
508 val = set_masked(val, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in set_divisors()
509 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in set_divisors()
510 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); in set_divisors()
733 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pll_set_std()
734 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pll_set_std()
735 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pll_set_std()
920 reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width); in pllx_set_freq()
921 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pllx_set_freq()
922 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
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| /freebsd/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_pll.c | 673 set_masked(uint32_t val, uint32_t v, uint32_t shift, uint32_t width) in set_masked() function
701 val = set_masked(val, m, mnp_bits->m_shift, mnp_bits->m_width); in set_divisors()
702 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width); in set_divisors()
703 val = set_masked(val, p, mnp_bits->p_shift, mnp_bits->p_width); in set_divisors()
931 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width); in pll_set_std()
932 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); in pll_set_std()
933 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pll_set_std()
1154 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
1191 reg = set_masked(reg, n, mnp_bits->n_shift, in pllx_set_freq()
1209 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
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