Searched refs:setRegAllocationHint (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIShrinkInstructions.cpp | 551 MRI->setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); in shrinkScalarLogicOp()
552 MRI->setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg()); in shrinkScalarLogicOp()
859 MRI->setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); in runOnMachineFunction()
860 MRI->setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); in runOnMachineFunction()
966 MRI->setRegAllocationHint(DstReg, 0, VCCReg); in runOnMachineFunction()
983 MRI->setRegAllocationHint(SReg, 0, VCCReg); in runOnMachineFunction()
999 MRI->setRegAllocationHint(SDst->getReg(), 0, VCCReg); in runOnMachineFunction()
1009 MRI->setRegAllocationHint(Src2->getReg(), 0, VCCReg); in runOnMachineFunction()
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| H A D | SIInstrInfo.cpp | 8953 MRI.setRegAllocationHint(UnusedCarry, 0, RI.getVCC()); in getAddNoCarry()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 802 void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) { in setRegAllocationHint() function
819 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); in setSimpleHint()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 405 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
407 MRI->setRegAllocationHint(NewReg, in updateRegAllocHint()
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| H A D | MVETPAndVPTOptimisationsPass.cpp | 1053 MF->getRegInfo().setRegAllocationHint(R, ARMRI::RegLR, 0); in HintDoLoopStartReg()
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| H A D | ARMLoadStoreOptimizer.cpp | 2469 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2470 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
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