| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 127 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); in AVRTargetLowering()
128 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); in AVRTargetLowering()
129 setIndexedStoreAction(ISD::PRE_DEC, MVT::i8, Legal); in AVRTargetLowering()
130 setIndexedStoreAction(ISD::PRE_DEC, MVT::i16, Legal); in AVRTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2626 void setIndexedStoreAction(ArrayRef<unsigned> IdxModes, MVT VT, in setIndexedStoreAction() function
2632 void setIndexedStoreAction(ArrayRef<unsigned> IdxModes, ArrayRef<MVT> VTs, in setIndexedStoreAction() function
2635 setIndexedStoreAction(IdxModes, VT, Action); in setIndexedStoreAction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 683 setIndexedStoreAction(IM, VT, Expand); in initActions()
703 setIndexedStoreAction(IM, VT, Expand); in initActions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 238 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
239 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
240 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
241 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
242 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
246 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
247 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 329 setIndexedStoreAction(im, VT, Legal); in addMVEVectorTypes()
359 setIndexedStoreAction(im, VT, Legal); in addMVEVectorTypes()
444 setIndexedStoreAction(im, VT, Legal); in addMVEVectorTypes()
1131 setIndexedStoreAction(im, MVT::i1, Legal); in ARMTargetLowering()
1132 setIndexedStoreAction(im, MVT::i8, Legal); in ARMTargetLowering()
1133 setIndexedStoreAction(im, MVT::i16, Legal); in ARMTargetLowering()
1134 setIndexedStoreAction(im, MVT::i32, Legal); in ARMTargetLowering()
1139 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1063 setIndexedStoreAction(im, MVT::i8, Legal); in AArch64TargetLowering()
1064 setIndexedStoreAction(im, MVT::i16, Legal); in AArch64TargetLowering()
1065 setIndexedStoreAction(im, MVT::i32, Legal); in AArch64TargetLowering()
1066 setIndexedStoreAction(im, MVT::i64, Legal); in AArch64TargetLowering()
1067 setIndexedStoreAction(im, MVT::f64, Legal); in AArch64TargetLowering()
1068 setIndexedStoreAction(im, MVT::f32, Legal); in AArch64TargetLowering()
1069 setIndexedStoreAction(im, MVT::f16, Legal); in AArch64TargetLowering()
1070 setIndexedStoreAction(im, MVT::bf16, Legal); in AArch64TargetLowering()
1944 setIndexedStoreAction(im, VT, Legal); in addTypeForNEON()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1429 setIndexedStoreAction(im, MVT::i8, Legal); in RISCVTargetLowering()
1431 setIndexedStoreAction(im, MVT::i16, Legal); in RISCVTargetLowering()
1433 setIndexedStoreAction(im, MVT::i32, Legal); in RISCVTargetLowering()
1437 setIndexedStoreAction(im, MVT::i64, Legal); in RISCVTargetLowering()
1447 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); in RISCVTargetLowering()
1448 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); in RISCVTargetLowering()
1449 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); in RISCVTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1823 setIndexedStoreAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
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| H A D | HexagonISelLoweringHVX.cpp | 194 setIndexedStoreAction(ISD::POST_INC, T, Legal); in initializeHVXLowering()
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