| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrInfo.cpp | 217 Cond[0].setImm(Xtensa::BNE); in reverseBranchCondition()
220 Cond[0].setImm(Xtensa::BEQ); in reverseBranchCondition()
223 Cond[0].setImm(Xtensa::BGE); in reverseBranchCondition()
226 Cond[0].setImm(Xtensa::BLT); in reverseBranchCondition()
229 Cond[0].setImm(Xtensa::BGEU); in reverseBranchCondition()
232 Cond[0].setImm(Xtensa::BLTU); in reverseBranchCondition()
235 Cond[0].setImm(Xtensa::BNEI); in reverseBranchCondition()
238 Cond[0].setImm(Xtensa::BEQI); in reverseBranchCondition()
241 Cond[0].setImm(Xtensa::BLTI); in reverseBranchCondition()
244 Cond[0].setImm(Xtensa::BGEI); in reverseBranchCondition()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ClauseMergePass.cpp | 103 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
154 RootCFAlu.getOperand(Mode0Idx).setImm( in mergeIfPossible()
156 RootCFAlu.getOperand(KBank0Idx).setImm( in mergeIfPossible()
159 .setImm(LatrCFAlu.getOperand(KBank0LineIdx).getImm()); in mergeIfPossible()
162 RootCFAlu.getOperand(Mode1Idx).setImm( in mergeIfPossible()
164 RootCFAlu.getOperand(KBank1Idx).setImm( in mergeIfPossible()
167 .setImm(LatrCFAlu.getOperand(KBank1LineIdx).getImm()); in mergeIfPossible()
169 RootCFAlu.getOperand(CntIdx).setImm(CumuledInsts); in mergeIfPossible()
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| H A D | R600InstrInfo.cpp | 737 PredSet->getOperand(2).setImm(Cond[1].getImm()); in insertBranch()
752 PredSet->getOperand(2).setImm(Cond[1].getImm()); in insertBranch()
898 MO.setImm(R600::PRED_SETNE_INT); in reverseBranchCondition()
901 MO.setImm(R600::PRED_SETE_INT); in reverseBranchCondition()
904 MO.setImm(R600::PRED_SETNE); in reverseBranchCondition()
907 MO.setImm(R600::PRED_SETE); in reverseBranchCondition()
938 MI.getOperand(8).setImm(0); in PredicateInstruction()
1318 MIB->getOperand(20).setImm(0); in buildSlotOfVectorInstruction()
1352 MI.getOperand(Idx).setImm(Imm); in setImmOperand()
1437 FlagOp.setImm(1); in addFlag()
[all …]
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| H A D | R600Packetizer.cpp | 214 MI->getOperand(LastOp).setImm(Bit); in setIsLastBit()
295 MI->getOperand(Op).setImm(BS[i]); in addToPacket()
299 MI.getOperand(Op).setImm(BS.back()); in addToPacket()
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| H A D | SIShrinkInstructions.cpp | 274 Src1.setImm(SignExtend32(Src1.getImm(), 32)); in shrinkScalarCompare()
288 Src1.setImm(SignExtend64(Src1.getImm(), 32)); in shrinkScalarCompare()
597 SrcImm->setImm(NewImm); in shrinkScalarLogicOp()
874 Src.setImm(static_cast<int64_t>(ModImm)); in run()
915 Src1->setImm(SignExtend64(Src1->getImm(), 32)); in run()
938 Src.setImm(SignExtend64(Src.getImm(), 32)); in run()
942 Src.setImm(static_cast<int64_t>(ModImm)); in run()
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| H A D | R600ControlFlowFinalizer.cpp | 432 ClauseHead.getOperand(7).setImm(ClauseContent.size() - 1); in MakeALUClause()
449 Clause.first->getOperand(0).setImm(0); in EmitALUClause()
459 MI.getOperand(0).setImm(Addr + MI.getOperand(0).getImm()); in CounterPropagateAddr()
603 IfOrElseInst->getOperand(1).setImm(1); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.cpp | 80 MI.getOperand(OffsetOperandNum).setImm(Offset); in eliminateFrameIndex()
103 ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset)); in eliminateFrameIndex()
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| H A D | WebAssemblySetP2AlignOperands.cpp | 73 MI.getOperand(OperandNo).setImm(P2Align); in rewriteP2Align()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86EvexToVex.cpp | |
| H A D | X86CompressEVEX.cpp | 130 Imm.setImm(Imm.getImm() * Scale); in performCustomAdjustments()
147 Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1)); in performCustomAdjustments()
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| H A D | X86InstrBuilder.h | 130 MI->getOperand(Operand + 1).setImm(1); in setDirectAddressInInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 1366 Cond[0].setImm(RISCV::BNE); in reverseBranchCondition()
1369 Cond[0].setImm(RISCV::BEQ); in reverseBranchCondition()
1372 Cond[0].setImm(RISCV::BGE); in reverseBranchCondition()
1375 Cond[0].setImm(RISCV::BLT); in reverseBranchCondition()
1378 Cond[0].setImm(RISCV::BGEU); in reverseBranchCondition()
1381 Cond[0].setImm(RISCV::BLTU); in reverseBranchCondition()
1384 Cond[0].setImm(RISCV::CV_BNEIMM); in reverseBranchCondition()
1387 Cond[0].setImm(RISCV::CV_BEQIMM); in reverseBranchCondition()
1390 Cond[0].setImm(RISCV::QC_BNEI); in reverseBranchCondition()
1393 Cond[0].setImm(RISCV::QC_BEQI); in reverseBranchCondition()
[all …]
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| H A D | RISCVVectorPeephole.cpp | 615 SrcPolicy.setImm(SrcPolicy.getImm() | RISCVVType::TAIL_AGNOSTIC); in foldUndefPassthruVMV_V_V()
689 Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc())).setImm(Policy); in foldVMV_V_V()
811 True.getOperand(RISCVII::getVecPolicyOpNum(True.getDesc())).setImm(Policy); in foldVMergeToMask()
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| H A D | RISCVFoldMemOffset.cpp | 274 MemMI->getOperand(2).setImm(NewOffset); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64StackTaggingPreRA.cpp | 322 TagOp.setImm(0); in findFirstSlotCandidate()
324 TagOp.setImm(MaxScoreST.Tag); in findFirstSlotCandidate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 722 MI.getOperand(3).setImm(3 - Immed); in simplifyCode()
861 MI.getOperand(2).setImm(NewElem); in simplifyCode()
1275 MI.getOperand(2).setImm(0); in simplifyCode()
1822 BI1->getOperand(0).setImm(NewPredicate1); in eliminateRedundantCompare()
1825 BI2->getOperand(0).setImm(NewPredicate2); in eliminateRedundantCompare()
1828 CMPI1->getOperand(2).setImm(NewImm1); in eliminateRedundantCompare()
1841 CMPI2->getOperand(2).setImm(NewImm2); in eliminateRedundantCompare()
1945 MI.getOperand(2).setImm(NewSH); in emitRLDICWhenLoweringJumpTables()
1946 MI.getOperand(3).setImm(NewMB); in emitRLDICWhenLoweringJumpTables()
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| H A D | PPCVSXSwapRemoval.cpp | 870 MI->getOperand(2).setImm(EltNo); in handleSpecialSwappables()
872 MI->getOperand(1).setImm(EltNo); in handleSpecialSwappables()
894 MI->getOperand(3).setImm(Selector); in handleSpecialSwappables()
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| H A D | PPCInstrInfo.cpp | 1208 MI.getOperand(4).setImm((ME + 1) & 31); in commuteInstructionImpl()
1209 MI.getOperand(5).setImm((MB - 1) & 31); in commuteInstructionImpl()
2060 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0); in reverseBranchCondition()
2063 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in reverseBranchCondition()
2560 UseMI->getOperand(0).setImm(Pred); in optimizeCompareInstr()
2561 CmpInstr.getOperand(2).setImm(0); in optimizeCompareInstr()
2740 MI->getOperand(2).setImm(Mask); in optimizeCompareInstr()
2749 MI->getOperand(2).setImm(Mask); in optimizeCompareInstr()
2777 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second); in optimizeCompareInstr()
3634 ADDIMI->getOperand(2).setImm(OffsetAddi + OffsetImm); in foldFrameOffset()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZShortenInst.cpp | 100 MI.getOperand(1).setImm(Imm >> 16); in shortenIIF()
370 ImmMO.setImm(ImmMO.getImm() & 0xfff); in processBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/Disassembler/ |
| H A D | BPFDisassembler.cpp | 204 Op.setImm(Make_64(Hi, Op.getImm())); in getInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMMCInstLower.cpp | 174 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
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| H A D | MVEVPTBlockPass.cpp | 226 Iter->getOperand(OpIdx).setImm(CurrentPredicate); in CreateVPTBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVExtract.cpp | 181 Op.setImm(MaxAlign->value()); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInst.h | 89 void setImm(int64_t Val) { in setImm() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/ |
| H A D | LanaiDisassembler.cpp | 121 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
|