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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dzynq-reset.txt8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
28 96 : dmac reset
29 128: usb0 reset
30 129: usb1 reset
[all …]
H A Dreset.txt3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
[all …]
H A Dti-syscon-reset.txt4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
13 and provides reset management functionality for various hardware modules
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
31 Should contain 7 cells for each reset expose
[all...]
H A Dfsl,imx7-src.txt4 Please also refer to reset.txt in this directory for common reset
17 - #reset-cells: 1, see below
21 src: reset-controller@30390000 {
25 #reset-cells = <1>;
29 Specifying reset lines connected to IP modules
32 The system reset controller can be used to reset various set of
33 peripherals. Device nodes that need access to reset lines should
34 specify them as a reset phandle in their corresponding node as
35 specified in reset.txt.
45 reset-names = "pciephy", "apps";
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H A Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
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H A Dxlnx,zynqmp-reset.txt2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
9 Please also refer to reset.txt in this directory for common reset
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
14 "xlnx,versal-reset" for Versal platform
15 - #reset-cells: Specifies the number of cells needed to encode reset
27 zynqmp_reset: reset-controller {
28 compatible = "xlnx,zynqmp-reset";
29 #reset-cells = <1>;
34 Specifying reset lines connected to IP modules
37 Device nodes that need access to reset lines should
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H A Dsnps,axs10x-reset.txt1 Binding for the AXS10x reset controller
4 to control reset signals of selected peripherals. For example DW GMAC, etc...
6 represents up-to 32 reset lines.
11 This binding uses the common reset binding[1].
13 [1] Documentation/devicetree/bindings/reset/reset.txt
16 - compatible: should be "snps,axs10x-reset".
17 - reg: should always contain pair address - length: for creg reset
19 - #reset-cells: from common reset binding; Should always be set to 1.
22 reset: reset-controller@11220 {
23 compatible = "snps,axs10x-reset";
[all …]
H A Dimg,pistachio-reset.txt4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
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H A Duniphier-reset.txt1 UniPhier glue reset controller
4 Peripheral core reset in glue layer
7 Some peripheral core reset belongs to its own glue layer. Before using
8 this core reset, it is necessary to control the clocks and resets to enable
13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
14 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
15 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
16 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
17 "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
18 "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
[all …]
H A Dbrcm,brcmstb-reset.txt1 Broadcom STB SW_INIT-style reset controller
4 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
6 reset lines.
8 Please also refer to reset.txt in this directory for common reset
12 - compatible: should be brcm,brcmstb-reset
14 - #reset-cells: must be set to 1
18 reset: reset-controller@8404318 {
19 compatible = "brcm,brcmstb-reset";
21 #reset-cells = <1>;
25 resets = <&reset 26>;
[all …]
H A Dhisilicon,hi3660-reset.txt4 Please also refer to reset.txt in this directory for common reset
7 The reset controller registers are part of the system-ctl block on
12 "hisilicon,hi3660-reset" for HI3660
13 "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
14 - hisi,rst-syscon: phandle of the reset's syscon.
15 - #reset-cells : Specifies the number of cells needed to encode a
16 reset source. The type shall be a <u32> and the value shall be 2.
18 Cell #1 : offset of the reset assert control
22 Cell #2 : bit position of the reset in the reset control register
31 compatible = "hisilicon,hi3660-reset";
[all …]
H A Dnuvoton,npcm-reset.txt4 - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
6 - #reset-cells: must be set to 2
9 - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
10 NPCM7xx contain four software reset that represent numbers 1 to 4.
12 If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
16 compatible = "nuvoton,npcm750-reset";
18 #reset-cells = <2>;
19 nuvoton,sw-reset-number = <2>;
22 Specifying reset lines connected to IP NPCM7XX modules
32 The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.
/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Dt8103-pmgr.dtsi14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
73 #reset-cells = <0>;
82 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Dt8112-pmgr.dtsi14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
93 #reset-cells = <0>;
[all …]
H A Dt8015-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
58 #reset-cells = <0>;
67 #reset-cells = <0>;
76 #reset-cells = <0>;
84 #reset-cells = <0>;
93 #reset-cells = <0>;
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H A Dt8012-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
74 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Ds8001-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Dt8010-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Dt8011-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
92 #reset-cells = <0>;
[all …]
H A Ds800-0-3-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
48 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
83 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
H A Dt7001-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
66 #reset-cells = <0>;
75 #reset-cells = <0>;
84 #reset-cells = <0>;
92 #reset-cells = <0>;
[all …]
H A Ds5l8960x-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
58 #reset-cells = <0>;
67 #reset-cells = <0>;
76 #reset-cells = <0>;
85 #reset-cells = <0>;
93 #reset-cells = <0>;
[all …]
H A Dt7000-pmgr.dtsi12 #reset-cells = <0>;
21 #reset-cells = <0>;
30 #reset-cells = <0>;
39 #reset-cells = <0>;
47 #reset-cells = <0>;
56 #reset-cells = <0>;
65 #reset-cells = <0>;
74 #reset-cells = <0>;
82 #reset-cells = <0>;
90 #reset-cells = <0>;
[all …]
H A Dt600x-pmgr.dtsi13 #reset-cells = <0>;
22 #reset-cells = <0>;
31 #reset-cells = <0>;
40 #reset-cells = <0>;
49 #reset-cells = <0>;
58 #reset-cells = <0>;
67 #reset-cells = <0>;
76 #reset-cells = <0>;
84 #reset-cells = <0>;
92 #reset-cells = <0>;
[all …]

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