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Searched refs:reglist (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/diff/src/
H A Ddiff.c784 add_regexp (struct regexp_list *reglist, char const *pattern) in add_regexp() argument
787 char const *m = re_compile_pattern (pattern, patlen, reglist->buf); in add_regexp()
793 char *regexps = reglist->regexps; in add_regexp()
794 size_t len = reglist->len; in add_regexp()
795 bool multiple_regexps = reglist->multiple_regexps = regexps != 0; in add_regexp()
796 size_t newlen = reglist->len = len + 2 * multiple_regexps + patlen; in add_regexp()
797 size_t size = reglist->size; in add_regexp()
807 reglist->size = size; in add_regexp()
808 reglist->regexps = regexps = xrealloc (regexps, size); in add_regexp()
823 summarize_regexp_list (struct regexp_list *reglist) in summarize_regexp_list() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp501 createRegList(SmallVector<unsigned, 4> reglist, SMLoc S) { in createRegList()
512 for (unsigned i = 0; i < reglist.size(); i += 2) { in createRegList()
514 Op->RegList.List1From = reglist[i]; in createRegList()
515 Op->RegList.List1To = reglist[i + 1]; in createRegList()
517 Op->RegList.List2From = reglist[i]; in createRegList()
518 Op->RegList.List2To = reglist[i + 1]; in createRegList()
520 Op->RegList.List3From = reglist[i]; in createRegList()
521 Op->RegList.List3To = reglist[i + 1]; in createRegList()
523 Op->RegList.List4From = reglist[i]; in createRegList()
524 Op->RegList.List4To = reglist[i + 1]; in createRegList()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb.td826 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
841 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
844 let InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops);
854 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
867 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
872 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
882 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1751 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1753 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
H A DARMInstrThumb2.td2054 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2069 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2084 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2099 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2123 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2141 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2159 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2177 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3930 reglist:$regs, variable_ops),
3932 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
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H A DARMInstrInfo.td602 def reglist : Operand<i32> {
3487 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3496 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3507 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3516 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3527 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3536 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3547 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3556 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3586 reglist:$regs, variable_ops),
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td524 def reglist : Operand<i32> {
546 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
553 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
889 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
893 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td392 (ins reglist:$regs, variable_ops), "push16 $regs", []> {
404 (ins reglist:$regs, variable_ops), "pop16 $regs", []> {
H A DCSKYInstrInfo.td453 def reglist : Operand<iPTR> {
890 def PUSH32 : I_12_PP<0b11111, 0b00000, (outs), (ins reglist:$regs, variable_ops), "push32 $regs">;
893 def POP32 : I_12_PP<0b11110, 0b00000, (outs), (ins reglist:$regs, variable_ops), "pop32 $regs">;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2459 unsigned reglist = fieldFromInstruction(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
2537 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
6450 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | in DecodeVSCCLRM() local
6453 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { in DecodeVSCCLRM()
6457 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | in DecodeVSCCLRM() local
6460 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { in DecodeVSCCLRM()