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Searched refs:reglist (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/
H A DCSKYAsmParser.cpp501 createRegList(const SmallVector<MCRegister, 4> &reglist, SMLoc S) { in createRegList()
512 for (unsigned i = 0; i < reglist.size(); i += 2) { in createRegList()
514 Op->RegList.List1From = reglist[i]; in createRegList()
515 Op->RegList.List1To = reglist[i + 1]; in createRegList()
517 Op->RegList.List2From = reglist[i]; in createRegList()
518 Op->RegList.List2To = reglist[i + 1]; in createRegList()
520 Op->RegList.List3From = reglist[i]; in createRegList()
521 Op->RegList.List3To = reglist[i + 1]; in createRegList()
523 Op->RegList.List4From = reglist[i]; in createRegList()
524 Op->RegList.List4To = reglist[i + 1]; in createRegList()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZc.td61 def reglist : RISCVOp<OtherVT> {
156 : RVInst16<(outs), (ins reglist:$rlist, immtype:$stackadj),
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb.td825 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
840 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
843 let InOperandList = (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops);
853 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
866 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
871 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
881 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1753 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1755 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
H A DARMInstrThumb2.td2060 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2075 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2090 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2105 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2129 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2147 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2165 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2183 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3957 reglist:$regs, variable_ops),
3959 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
[all …]
H A DARMInstrInfo.td622 def reglist : Operand<i32> {
3508 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3517 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3528 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3537 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3548 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3557 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3568 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3577 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3607 reglist:$regs, variable_ops),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td524 def reglist : Operand<i32> {
546 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
553 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
889 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
893 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td392 (ins reglist:$regs, variable_ops), "push16 $regs", []> {
404 (ins reglist:$regs, variable_ops), "pop16 $regs", []> {
H A DCSKYInstrInfo.td453 def reglist : Operand<iPTR> {
890 def PUSH32 : I_12_PP<0b11111, 0b00000, (outs), (ins reglist:$regs, variable_ops), "push32 $regs">;
893 def POP32 : I_12_PP<0b11110, 0b00000, (outs), (ins reglist:$regs, variable_ops), "pop32 $regs">;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2465 unsigned reglist = fieldFromInstruction(Insn, 0, 16); in DecodeMemMultipleWritebackInstruction() local
2543 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) in DecodeMemMultipleWritebackInstruction()
6459 unsigned reglist = regs | (fieldFromInstruction(Insn, 12, 4) << 8) | in DecodeVSCCLRM() local
6461 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { in DecodeVSCCLRM()