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Searched refs:regclasses (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue()
359 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta()
363 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta()
H A DScheduleDAGRRList.cpp1774 for (const TargetRegisterClass *RC : TRI->regclasses()) in RegReductionPQBase()
2083 for (const TargetRegisterClass *RC : TRI->regclasses()) { in dumpRegPressure()
H A DTargetLowering.cpp5636 for (const TargetRegisterClass *RC : RI->regclasses()) { in getRegForInlineAsmConstraint()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp216 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
234 for (const TargetRegisterClass *RC : regclasses()) { in getMinimalPhysRegClassLLT()
262 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
H A DRegisterClassInfo.cpp205 for (const TargetRegisterClass *C : TRI->regclasses()) { in computePSetLimit()
H A DMachineCopyPropagation.cpp613 for (const TargetRegisterClass *RC : TRI->regclasses()) { in isForwardableRegClassCopy()
629 for (const TargetRegisterClass *RC : TRI->regclasses()) { in isForwardableRegClassCopy()
1221 for (const TargetRegisterClass *RC : TRI->regclasses()) { in EliminateSpillageCopies()
H A DRDFRegisters.cpp34 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
H A DMachinePipeliner.cpp1338 for (const TargetRegisterClass *TRC : TRI->regclasses()) { in computePressureSetLimit()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h441 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBlockRanges.cpp224 for (const TargetRegisterClass *RC : TRI.regclasses()) { in HexagonBlockRanges()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP400.td253 // FIXME: This could be better modeled by looking at the regclasses of the operands.
H A DRISCVSchedSiFiveP600.td815 // FIXME: This could be better modeled by looking at the regclasses of the operands.
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h808 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp619 for (const TargetRegisterClass *RC : regclasses()) { in getReservedRegs()
696 for (const TargetRegisterClass *RC : regclasses()) { in getReservedRegs()
710 for (const TargetRegisterClass *RC : regclasses()) { in getReservedRegs()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.cpp1070 for (const TargetRegisterClass *RC : TRI.regclasses()) { in MLocTracker()
1561 for (const auto *TRCI : TRI->regclasses()) in getValueForInstrRef()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td581 // FIXME: This could be better modeled by looking at the regclasses of the operands.