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Searched refs:regclass (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td2634 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
2635 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
2639 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
2640 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
2644 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
2645 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
2646 regclass:$dst4),
2653 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
2654 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
2656 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
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H A DNVPTXIntrinsics.td200 foreach regclass = ["i32", "f32"] in {
205 def : SHFL_INSTR<sync, mode, regclass, return_pred,
217 multiclass VOTE<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
218 def : NVPTXInst<(outs regclass:$dest), (ins Int1Regs:$pred),
220 [(set regclass:$dest, (IntOp Int1Regs:$pred))]>,
230 multiclass VOTE_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
231 def i : NVPTXInst<(outs regclass:$dest), (ins i32imm:$mask, Int1Regs:$pred),
233 [(set regclass:$dest, (IntOp imm:$mask, Int1Regs:$pred))]>,
235 def r : NVPTXInst<(outs regclass:$dest), (ins Int32Regs:$mask, Int1Regs:$pred),
237 [(set regclass:$dest, (IntOp Int32Regs:$mask, Int1Regs:$pred))]>,
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/freebsd/contrib/llvm-project/libunwind/src/
H A DUnwind-EHABI.cpp910 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Set() argument
915 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Set()
919 switch (regclass) { in _Unwind_VRS_Set()
978 _Unwind_VRS_RegClass regclass, uint32_t regno, in _Unwind_VRS_Get_Internal() argument
982 switch (regclass) { in _Unwind_VRS_Get_Internal()
1040 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Get() argument
1044 _Unwind_VRS_Get_Internal(context, regclass, regno, representation, in _Unwind_VRS_Get()
1048 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Get()
1055 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Pop() argument
1060 static_cast<void *>(context), regclass, discriminator, in _Unwind_VRS_Pop()
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/freebsd/contrib/llvm-project/libunwind/include/
H A Dunwind_arm_ehabi.h118 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
123 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
128 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
/freebsd/contrib/libcxxrt/
H A Dunwind-arm.h132 _Unwind_VRS_RegClass regclass,
137 _Unwind_VRS_RegClass regclass,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrCDE.td471 class CDE_VCX_RegisterOperandsTemplate<RegisterClass regclass>
473 let Rd = (outs regclass:$Vd);
474 let Rd_src = (ins regclass:$Vd_src);
475 let Rn = (ins regclass:$Vn);
476 let Rm = (ins regclass:$Vm);
479 class CDE_VCXQ_RegisterOperandsTemplate<RegisterClass regclass>
481 let Rd = (outs regclass:$Qd);
482 let Rd_src = (ins regclass:$Qd_src);
483 let Rn = (ins regclass:$Qn);
484 let Rm = (ins regclass:$Qm);
H A DARMInstrInfo.td2565 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
H A DARMInstrThumb2.td1523 // can be SP. We need another regclass (similar to rGPR) to represent
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td910 /// type that it doesn't know, and resolves the actual regclass to use by using
1021 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
1024 RegisterClass RegClass = regclass;
1265 let InOperandList = (ins unknown:$src, i32imm:$regclass);
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DTargetOpcodes.def101 // pair. Once it has been lowered to a MachineInstr, the regclass operand
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrUtils.td132 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
147 RegisterClass RegClass = regclass;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td267 // Condition code regclass.
H A DAArch64InstrFormats.td1153 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
1157 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
1183 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
1187 let MIOperandInfo = (ops regclass, shiftop);
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVPseudos.td140 class LMULInfo<int lmul, int oct, VReg regclass, VReg wregclass,
143 VReg vrclass = regclass;