| /freebsd/sys/dev/ath/ath_hal/ar9002/ |
| H A D | ar9285_cal.c | 54 uint32_t regList[][2] = { in ar9285_hw_pa_cal() local
71 for (i = 0; i < N(regList); i++) in ar9285_hw_pa_cal()
72 regList[i][1] = OS_REG_READ(ah, regList[i][0]); in ar9285_hw_pa_cal()
146 for (i = 0; i < N(regList); i++) in ar9285_hw_pa_cal()
147 OS_REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9285_hw_pa_cal()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetCallingConv.td | 112 class CCAssignToReg<list<Register> regList> : CCAction {
113 list<Register> RegList = regList;
119 class CCAssignToRegTuple<list<string> regList> : CCAction {
120 list<string> RegList = regList;
125 class CCAssignToRegWithShadow<list<Register> regList,
127 list<Register> RegList = regList;
153 /// CCIf<CCAssignToReg<regList>, CCAssignToStack<size, align>>.
154 class CCAssignToRegAndStack<list<Register> regList, int size, int align>
155 : CCAssignToReg<regList> {
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| H A D | Target.td | 261 dag regList, RegAltNameIndex idx = NoRegAltName>
295 dag MemberList = regList;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 370 auto regList = getRegList(); in isRegList() local
372 if (!isLegalRegList(regList.List1From, regList.List1To)) in isRegList()
374 if (!isLegalRegList(regList.List2From, regList.List2To)) in isRegList()
376 if (!isLegalRegList(regList.List3From, regList.List3To)) in isRegList()
378 if (!isLegalRegList(regList.List4From, regList.List4To)) in isRegList()
600 auto regList = getRegList(); in addRegListOperands() local
604 unsigned T = getListValue(regList.List1From, regList.List1To); in addRegListOperands()
608 T = getListValue(regList.List2From, regList.List2To); in addRegListOperands()
612 T = getListValue(regList.List3From, regList.List3To); in addRegListOperands()
616 T = getListValue(regList.List4From, regList.List4To); in addRegListOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.td | 17 class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
18 : RegisterClass <"NVPTX", regTypes, alignment, regList>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegisterInfo.td | 19 class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>
20 : RegisterClass<"WebAssembly", regTypes, alignment, regList>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.td | 873 SIRegisterTuples regList,
874 SIRegisterTuples ttmpList = regList,
877 defvar hasTTMP = !ne(regList, ttmpList);
883 def "" # sgprName : SIRegisterClass<"AMDGPU", regTypes, 32, (add regList)> {
937 class VRegClassBase<int numRegs, list<ValueType> regTypes, dag regList> :
938 SIRegisterClass<"AMDGPU", regTypes, 32, regList> {
949 multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> {
952 def "" : VRegClassBase<numRegs, regTypes, regList> {
957 def _Align2 : VRegClassBase<numRegs, regTypes, (decimate regList, 2)> {
983 multiclass ARegClass<int numRegs, list<ValueType> regTypes, dag regList> {
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.td | 36 // XPLINK. Otherwise, by default, XPLINK will use the regList ordering as well
38 dag regList, list<dag> altRegList = [regList],
47 def Bit : RegisterClass<"SystemZ", types, size, regList> {
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.td | 98 class MxRegClass<list<ValueType> regTypes, int alignment, dag regList>
99 : RegisterClass<"M68k", regTypes, alignment, regList>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchRegisterInfo.td | 100 class GPRRegisterClass<dag regList>
101 : RegisterClass<"LoongArch", [GRLenVT], 32, regList> {
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.td | 229 class RISCVRegisterClass<list<ValueType> regTypes, int align, dag regList>
230 : RegisterClass<"RISCV", regTypes, align, regList> {
240 class GPRRegisterClass<dag regList>
241 : RISCVRegisterClass<[XLenVT, XLenFVT, i32, i16], 32, regList> {
739 class VReg<list<ValueType> regTypes, dag regList, int Vlmul, int nf = 1>
742 regList> {
|