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Searched refs:regClass (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DFLATInstructions.td201 class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
204 RegisterOperand vdata_op = getLdStRegisterOperand<regClass>.ret> : FLAT_Pseudo<
243 multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
245 def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1>,
247 def _SADDR : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1>,
252 class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterClass regClass,
255 (outs regClass:$vdst),
258 !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
271 multiclass FLAT_Global_Load_AddTid_Pseudo<string opName, RegisterClass regClass,
273 def "" : FLAT_Global_Load_AddTid_Pseudo<opName, regClass, HasTiedOutput>,
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H A DSIRegisterInfo.td1127 class SrcRegOrImm9<RegisterClass regClass, string opWidth, string operandType,
1129 : RegOrImmOperand<regClass, operandType> {
1148 class SrcRegOrImmDeferred9<RegisterClass regClass, string opWidth,
1150 : RegOrImmOperand<regClass, operandType> {
1239 class SrcReg9<RegisterClass regClass, string width> : RegisterOperand<regClass> {
1281 class AVOperand<RegisterClass regClass, string decoder, string width>
1282 : RegisterOperand<regClass> {
1326 class AVSrcOperand<RegisterClass regClass, string width>
1327 : AVOperand<regClass, "decodeSrcAV10", width>;
1333 class AVDstOperand<RegisterClass regClass, string width>
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H A DSIWholeQuadMode.cpp1454 const TargetRegisterClass *regClass = in lowerCopyInstrs() local
1456 if (TRI->isVGPRClass(regClass)) { in lowerCopyInstrs()
1457 const unsigned MovOp = TII->getMovOpcode(regClass); in lowerCopyInstrs()
H A DSIInstrInfo.cpp9615 const TargetRegisterClass *regClass = in getInstructionUniformity() local
9617 return RI.isSGPRClass(regClass) ? InstructionUniformity::AlwaysUniform in getInstructionUniformity()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCTargetDesc.cpp122 int16_t regClass = Desc.operands()[OpNo].RegClass; in getRegNumForOperand() local
123 switch (regClass) { in getRegNumForOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td127 class MemOperand<RegisterClass regClass> : RegisterOperand<regClass>{