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Searched refs:reg (Results 1 – 25 of 5059) sorted by relevance

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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_config.c53 uint32_t reg; in al_udma_axi_set() local
57 reg = al_reg_read32(&axi_regs->cfg_2); in al_udma_axi_set()
58 reg &= ~UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK; in al_udma_axi_set()
59 reg |= axi->arb_promotion; in al_udma_axi_set()
60 al_reg_write32(&axi_regs->cfg_2, reg); in al_udma_axi_set()
62 reg = al_reg_read32(&axi_regs->endian_cfg); in al_udma_axi_set()
64 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN; in al_udma_axi_set()
66 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN; in al_udma_axi_set()
69 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA; in al_udma_axi_set()
71 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA; in al_udma_axi_set()
[all …]
H A Dal_hal_reg_utils.h66 #define AL_REG_FIELD_GET(reg, mask, shift) (((reg) & (mask)) >> (shift)) argument
69 #define AL_REG_FIELD_SET(reg, mask, shift, val) \ argument
70 (reg) = \
71 (((reg) & (~(mask))) | \
75 #define AL_REG_FIELD_SET_64(reg, mask, shift, val) \ argument
76 ((reg) = \
77 (((reg) & (~(mask))) | \
81 #define AL_REG_BIT_GET(reg, shift) \ argument
82 AL_REG_FIELD_GET(reg, AL_BIT(shift), shift)
88 #define AL_REG_BIT_VAL_SET(reg, shift, val) \ argument
[all …]
/freebsd/sys/dev/qcom_tlmm/
H A Dqcom_tlmm_ipq4018_hw.c71 uint32_t reg; in qcom_tlmm_ipq4018_hw_pin_set_function() local
78 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin, in qcom_tlmm_ipq4018_hw_pin_set_function()
80 reg &= ~(QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK in qcom_tlmm_ipq4018_hw_pin_set_function()
82 reg |= (function & QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK) in qcom_tlmm_ipq4018_hw_pin_set_function()
85 QCOM_TLMM_IPQ4018_REG_PIN_CONTROL), reg); in qcom_tlmm_ipq4018_hw_pin_set_function()
99 uint32_t reg; in qcom_tlmm_ipq4018_hw_pin_get_function() local
107 reg = GPIO_READ(sc, QCOM_TLMM_IPQ4018_REG_PIN(pin, in qcom_tlmm_ipq4018_hw_pin_get_function()
109 reg = reg >> QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT; in qcom_tlmm_ipq4018_hw_pin_get_function()
110 reg &= QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK; in qcom_tlmm_ipq4018_hw_pin_get_function()
111 *function = reg; in qcom_tlmm_ipq4018_hw_pin_get_function()
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_dcb_82599.c125 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() local
134 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82599()
135 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); in ixgbe_dcb_config_rx_arbiter_82599()
143 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599()
145 reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); in ixgbe_dcb_config_rx_arbiter_82599()
147 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); in ixgbe_dcb_config_rx_arbiter_82599()
153 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82599()
155 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; in ixgbe_dcb_config_rx_arbiter_82599()
158 reg |= IXGBE_RTRPT4C_LSP; in ixgbe_dcb_config_rx_arbiter_82599()
160 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); in ixgbe_dcb_config_rx_arbiter_82599()
[all …]
H A Dixgbe_dcb_82598.c115 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
120 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
121 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
123 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
125 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
127 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
129 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
131 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
138 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
141 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_ccm.c91 uint32_t reg; in ccm_init_gates() local
94 reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA; in ccm_init_gates()
95 WR4(sc, CCM_CCGR0, reg); in ccm_init_gates()
98 reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 | in ccm_init_gates()
100 WR4(sc, CCM_CCGR1, reg); in ccm_init_gates()
103 reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM | in ccm_init_gates()
107 WR4(sc, CCM_CCGR2, reg); in ccm_init_gates()
110 reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG | in ccm_init_gates()
112 WR4(sc, CCM_CCGR3, reg); in ccm_init_gates()
115 reg = CCGR4_PL301_MX6QFAST1_S133 | in ccm_init_gates()
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c459 bus_size_t reg; member
476 .reg = r, \
545 uint32_t reg; in uphy_pex_enable() local
570 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
571 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0); in uphy_pex_enable()
572 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136); in uphy_pex_enable()
573 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
575 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in uphy_pex_enable()
576 reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0); in uphy_pex_enable()
577 reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a); in uphy_pex_enable()
[all …]
H A Dtegra210_clk_pll.c600 uint32_t reg; in pll_enable() local
603 RD4(sc, sc->base_reg, &reg); in pll_enable()
605 reg &= ~PLL_BASE_BYPASS; in pll_enable()
606 reg |= PLL_BASE_ENABLE; in pll_enable()
607 WR4(sc, sc->base_reg, reg); in pll_enable()
614 uint32_t reg; in pll_disable() local
616 RD4(sc, sc->base_reg, &reg); in pll_disable()
618 reg |= PLL_BASE_BYPASS; in pll_disable()
619 reg &= ~PLL_BASE_ENABLE; in pll_disable()
620 WR4(sc, sc->base_reg, reg); in pll_disable()
[all …]
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c415 uint32_t reg; in pll_enable() local
417 RD4(sc, sc->base_reg, &reg); in pll_enable()
419 reg &= ~PLL_BASE_BYPASS; in pll_enable()
420 reg |= PLL_BASE_ENABLE; in pll_enable()
421 WR4(sc, sc->base_reg, reg); in pll_enable()
428 uint32_t reg; in pll_disable() local
430 RD4(sc, sc->base_reg, &reg); in pll_disable()
432 reg |= PLL_BASE_BYPASS; in pll_disable()
433 reg &= ~PLL_BASE_ENABLE; in pll_disable()
434 WR4(sc, sc->base_reg, reg); in pll_disable()
[all …]
H A Dtegra124_xusbpadctl.c291 bus_size_t reg; member
307 .reg = r, \
366 uint32_t reg; in usb3_port_init() local
368 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); in usb3_port_init()
370 reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx); in usb3_port_init()
372 reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx); in usb3_port_init()
373 reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0); in usb3_port_init()
374 reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion); in usb3_port_init()
375 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); in usb3_port_init()
377 reg = RD4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx)); in usb3_port_init()
[all …]
/freebsd/sys/arm/altera/socfpga/
H A Dsocfpga_a10_manager.c148 int reg; in fpga_open() local
153 reg = READ4(sc, IMGCFG_STAT); in fpga_open()
154 if ((reg & F2S_USERMODE) == 0) { in fpga_open()
160 reg = READ4(sc, IMGCFG_STAT); in fpga_open()
161 msel = (reg & F2S_MSEL_M) >> F2S_MSEL_S; in fpga_open()
173 reg = READ4(sc, IMGCFG_CTRL_02); in fpga_open()
174 reg &= ~(CTRL_02_CDRATIO_M); in fpga_open()
175 WRITE4(sc, IMGCFG_CTRL_02, reg); in fpga_open()
177 reg = READ4(sc, IMGCFG_CTRL_02); in fpga_open()
178 reg &= ~CTRL_02_CFGWIDTH_32; in fpga_open()
[all …]
/freebsd/sys/contrib/dev/athk/
H A Dregd.c26 static int __ath_regd_init(struct ath_regulatory *reg);
117 static bool dynamic_country_user_possible(struct ath_regulatory *reg) in dynamic_country_user_possible() argument
122 switch (reg->country_code) { in dynamic_country_user_possible()
189 static bool ath_reg_dyn_country_user_allow(struct ath_regulatory *reg) in ath_reg_dyn_country_user_allow() argument
193 if (!dynamic_country_user_possible(reg)) in ath_reg_dyn_country_user_allow()
205 static u16 ath_regd_get_eepromRD(struct ath_regulatory *reg) in ath_regd_get_eepromRD() argument
207 return reg->current_rd & ~WORLDWIDE_ROAMING_FLAG; in ath_regd_get_eepromRD()
210 bool ath_is_world_regd(struct ath_regulatory *reg) in ath_is_world_regd() argument
212 return is_wwr_sku(ath_regd_get_eepromRD(reg)); in ath_is_world_regd()
223 ieee80211_regdomain *ath_world_regdomain(struct ath_regulatory *reg) in ath_world_regdomain() argument
[all …]
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-facebook-fuji.dts213 <0>, /* device reg=<1> does not exist */
221 reg = <2>;
240 reg = <0x70>;
246 reg = <0>;
250 reg = <0x10>;
260 reg = <1>;
266 reg = <2>;
272 reg = <3>;
278 reg = <4>;
284 reg
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H A Daspeed-bmc-facebook-cmm.dts335 reg = <0x77>;
342 reg = <0>;
348 reg = <0x70>;
354 reg = <0>;
359 reg = <1>;
364 reg = <2>;
369 reg = <3>;
374 reg = <4>;
379 reg = <5>;
384 reg
[all...]
H A Daspeed-bmc-ibm-everest.dts175 reg = <0x80000000 0x40000000>;
185 reg = <0xb3d00000 0x100000>;
190 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
201 reg = <0xb4000000 0x04000000>; /* 64M */
208 reg = <0xbf000000 0x01000000>; /* 16M */
327 reg = <0x51>;
332 reg = <0x62>;
371 reg = <0x54>;
376 reg = <0x68>;
381 reg
[all...]
H A Dibm-power9-dual.dtsi6 reg = <0 0>;
13 reg = <0x1000 0x400>;
18 reg = <0x1800 0x400>;
23 reg = <0>;
27 reg = <1>;
31 reg = <2>;
35 reg = <3>;
39 reg = <4>;
43 reg = <5>;
47 reg = <6>;
[all …]
H A Daspeed-bmc-ibm-rainier.dts40 reg = <0x80000000 0x40000000>;
50 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
61 reg = <0xb4000000 0x04000000>; /* 64M */
68 reg = <0xbf000000 0x01000000>; /* 16M */
86 reg = <0>;
92 reg = <1>;
98 reg = <2>;
104 reg = <3>;
263 reg = <0x51>;
268 reg
[all...]
H A Daspeed-bmc-opp-swift.dts17 reg = <0x80000000 0x20000000>;
27 reg = <0x98000000 0x04000000>; /* 64M */
235 reg = < 0 0x60000 >;
239 reg = < 0x60000 0x20000 >;
243 reg = < 0x80000 0x7F80000>;
259 reg = < 0 0x60000 >;
263 reg = < 0x60000 0x20000 >;
267 reg = < 0x80000 0x7F80000>;
342 reg = <0x52>;
348 reg = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra186-p2771-0000.dts27 reg = <0>;
35 reg = <1>;
53 reg = <0>;
61 reg = <1>;
79 reg = <0>;
87 reg = <1>;
105 reg = <0>;
113 reg = <1>;
131 reg = <0>;
139 reg = <1>;
[all …]
H A Dtegra234-p3737-0000+p3701-0000.dts186 reg = <0x0>;
198 reg = <0x08>;
209 reg = <0>;
218 reg = <0>;
226 reg = <1>;
237 reg = <1>;
246 reg = <0>;
254 reg = <1>;
H A Dtegra194-p3509-0000.dtsi23 reg = <0>;
31 reg = <1>;
49 reg = <0>;
57 reg = <1>;
75 reg = <0>;
84 reg = <1>;
102 reg = <0>;
110 reg = <1>;
127 reg = <0>;
135 reg = <1>;
[all …]
H A Dtegra194-p2972-0000.dts28 reg = <0>;
36 reg = <1>;
54 reg = <0>;
62 reg = <1>;
80 reg = <0>;
88 reg = <1>;
106 reg = <0>;
114 reg = <1>;
132 reg = <0>;
140 reg = <1>;
[all …]
H A Dtegra210-p2371-2180.dts42 reg = <0>;
55 reg = <0x2c>;
82 reg = <0x57>;
132 reg = <0>;
140 reg = <1>;
158 reg = <0>;
166 reg = <1>;
184 reg = <0>;
192 reg = <1>;
210 reg
[all...]
/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_hw_port.c76 uint32_t reg; in ar40xx_hw_port_init() local
113 reg = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH in ar40xx_hw_port_init()
115 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg); in ar40xx_hw_port_init()
117 reg = AR40XX_PORT_LOOKUP_LEARN; in ar40xx_hw_port_init()
118 reg |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S; in ar40xx_hw_port_init()
119 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg); in ar40xx_hw_port_init()
151 uint32_t reg; in ar40xx_hw_port_link_up() local
158 reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(port)); in ar40xx_hw_port_link_up()
159 reg |= AR40XX_PORT_AUTO_LINK_EN; in ar40xx_hw_port_link_up()
160 AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), reg); in ar40xx_hw_port_link_up()
[all …]
/freebsd/sys/arm/arm/
H A Dmachdep_kdb.c46 u_int reg; in DB_SHOW_COMMAND() local
48 reg = cp15_midr_get(); in DB_SHOW_COMMAND()
49 db_printf("Cpu ID: 0x%08x\n", reg); in DB_SHOW_COMMAND()
50 reg = cp15_ctr_get(); in DB_SHOW_COMMAND()
51 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); in DB_SHOW_COMMAND()
53 reg = cp15_sctlr_get(); in DB_SHOW_COMMAND()
54 db_printf("Ctrl: 0x%08x\n",reg); in DB_SHOW_COMMAND()
55 reg = cp15_actlr_get(); in DB_SHOW_COMMAND()
56 db_printf("Aux Ctrl: 0x%08x\n",reg); in DB_SHOW_COMMAND()
58 reg = cp15_id_pfr0_get(); in DB_SHOW_COMMAND()
[all …]

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