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Searched refs:refdiv (Results 1 – 13 of 13) sorted by relevance

/freebsd/sys/dev/clk/rockchip/
H A Drk3399_pmucru.c141 .refdiv = 1,
149 .refdiv = 1,
157 .refdiv = 1,
165 .refdiv = 1,
173 .refdiv = 1,
181 .refdiv = 1,
189 .refdiv = 1,
197 .refdiv = 1,
205 .refdiv = 1,
213 .refdiv = 1,
[all …]
H A Drk_clk_pll.c160 uint32_t refdiv, fbdiv, postdiv; in rk3066_clk_pll_recalc() local
185 refdiv = (raw0 & RK3066_CLK_PLL_REFDIV_MASK) >> in rk3066_clk_pll_recalc()
187 refdiv += 1; in rk3066_clk_pll_recalc()
196 rate /= refdiv; in rk3066_clk_pll_recalc()
243 reg |= (rates->refdiv - 1)<< RK3066_CLK_PLL_REFDIV_SHIFT; in rk3066_clk_pll_set_freq()
381 uint32_t dsmpd, refdiv, fbdiv; in rk3328_clk_pll_recalc() local
397 refdiv = (raw2 & RK3328_CLK_PLL_REFDIV_MASK) >> RK3328_CLK_PLL_REFDIV_SHIFT; in rk3328_clk_pll_recalc()
404 rate = *freq * fbdiv / refdiv; in rk3328_clk_pll_recalc()
409 frac_rate = *freq * frac / refdiv; in rk3328_clk_pll_recalc()
466 (rates->refdiv << RK3328_CLK_PLL_REFDIV_SHIFT); in rk3328_clk_pll_set_freq()
[all …]
H A Drk_clk_pll.h35 uint32_t refdiv; member
H A Drk3288_cru.c365 .refdiv = _ref, \
H A Drk3328_cru.c573 .refdiv = _ref, \
H A Drk3399_cru.c550 .refdiv = _ref, \
H A Drk3568_cru.c58 .refdiv = _ref, \
/freebsd/sys/arm/mv/clk/
H A Da37x0_tbg_pll.c47 struct a37x0_tbg_pll_reg_def refdiv; member
56 uint32_t vcodiv, fbdiv, refdiv; in a37x0_tbg_pll_recalc_freq() local
68 RD4(clk, sc->refdiv.offset, &val); in a37x0_tbg_pll_recalc_freq()
69 refdiv = (val >> sc->refdiv.shift) & sc->refdiv.mask; in a37x0_tbg_pll_recalc_freq()
74 if (refdiv == 0) in a37x0_tbg_pll_recalc_freq()
75 refdiv = 1; in a37x0_tbg_pll_recalc_freq()
77 *freq = *freq * (fbdiv / refdiv) * 4; in a37x0_tbg_pll_recalc_freq()
119 sc->refdiv = clkdef->refdiv; in a37x0_tbg_pll_clk_register()
H A Da37x0_tbg.c169 def.refdiv.offset = TBG_CTRL7; in a37x0_tbg_attach()
170 def.refdiv.shift = tbg[i].refdiv_shift; in a37x0_tbg_attach()
173 def.vcodiv.mask = def.refdiv.mask = def.fbdiv.mask = TBG_MASK; in a37x0_tbg_attach()
H A Da37x0_tbg_pll.h44 struct a37x0_tbg_pll_reg_def refdiv; member
/freebsd/sys/contrib/dev/athk/ath10k/
H A Dhw.c491 .refdiv = 0,
499 .refdiv = 0,
507 .refdiv = 0,
515 .refdiv = 0,
523 .refdiv = 0,
531 .refdiv = 0,
539 .refdiv = 0,
547 .refdiv = 0,
828 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | in ath10k_hw_qca6174_enable_pll_clock()
H A Dhw.h509 u32 refdiv; member
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_reset.c1511 u_int32_t refdiv; in ar9300_init_pll() local
1521 refdiv = 1; in ar9300_init_pll()
1525 refdiv = 3; in ar9300_init_pll()
1536 refdiv = 5; in ar9300_init_pll()
1540 refdiv = 1; in ar9300_init_pll()
1565 ((refdiv << 27) | (pll2_divint << 18) | pll2_divfrac)); in ar9300_init_pll()