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Searched refs:rdmsr (Results 1 – 25 of 57) sorted by relevance

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/freebsd/sys/amd64/amd64/
H A Dinitcpu.c104 wrmsr(MSR_DE_CFG, rdmsr(MSR_DE_CFG) | in init_amd()
116 msr = rdmsr(MSR_NB_CFG1); in init_amd()
130 msr = rdmsr(0xc001102a); in init_amd()
144 msr = rdmsr(MSR_LS_CFG); in init_amd()
154 msr = rdmsr(MSR_DE_CFG); in init_amd()
159 msr = rdmsr(MSR_LS_CFG); in init_amd()
164 msr = rdmsr(0xc0011028); in init_amd()
169 msr = rdmsr(MSR_LS_CFG); in init_amd()
224 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); in init_via()
237 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28)); in init_via()
[all …]
H A Dcpu_switch.S104 rdmsr
345 rdmsr
349 rdmsr
353 rdmsr
357 rdmsr
361 rdmsr
365 rdmsr
369 rdmsr
373 rdmsr
H A Dmpboot.S111 rdmsr
121 rdmsr
H A Dlocore.S146 rdmsr /* to safer tweaking LA57 */
156 rdmsr
H A Dexception.S667 rdmsr
684 rdmsr
740 rdmsr
808 rdmsr
825 rdmsr
852 rdmsr
1016 rdmsr
1033 rdmsr
1195 rdmsr
1202 rdmsr
/freebsd/sys/amd64/vmm/intel/
H A Dvmx_msr.c62 return (rdmsr(MSR_VMX_BASIC) & 0xffffffff); in vmx_revision()
88 true_ctls_avail = (rdmsr(MSR_VMX_BASIC) & (1UL << 55)) != 0; in vmx_set_ctlreg()
90 val = rdmsr(ctl_reg); in vmx_set_ctlreg()
92 trueval = rdmsr(true_ctl_reg); /* step c */ in vmx_set_ctlreg()
252 host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR); in vmx_msr_init()
253 host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR); in vmx_msr_init()
254 host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR); in vmx_msr_init()
255 host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK); in vmx_msr_init()
260 misc_enable = rdmsr(MSR_IA32_MISC_ENABLE); in vmx_msr_init()
369 vcpu->guest_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR); in vmx_msr_guest_exit()
[all …]
/freebsd/sys/i386/i386/
H A Dinitcpu.c401 fcr = rdmsr(0x0107); in init_winchip()
497 apicbase = rdmsr(MSR_APICBASE); in init_ppro()
514 apicbase = rdmsr(MSR_APICBASE); in ppro_reenable_apic()
537 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); in init_mendocino()
594 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); in init_via()
609 wrmsr(0x1107, rdmsr(0x1107) | fcr); in init_via()
621 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); in init_transmeta()
691 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); in initializecpu()
735 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); in initializecpu()
766 msr = rdmsr(MSR_EFER) | EFER_NXE; in initializecpu()
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H A Dgeode.c128 a = rdmsr(0x5140000c); in cs5536_led_func()
214 a = rdmsr(0x5140000d); in cs5536_watchdog()
227 m = rdmsr(0x51400029); in cs5536_watchdog()
350 printf("MFGPT bar: %jx\n", rdmsr(0x5140000d)); in geode_probe()
H A Dlongrun.c94 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); in tmx86_get_longrun_mode()
97 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01; in tmx86_get_longrun_mode()
142 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN); in tmx86_set_longrun_mode()
150 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS); in tmx86_set_longrun_mode()
H A Dk6_mem.c112 reg = rdmsr(UWCCR); in k6_mrinit()
165 reg = rdmsr(UWCCR); in k6_mrset()
/freebsd/sys/dev/hyperv/vmbus/x86/
H A Dhyperv_x86.c84 return rdmsr(MSR_HV_TIME_REF_COUNT); in hyperv_get_timecount()
91 return (rdmsr(MSR_HV_TIME_REF_COUNT)); in hyperv_tc64_rdmsr()
117 hc_orig = rdmsr(MSR_HV_HYPERCALL); in hypercall_page_setup()
131 hc = rdmsr(MSR_HV_HYPERCALL); in hypercall_page_setup()
146 hc = rdmsr(MSR_HV_HYPERCALL); in hypercall_disable()
H A Dhyperv_machdep.h36 #define RDMSR(msr) rdmsr(msr)
/freebsd/sys/x86/x86/
H A Dmca.c664 status = rdmsr(mca_msr_ops.status(bank)); in mca_check_status()
679 rec->mr_addr = rdmsr(mca_msr_ops.addr(bank)); in mca_check_status()
682 rec->mr_misc = rdmsr(mca_msr_ops.misc(bank)); in mca_check_status()
685 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP); in mca_check_status()
686 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS); in mca_check_status()
844 ctl = rdmsr(MSR_MC_CTL2(bank)); in cmci_update()
869 misc = rdmsr(mca_msr_ops.misc(bank)); in amd_thresholding_update()
902 mcg_cap = rdmsr(MSR_MCG_CAP); in mca_scan()
1196 ctl = rdmsr(MSR_MC_CTL2(i)); in cmci_monitor()
1205 ctl = rdmsr(MSR_MC_CTL2(i)); in cmci_monitor()
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H A Dx86_mem.c210 msrv = rdmsr(msr); in x86_mrfetch()
222 msrv = rdmsr(msr); in x86_mrfetch()
234 msrv = rdmsr(msr); in x86_mrfetch()
249 msrv = rdmsr(msr); in x86_mrfetch()
253 msrv = rdmsr(msr + 1); in x86_mrfetch()
343 wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE); in x86_mrstoreone()
350 omsrv = rdmsr(msr); in x86_mrstoreone()
362 omsrv = rdmsr(msr); in x86_mrstoreone()
374 omsrv = rdmsr(msr); in x86_mrstoreone()
389 omsrv = rdmsr(msr); in x86_mrstoreone()
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H A Ducode.c118 orev = rdmsr(MSR_BIOS_SIGN) >> 32; in ucode_intel_load()
139 nrev = rdmsr(MSR_BIOS_SIGN) >> 32; in ucode_intel_load()
193 platformid = rdmsr(MSR_IA32_PLATFORM_ID); in ucode_intel_match()
241 orev = rdmsr(MSR_BIOS_SIGN); in ucode_amd_load()
259 nrev = rdmsr(MSR_BIOS_SIGN); in ucode_amd_load()
278 revision = rdmsr(MSR_BIOS_SIGN); in ucode_amd_match()
H A Didentcpu.c1279 rdmsr(0x1002); /* Cyrix CPU generates fault. */ in identblue()
1516 msr = rdmsr(MSR_IA32_MISC_ENABLE); in fix_cpuid()
1533 msr = rdmsr(MSR_EXTFEATURES); in fix_cpuid()
1593 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); in identify_cpu2()
1896 amd_whcr = rdmsr(0xc0000082); in print_AMD_info()
1908 amd_whcr = rdmsr(0xc0000082); in print_AMD_info()
2334 msr = rdmsr(MSR_VM_CR); in print_svm_info()
2461 val = rdmsr(true_msr); in vmx_settable()
2463 val = rdmsr(msr); in vmx_settable()
2477 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); in print_vmx_info()
[all …]
/freebsd/sys/amd64/vmm/amd/
H A Dsvm_msr.c66 host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR); in svm_msr_init()
67 host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR); in svm_msr_init()
68 host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR); in svm_msr_init()
69 host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK); in svm_msr_init()
/freebsd/sys/x86/cpufreq/
H A Dhwpstate_amd.c200 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); in hwpstate_goto_pstate()
242 msr = rdmsr(MSR_AMD_10H_11H_STATUS); in hwpstate_set()
292 msr = rdmsr(MSR_AMD_10H_11H_STATUS); in hwpstate_settings()
418 msr = rdmsr(MSR_AMD_10H_11H_LIMIT);
457 msr = rdmsr(MSR_AMD_10H_11H_LIMIT); in hwpstate_get_info_from_msr()
461 msr = rdmsr(MSR_AMD_10H_11H_CONFIG + i); in hwpstate_get_info_from_msr()
H A Dpowernow.c277 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn7_setfidvid()
285 ctl = rdmsr(MSR_AMDK7_FIDVID_CTL) & PN7_CTR_FIDCHRATIO; in pn7_setfidvid()
316 *status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn8_read_pending_wait()
486 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn_get()
652 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn_decode_pst()
822 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn_decode_acpi()
891 status = rdmsr(MSR_AMDK7_FIDVID_STATUS); in pn_probe()
/freebsd/sys/amd64/vmm/
H A Dvmm_host.c47 vmm_host_efer = rdmsr(MSR_EFER); in vmm_host_state_init()
48 vmm_host_pat = rdmsr(MSR_PAT); in vmm_host_state_init()
/freebsd/sys/dev/hwpmc/
H A Dhwpmc_core.c153 wrmsr(MSR_DEBUGCTLMSR, rdmsr(MSR_DEBUGCTLMSR) | 0x1000); in core_pcpu_init()
436 cc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), in iaf_start_pmc()
437 cc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); in iaf_start_pmc()
462 cc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), in iaf_stop_pmc()
463 cc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); in iaf_stop_pmc()
493 (uintmax_t) rdmsr(IAF_CTRL), in iaf_write_pmc()
1078 intrstatus = rdmsr(IA_GLOBAL_STATUS); in core2_intr()
1171 cpu, (uintmax_t) rdmsr(IAF_CTRL), in core2_intr()
1172 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), in core2_intr()
1173 (uintmax_t) rdmsr(IA_GLOBAL_STATUS)); in core2_intr()
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H A Dhwpmc_uncore.c272 tmp = rdmsr(UCF_CTR0 + ri); in ucf_read_pmc()
321 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), in ucf_start_pmc()
322 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); in ucf_start_pmc()
352 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), in ucf_stop_pmc()
353 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); in ucf_stop_pmc()
378 cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL)); in ucf_write_pmc()
581 tmp = rdmsr(UCP_PMC0 + ri); in ucp_read_pmc()
/freebsd/sys/dev/hyperv/vmbus/amd64/
H A Dhyperv_machdep.c165 return (rdmsr(MSR_HV_TIME_REF_COUNT)); \
217 orig = rdmsr(MSR_HV_REFERENCE_TSC); in hyperv_tsc_tcinit()
/freebsd/sys/compat/linuxkpi/common/include/asm/
H A Dmsr.h32 #define rdmsrl(msr, val) ((val) = rdmsr(msr))
/freebsd/sys/dev/agp/
H A Dagp_nvidia.c389 base = rdmsr(IORR_BASE0 + 2 * iorr_addr); in nvidia_init_iorr()
390 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr); in nvidia_init_iorr()
410 sys = rdmsr(SYSCFG); in nvidia_init_iorr()

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