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Searched refs:printReg (Results 1 – 25 of 110) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp137 << " " << printReg(r, TRI)); in AggressiveAntiDepBreaker()
211 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe()
315 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
330 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
333 LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" in HandleLastUse()
370 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in PrescanInstruction()
391 << printReg(AliasReg, TRI) << ")"); in PrescanInstruction()
466 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in ScanInstruction()
502 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI)); in ScanInstruction()
505 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in ScanInstruction()
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H A DRegAllocFast.cpp584 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " in " in spill()
585 << printReg(AssignedReg, TRI)); in spill()
644 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " in reload()
645 << printReg(PhysReg, TRI) << '\n'); in reload()
775 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':'); in freePhysReg()
789 LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n'); in freePhysReg()
808 << printReg(PhysReg, TRI) << '\n'); in calcSpillCost()
861 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to " in assignVirtToPhysReg()
862 << printReg(PhysReg, TRI) << '\n'); in assignVirtToPhysReg()
916 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg) in allocVirtReg()
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H A DLiveRegMatrix.cpp112 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to " in assign()
113 << printReg(PhysReg, TRI) << ':'); in assign()
130 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg(), TRI) in unassign()
131 << " from " << printReg(PhysReg, TRI) << ':'); in unassign()
H A DFixupStatepointCallerSaved.cpp154 << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI) in performCopyPropagation()
259 << printReg(Reg, &TRI) << " at " in getFrameIndex()
290 << printReg(Reg, &TRI) << " at landing pad " in getFrameIndex()
392 LLVM_DEBUG(dbgs() << "Will spill " << printReg(Reg, &TRI) << " at index " in findRegistersToSpill()
412 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, &TRI) << " to FI " << FI in spillRegisters()
457 LLVM_DEBUG(dbgs() << "Reloading " << printReg(Reg, &TRI) << " from FI " in insertReloads()
H A DRegAllocGreedy.cpp555 LLVM_DEBUG(dbgs() << "missed hint " << printReg(PhysHint, TRI) << '\n'); in tryAssign()
579 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " in tryAssign()
604 << printReg(FromReg, TRI) << " to " in canReassign()
605 << printReg(Reg, TRI) << '\n'); in canReassign()
623 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) in evictInterference()
699 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " in canAllocatePhysReg()
700 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in canAllocatePhysReg()
1262 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n"); in calculateRegionSplitCostAroundReg()
1265 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) in calculateRegionSplitCostAroundReg()
1273 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; in calculateRegionSplitCostAroundReg()
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H A DMachineRegisterInfo.cpp214 << printReg(Reg, getTargetRegisterInfo()) << "...\n"; in clearVirtRegs()
232 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
241 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
247 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
253 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
H A DRegAllocBase.cpp205 LLVM_DEBUG(dbgs() << "Enqueuing " << printReg(Reg, TRI) << '\n'); in enqueue()
208 LLVM_DEBUG(dbgs() << "Not enqueueing " << printReg(Reg, TRI) in enqueue()
H A DRegisterCoalescer.cpp695 LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg(), TRI)); in adjustCopiesBackFrom()
2127 << printReg(CP.getSrcReg(), TRI) << " with " in joinCopy()
2128 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'); in joinCopy()
2149 dbgs() << printReg(CP.getDstReg()) << " in " in joinCopy()
2151 << printReg(CP.getSrcReg()) << " in " in joinCopy()
2154 dbgs() << printReg(CP.getSrcReg(), TRI) << " in " in joinCopy()
2155 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; in joinCopy()
2265 dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) in joinCopy()
2266 << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; in joinCopy()
2269 dbgs() << printReg(CP.getDstReg(), TRI); in joinCopy()
[all …]
H A DAllocationOrder.cpp43 dbgs() << ' ' << printReg(Hint, TRI); in create()
H A DRenameIndependentSubregs.cpp143 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses() in INITIALIZE_PASS_DEPENDENCY()
145 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:"); in INITIALIZE_PASS_DEPENDENCY()
151 LLVM_DEBUG(dbgs() << ' ' << printReg(NewVReg)); in INITIALIZE_PASS_DEPENDENCY()
H A DInitUndef.cpp163 dbgs() << printReg(Reg, nullptr) in handleSubReg()
209 << printReg(MO.getReg()) << '\n'); in fixupIllOperand()
H A DTargetRegisterInfo.cpp91 dbgs() << "Error: Super register " << printReg(SR, this) in checkAllSuperRegsMarked()
92 << " of reserved register " << printReg(Reg, this) in checkAllSuperRegsMarked()
107 Printable printReg(Register Reg, const TargetRegisterInfo *TRI, in printReg() function
727 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegNumbering.cpp75 LLVM_DEBUG(dbgs() << "Arg VReg " << printReg(MI.getOperand(0).getReg()) in runOnMachineFunction()
94 LLVM_DEBUG(dbgs() << "VReg " << printReg(VReg) << " -> WAReg " in runOnMachineFunction()
100 LLVM_DEBUG(dbgs() << "VReg " << printReg(VReg) << " -> WAReg " << CurReg in runOnMachineFunction()
H A DWebAssemblyRegColoring.cpp314 LLVM_DEBUG(dbgs() << "Assigning vreg " << printReg(LI->reg()) << " to vreg " in runOnMachineFunction()
315 << printReg(New) << "\n"); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFixCortexA57AES1742098Pass.cpp307 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
323 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
331 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
349 << printReg(MOp.getReg(), TRI) << "\n"); in analyzeMF()
365 << printReg(MOp.getReg(), TRI) << ": " << *DefMI); in analyzeMF()
399 LLVM_DEBUG(dbgs() << "Inserting VORRq of " << printReg(RegToFixup, TRI) in insertAESFixup()
H A DMVETPAndVPTOptimisationsPass.cpp780 << "Replacing all uses of '" << printReg(Result) in ReduceOldVCCRValueUses()
781 << "' with '" << printReg(LastVPNOTResult) << "'\n"); in ReduceOldVCCRValueUses()
790 LLVM_DEBUG(dbgs() << "Replacing use of '" << printReg(VCCRValue) in ReduceOldVCCRValueUses()
791 << "' with '" << printReg(LastVPNOTResult) in ReduceOldVCCRValueUses()
804 << printReg(OppositeVCCRValue) << "' with '" in ReduceOldVCCRValueUses()
805 << printReg(LastVPNOTResult) << " for instr: "; in ReduceOldVCCRValueUses()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURewriteAGPRCopyMFMA.cpp154 << " Dst=[" << printReg(VReg) << " => " in run()
155 << printReg(PhysReg, &TRI) << "], Src2=[" in run()
156 << printReg(Src2->getReg(), &TRI) << " => " in run()
157 << printReg(Src2PhysReg, &TRI) << "]: " << *CopySrcMI; in run()
200 LLVM_DEBUG(dbgs() << "Other uses of " << printReg(Src2->getReg(), &TRI) in run()
H A DSIOptimizeVGPRLiveRange.cpp264 LLVM_DEBUG(dbgs() << "Excluding " << printReg(MOReg, TRI) in collectCandidateRegisters()
293 LLVM_DEBUG(dbgs() << "Excluding " << printReg(Reg, TRI) in collectCandidateRegisters()
394 << printReg(MOReg, TRI, 0, MRI) << '\n'); in collectWaterfallCandidateRegisters()
398 << printReg(MOReg, TRI, 0, MRI) << '\n'); in collectWaterfallCandidateRegisters()
510 LLVM_DEBUG(dbgs() << "Optimizing " << printReg(Reg, TRI) << '\n'); in optimizeLiveRange()
562 LLVM_DEBUG(dbgs() << "Optimizing " << printReg(Reg, TRI) << '\n'); in optimizeWaterfallLiveRange()
H A DGCNNSAReassign.cpp326 << " " << llvm::printReg((VRM->getPhys(LI->reg())), TRI); in run()
366 << llvm::printReg((VRM->getPhys(Intervals.front()->reg())), TRI) in run()
368 << llvm::printReg((VRM->getPhys(Intervals.back()->reg())), TRI) in run()
H A DGCNRewritePartialRegUses.cpp402 LLVM_DEBUG(dbgs() << "Try to rewrite partial reg " << printReg(Reg, TRI) in rewriteReg()
412 LLVM_DEBUG(dbgs() << " Success " << printReg(Reg, TRI) << ':' in rewriteReg()
414 << printReg(NewReg, TRI) << ':' in rewriteReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp541 LLVM_DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n"); in colorChain()
615 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction()
635 << printReg(AccumReg, TRI) << " in MI " << *MI); in scanInstruction()
661 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
689 LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI) in maybeKillChain()
701 << printReg(I->first, TRI) << "\n"); in maybeKillChain()
H A DAArch64PBQPRegAlloc.cpp242 LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) in addInterChainConstraint()
243 << " to " << printReg(Rd, TRI) << '\n'); in addInterChainConstraint()
248 LLVM_DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI) in addInterChainConstraint()
335 LLVM_DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at "; in apply()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp194 OS << ' ' << printReg(R, P.TRI); in operator <<()
435 OS << printReg(*I, P.TRI); in operator <<()
488 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) in operator <<()
578 dbgs() << " " << printReg(I.first, HRI) << ":\n"; in dump_map()
779 dbgs() << __func__ << ": " << printReg(VR, HRI) in findRecordInsertForms()
844 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; in findRecordInsertForms()
849 dbgs() << " (" << printReg(J.first, HRI) << ",@" << J.second << ')'; in findRecordInsertForms()
894 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) in findRecordInsertForms()
895 << ',' << printReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms()
1519 dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n"; in runOnMachineFunction()
H A DHexagonGenPredicate.cpp57 return OS << printReg(PR.Reg.Reg, &PR.TRI, PR.Reg.SubReg); in operator <<()
201 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.Reg, TRI, Reg.SubReg) in processPredicateGPR()
207 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.Reg, TRI, Reg.SubReg) in processPredicateGPR()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.cpp69 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in replaceFrameIndex()
70 << " for FrameReg=" << printReg(FrameReg, TRI) in replaceFrameIndex()

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