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Searched refs:postdiv1 (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/dev/clk/rockchip/
H A Drk3399_pmucru.c143 .postdiv1 = 1,
151 .postdiv1 = 1,
159 .postdiv1 = 1,
167 .postdiv1 = 1,
175 .postdiv1 = 1,
183 .postdiv1 = 1,
191 .postdiv1 = 1,
199 .postdiv1 = 1,
207 .postdiv1 = 1,
215 .postdiv1 = 1,
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H A Drk_clk_pll.c240 reg |= (rates->postdiv1 - 1) << RK3066_CLK_PLL_POSTDIV_SHIFT; in rk3066_clk_pll_set_freq()
382 uint32_t postdiv1, postdiv2, frac; in rk3328_clk_pll_recalc() local
394 postdiv1 = (raw1 & RK3328_CLK_PLL_POSTDIV1_MASK) >> RK3328_CLK_PLL_POSTDIV1_SHIFT; in rk3328_clk_pll_recalc()
413 *freq = rate / postdiv1 / postdiv2; in rk3328_clk_pll_recalc()
457 reg = (rates->postdiv1 << RK3328_CLK_PLL_POSTDIV1_SHIFT) | in rk3328_clk_pll_set_freq()
589 uint32_t postdiv1, postdiv2, fracdiv; in rk3399_clk_pll_recalc() local
625 postdiv1 = (con2 & RK3399_CLK_PLL_POSTDIV1_MASK) in rk3399_clk_pll_recalc()
639 dprintf("postdiv1: %d\n", postdiv1); in rk3399_clk_pll_recalc()
656 *freq = foutvco / postdiv1 / postdiv2; in rk3399_clk_pll_recalc()
702 reg = rates->postdiv1 << RK3399_CLK_PLL_POSTDIV1_SHIFT; in rk3399_clk_pll_set_freq()
H A Drk_clk_pll.h37 uint32_t postdiv1; member
H A Drk3288_cru.c367 .postdiv1 = _post, \
H A Drk3328_cru.c575 .postdiv1 = _post1, \
H A Drk3399_cru.c552 .postdiv1 = _post1, \
H A Drk3568_cru.c60 .postdiv1 = _post1, \