xref: /freebsd/sys/dev/firmware/xilinx/pm_defs.h (revision 9e88711f28dc9afa7d68ae8dd027d2399a2a290b)
1 /*
2  * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 /* ZynqMP power management enums and defines */
8 
9 #ifndef PM_DEFS_H
10 #define PM_DEFS_H
11 
12 /*********************************************************************
13  * Macro definitions
14  ********************************************************************/
15 
16 /*
17  * Version number is a 32bit value, like:
18  * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
19  */
20 #define PM_VERSION_MAJOR	1U
21 #define PM_VERSION_MINOR	1U
22 
23 #define PM_VERSION	((PM_VERSION_MAJOR << 16U) | PM_VERSION_MINOR)
24 
25 /**
26  * PM API versions
27  */
28 /* Expected version of firmware APIs */
29 #define FW_API_BASE_VERSION		(1U)
30 /* Expected version of firmware API for feature check */
31 #define FW_API_VERSION_2		(2U)
32 /* Version of APIs implemented in ATF */
33 #define ATF_API_BASE_VERSION		(1U)
34 
35 /* Capabilities for RAM */
36 #define PM_CAP_ACCESS	0x1U
37 #define PM_CAP_CONTEXT	0x2U
38 
39 #define MAX_LATENCY	(~0U)
40 #define MAX_QOS		100U
41 
42 /* State arguments of the self suspend */
43 #define PM_STATE_CPU_IDLE		0x0U
44 #define PM_STATE_SUSPEND_TO_RAM		0xFU
45 
46 /* APU processor states */
47 #define PM_PROC_STATE_FORCEDOFF		0U
48 #define PM_PROC_STATE_ACTIVE		1U
49 #define PM_PROC_STATE_SLEEP		2U
50 #define PM_PROC_STATE_SUSPENDING	3U
51 
52 #define EM_FUNID_NUM_MASK    0xF0000U
53 
54 #define PM_GET_CALLBACK_DATA		0xa01
55 #define PM_SET_SUSPEND_MODE		0xa02
56 #define PM_GET_TRUSTZONE_VERSION	0xa03
57 
58 /*********************************************************************
59  * Enum definitions
60  ********************************************************************/
61 
62 enum pm_api_id {
63 	/* Miscellaneous API functions: */
64 	PM_GET_API_VERSION = 1, /* Do not change or move */
65 	PM_SET_CONFIGURATION,
66 	PM_GET_NODE_STATUS,
67 	PM_GET_OP_CHARACTERISTIC,
68 	PM_REGISTER_NOTIFIER,
69 	/* API for suspending of PUs: */
70 	PM_REQ_SUSPEND,
71 	PM_SELF_SUSPEND,
72 	PM_FORCE_POWERDOWN,
73 	PM_ABORT_SUSPEND,
74 	PM_REQ_WAKEUP,
75 	PM_SET_WAKEUP_SOURCE,
76 	PM_SYSTEM_SHUTDOWN,
77 	/* API for managing PM slaves: */
78 	PM_REQ_NODE,
79 	PM_RELEASE_NODE,
80 	PM_SET_REQUIREMENT,
81 	PM_SET_MAX_LATENCY,
82 	/* Direct control API functions: */
83 	PM_RESET_ASSERT,
84 	PM_RESET_GET_STATUS,
85 	PM_MMIO_WRITE,
86 	PM_MMIO_READ,
87 	PM_INIT_FINALIZE,
88 	PM_FPGA_LOAD,
89 	PM_FPGA_GET_STATUS,
90 	PM_GET_CHIPID,
91 	PM_SECURE_RSA_AES,
92 	PM_SECURE_SHA,
93 	PM_SECURE_RSA,
94 	PM_PINCTRL_REQUEST,
95 	PM_PINCTRL_RELEASE,
96 	PM_PINCTRL_GET_FUNCTION,
97 	PM_PINCTRL_SET_FUNCTION,
98 	PM_PINCTRL_CONFIG_PARAM_GET,
99 	PM_PINCTRL_CONFIG_PARAM_SET,
100 	PM_IOCTL,
101 	/* API to query information from firmware */
102 	PM_QUERY_DATA,
103 	/* Clock control API functions */
104 	PM_CLOCK_ENABLE,
105 	PM_CLOCK_DISABLE,
106 	PM_CLOCK_GETSTATE,
107 	PM_CLOCK_SETDIVIDER,
108 	PM_CLOCK_GETDIVIDER,
109 	PM_CLOCK_SETRATE,
110 	PM_CLOCK_GETRATE,
111 	PM_CLOCK_SETPARENT,
112 	PM_CLOCK_GETPARENT,
113 	PM_SECURE_IMAGE,
114 	/* FPGA PL Readback */
115 	PM_FPGA_READ,
116 	PM_SECURE_AES,
117 	/* PLL control API functions */
118 	PM_PLL_SET_PARAMETER,
119 	PM_PLL_GET_PARAMETER,
120 	PM_PLL_SET_MODE,
121 	PM_PLL_GET_MODE,
122 	/* PM Register Access API */
123 	PM_REGISTER_ACCESS,
124 	PM_EFUSE_ACCESS,
125 	PM_FPGA_GET_VERSION,
126 	PM_FPGA_GET_FEATURE_LIST,
127 	PM_FEATURE_CHECK = 63,
128 	PM_API_MAX
129 };
130 
131 enum pm_query_id {
132 	PM_QID_INVALID = 0,
133 	PM_QID_CLOCK_GET_NAME,
134 	PM_QID_CLOCK_GET_TOPOLOGY,
135 	PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
136 	PM_QID_CLOCK_GET_PARENTS,
137 	PM_QID_CLOCK_GET_ATTRIBUTES,
138 	PM_QID_PINCTRL_GET_NUM_PINS,
139 	PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
140 	PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
141 	PM_QID_PINCTRL_GET_FUNCTION_NAME,
142 	PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
143 	PM_QID_PINCTRL_GET_PIN_GROUPS,
144 	PM_QID_CLOCK_GET_NUM_CLOCKS,
145 	PM_QID_CLOCK_GET_MAX_DIVISOR,
146 };
147 
148 enum pm_node_id {
149 	NODE_UNKNOWN = 0,
150 	NODE_APU,
151 	NODE_APU_0,
152 	NODE_APU_1,
153 	NODE_APU_2,
154 	NODE_APU_3,
155 	NODE_RPU,
156 	NODE_RPU_0,
157 	NODE_RPU_1,
158 	NODE_PLD,
159 	NODE_FPD,
160 	NODE_OCM_BANK_0,
161 	NODE_OCM_BANK_1,
162 	NODE_OCM_BANK_2,
163 	NODE_OCM_BANK_3,
164 	NODE_TCM_0_A,
165 	NODE_TCM_0_B,
166 	NODE_TCM_1_A,
167 	NODE_TCM_1_B,
168 	NODE_L2,
169 	NODE_GPU_PP_0,
170 	NODE_GPU_PP_1,
171 	NODE_USB_0,
172 	NODE_USB_1,
173 	NODE_TTC_0,
174 	NODE_TTC_1,
175 	NODE_TTC_2,
176 	NODE_TTC_3,
177 	NODE_SATA,
178 	NODE_ETH_0,
179 	NODE_ETH_1,
180 	NODE_ETH_2,
181 	NODE_ETH_3,
182 	NODE_UART_0,
183 	NODE_UART_1,
184 	NODE_SPI_0,
185 	NODE_SPI_1,
186 	NODE_I2C_0,
187 	NODE_I2C_1,
188 	NODE_SD_0,
189 	NODE_SD_1,
190 	NODE_DP,
191 	NODE_GDMA,
192 	NODE_ADMA,
193 	NODE_NAND,
194 	NODE_QSPI,
195 	NODE_GPIO,
196 	NODE_CAN_0,
197 	NODE_CAN_1,
198 	NODE_EXTERN,
199 	NODE_APLL,
200 	NODE_VPLL,
201 	NODE_DPLL,
202 	NODE_RPLL,
203 	NODE_IOPLL,
204 	NODE_DDR,
205 	NODE_IPI_APU,
206 	NODE_IPI_RPU_0,
207 	NODE_GPU,
208 	NODE_PCIE,
209 	NODE_PCAP,
210 	NODE_RTC,
211 	NODE_LPD,
212 	NODE_VCU,
213 	NODE_IPI_RPU_1,
214 	NODE_IPI_PL_0,
215 	NODE_IPI_PL_1,
216 	NODE_IPI_PL_2,
217 	NODE_IPI_PL_3,
218 	NODE_PL,
219 	NODE_GEM_TSU,
220 	NODE_SWDT_0,
221 	NODE_SWDT_1,
222 	NODE_CSU,
223 	NODE_PJTAG,
224 	NODE_TRACE,
225 	NODE_TESTSCAN,
226 	NODE_PMU,
227 	NODE_MAX,
228 };
229 
230 enum pm_request_ack {
231 	REQ_ACK_NO = 1,
232 	REQ_ACK_BLOCKING,
233 	REQ_ACK_NON_BLOCKING,
234 };
235 
236 enum pm_abort_reason {
237 	ABORT_REASON_WKUP_EVENT = 100,
238 	ABORT_REASON_PU_BUSY,
239 	ABORT_REASON_NO_PWRDN,
240 	ABORT_REASON_UNKNOWN,
241 };
242 
243 enum pm_suspend_reason {
244 	SUSPEND_REASON_PU_REQ = 201,
245 	SUSPEND_REASON_ALERT,
246 	SUSPEND_REASON_SYS_SHUTDOWN,
247 };
248 
249 enum pm_ram_state {
250 	PM_RAM_STATE_OFF = 1,
251 	PM_RAM_STATE_RETENTION,
252 	PM_RAM_STATE_ON,
253 };
254 
255 enum pm_opchar_type {
256 	PM_OPCHAR_TYPE_POWER = 1,
257 	PM_OPCHAR_TYPE_TEMP,
258 	PM_OPCHAR_TYPE_LATENCY,
259 };
260 
261 /**
262  * @PM_RET_SUCCESS:		success
263  * @PM_RET_ERROR_ARGS:		illegal arguments provided (deprecated)
264  * @PM_RET_ERROR_NOTSUPPORTED:	feature not supported  (deprecated)
265  * @PM_RET_ERROR_NOT_ENABLED:	feature is not enabled
266  * @PM_RET_ERROR_INTERNAL:	internal error
267  * @PM_RET_ERROR_CONFLICT:	conflict
268  * @PM_RET_ERROR_ACCESS:	access rights violation
269  * @PM_RET_ERROR_INVALID_NODE:	invalid node
270  * @PM_RET_ERROR_DOUBLE_REQ:	duplicate request for same node
271  * @PM_RET_ERROR_ABORT_SUSPEND:	suspend procedure has been aborted
272  * @PM_RET_ERROR_TIMEOUT:	timeout in communication with PMU
273  * @PM_RET_ERROR_NODE_USED:	node is already in use
274  */
275 enum pm_ret_status {
276 	PM_RET_SUCCESS = (0U),
277 	PM_RET_ERROR_ARGS = (1U),
278 	PM_RET_ERROR_NOTSUPPORTED = (4U),
279 	PM_RET_ERROR_NOT_ENABLED = (29U),
280 	PM_RET_ERROR_INTERNAL = (2000U),
281 	PM_RET_ERROR_CONFLICT = (2001U),
282 	PM_RET_ERROR_ACCESS = (2002U),
283 	PM_RET_ERROR_INVALID_NODE = (2003U),
284 	PM_RET_ERROR_DOUBLE_REQ = (2004U),
285 	PM_RET_ERROR_ABORT_SUSPEND = (2005U),
286 	PM_RET_ERROR_TIMEOUT = (2006U),
287 	PM_RET_ERROR_NODE_USED = (2007U),
288 	PM_RET_ERROR_NO_FEATURE = (2008U)
289 };
290 
291 /**
292  * @PM_INITIAL_BOOT:	boot is a fresh system startup
293  * @PM_RESUME:		boot is a resume
294  * @PM_BOOT_ERROR:	error, boot cause cannot be identified
295  */
296 enum pm_boot_status {
297 	PM_INITIAL_BOOT,
298 	PM_RESUME,
299 	PM_BOOT_ERROR,
300 };
301 
302 /**
303  * @PMF_SHUTDOWN_TYPE_SHUTDOWN:		shutdown
304  * @PMF_SHUTDOWN_TYPE_RESET:		reset/reboot
305  * @PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY:	set the shutdown/reboot scope
306  */
307 enum pm_shutdown_type {
308 	PMF_SHUTDOWN_TYPE_SHUTDOWN,
309 	PMF_SHUTDOWN_TYPE_RESET,
310 	PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY,
311 };
312 
313 /**
314  * @PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM:	shutdown/reboot APU subsystem only
315  * @PMF_SHUTDOWN_SUBTYPE_PS_ONLY:	shutdown/reboot entire PS (but not PL)
316  * @PMF_SHUTDOWN_SUBTYPE_SYSTEM:	shutdown/reboot entire system
317  */
318 enum pm_shutdown_subtype {
319 	PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
320 	PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
321 	PMF_SHUTDOWN_SUBTYPE_SYSTEM,
322 };
323 
324 /**
325  * @PM_PLL_PARAM_DIV2:		Enable for divide by 2 function inside the PLL
326  * @PM_PLL_PARAM_FBDIV:		Feedback divisor integer portion for the PLL
327  * @PM_PLL_PARAM_DATA:		Feedback divisor fractional portion for the PLL
328  * @PM_PLL_PARAM_PRE_SRC:	Clock source for PLL input
329  * @PM_PLL_PARAM_POST_SRC:	Clock source for PLL Bypass mode
330  * @PM_PLL_PARAM_LOCK_DLY:	Lock circuit config settings for lock windowsize
331  * @PM_PLL_PARAM_LOCK_CNT:	Lock circuit counter setting
332  * @PM_PLL_PARAM_LFHF:		PLL loop filter high frequency capacitor control
333  * @PM_PLL_PARAM_CP:		PLL charge pump control
334  * @PM_PLL_PARAM_RES:		PLL loop filter resistor control
335  */
336 enum pm_pll_param {
337 	PM_PLL_PARAM_DIV2,
338 	PM_PLL_PARAM_FBDIV,
339 	PM_PLL_PARAM_DATA,
340 	PM_PLL_PARAM_PRE_SRC,
341 	PM_PLL_PARAM_POST_SRC,
342 	PM_PLL_PARAM_LOCK_DLY,
343 	PM_PLL_PARAM_LOCK_CNT,
344 	PM_PLL_PARAM_LFHF,
345 	PM_PLL_PARAM_CP,
346 	PM_PLL_PARAM_RES,
347 	PM_PLL_PARAM_MAX,
348 };
349 
350 /**
351  * @PM_PLL_MODE_RESET:		PLL is in reset (not locked)
352  * @PM_PLL_MODE_INTEGER:	PLL is locked in integer mode
353  * @PM_PLL_MODE_FRACTIONAL:	PLL is locked in fractional mode
354  */
355 enum pm_pll_mode {
356 	PM_PLL_MODE_RESET,
357 	PM_PLL_MODE_INTEGER,
358 	PM_PLL_MODE_FRACTIONAL,
359 	PM_PLL_MODE_MAX,
360 };
361 
362 /**
363  * @PM_CLOCK_DIV0_ID:		Clock divider 0
364  * @PM_CLOCK_DIV1_ID:		Clock divider 1
365  */
366 enum pm_clock_div_id {
367 	PM_CLOCK_DIV0_ID,
368 	PM_CLOCK_DIV1_ID,
369 };
370 
371 /**
372  * EM API IDs
373  */
374 enum em_api_id {
375 	EM_SET_ACTION = 1,
376 	EM_REMOVE_ACTION,
377 	EM_SEND_ERRORS,
378 };
379 
380 #endif /* PM_DEFS_H */
381