Searched refs:pll_cml (Results 1 – 2 of 2) sorted by relevance
563 uint32_t pll_cml = 13; in plle_enable() local593 reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT; in plle_enable()
755 uint32_t pll_cml = 14; in plle_enable() local784 reg = set_divisors(sc, reg, pll_m, pll_n, pll_cml); in plle_enable()