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Searched refs:pll0 (Results 1 – 21 of 21) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/clock/ti/davinci/
H A Dpll.txt9 - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
14 - for "ti,da850-pll0", shall be "clksrc", "extclksrc"
20 This property is only valid when compatible = "ti,da850-pll0".
42 This child node is only valid when compatible = "ti,da850-pll0".
56 pll0: clock-controller@11000 {
57 compatible = "ti,da850-pll0";
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqoriq-clock.txt160 pll0: pll0@800 {
165 clock-output-names = "pll0", "pll0-div2";
180 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
181 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
189 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
190 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
H A Drenesas,r8a73a4-cpg-clocks.txt17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
H A Drenesas,sh73a0-cpg-clocks.txt19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
H A Dsilabs,si5351.txt82 /* connect xtal input as source of pll0 and pll1 */
88 * - pll0 as clock source of multisynth0
90 * - multisynth0 can change pll0
/freebsd/sys/contrib/device-tree/Bindings/clock/st/
H A Dst,clkgen-pll.txt12 "st,clkgen-pll0"
13 "st,clkgen-pll0-a0"
14 "st,clkgen-pll0-c0"
H A Dst,clkgen.txt51 compatible = "st,clkgen-pll0";
/freebsd/sys/contrib/device-tree/src/arc/
H A Dabilis_tb10x.dtsi48 pll0: oscillator { label
51 clock-output-names = "pll0";
56 clocks = <&pll0>;
62 clocks = <&pll0>;
H A Dabilis_tb100.dtsi17 pll0: oscillator { label
H A Dabilis_tb101.dtsi17 pll0: oscillator { label
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih410-clock.dtsi75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
H A Dstih418-clock.dtsi75 compatible = "st,clkgen-pll0-a0";
94 clk_s_c0_pll0: clk-s-c0-pll0 {
96 compatible = "st,clkgen-pll0-c0";
H A Dstih407-clock.dtsi70 compatible = "st,clkgen-pll0-a0";
89 clk_s_c0_pll0: clk-s-c0-pll0 {
91 compatible = "st,clkgen-pll0-c0";
/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_hdmi.c129 uint32_t pll0; member
141 .pll0 = 0x01003010,
150 .pll0 = 0x01003110,
159 .pll0 = 0x01003310,
168 .pll0 = 0x01003F10,
650 WR4(sc, HDMI_NV_PDISP_SOR_PLL0, tmds->pll0); in tmds_init()
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_subr.c69 static uint32_t bhnd_pmu5_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m);
71 static uint32_t bhnd_pmu6_4706_clock(struct bhnd_pmu_query *sc, u_int pll0,
2219 bhnd_pmu5_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m) in bhnd_pmu5_clock() argument
2227 if ((pll0 & 3) || (pll0 > BHND_PMU4716_MAINPLL_PLL0)) { in bhnd_pmu5_clock()
2228 PMU_LOG(sc, "%s: Bad pll0: %d", __func__, pll0); in bhnd_pmu5_clock()
2249 pll0 + BHND_PMU5_PLL_P1P2_OFF); in bhnd_pmu5_clock()
2258 pll0 + BHND_PMU5_PLL_M14_OFF); in bhnd_pmu5_clock()
2267 pll0 + BHND_PMU5_PLL_NM5_OFF); in bhnd_pmu5_clock()
2285 bhnd_pmu6_4706_clock(struct bhnd_pmu_query *sc, u_int pll0, u_int m) in bhnd_pmu6_4706_clock() argument
2292 pll0 + BHND_PMU6_4706_PROCPLL_OFF); in bhnd_pmu6_4706_clock()
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Ddove-cubox.dts101 /* connect xtal input as source of pll0 and pll1 */
/freebsd/sys/contrib/device-tree/src/arm/ti/davinci/
H A Dda850.dtsi135 pll0: clock-controller@11000 { label
136 compatible = "ti,da850-pll0";
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e-main.dtsi711 wiz0_pll0_refclk: pll0-refclk {
771 wiz1_pll0_refclk: pll0-refclk {
831 wiz2_pll0_refclk: pll0-refclk {
891 wiz3_pll0_refclk: pll0-refclk {
H A Dk3-j7200-main.dtsi696 wiz0_pll0_refclk: pll0-refclk {
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dsh73a0.dtsi651 clock-output-names = "main", "pll0", "pll1", "pll2",
H A Dr8a73a4.dtsi514 clock-output-names = "main", "pll0", "pll1", "pll2",