1 /*-
2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
6 * All rights reserved.
7 * Copyright (c) 2020-2025 The FreeBSD Foundation
8 *
9 * Portions of this software were developed by Björn Zeeb
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
17 * disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33 #ifndef _LINUXKPI_LINUX_PCI_H_
34 #define _LINUXKPI_LINUX_PCI_H_
35
36 #define CONFIG_PCI_MSI
37
38 #include <linux/types.h>
39 #include <linux/device/driver.h>
40
41 #include <sys/param.h>
42 #include <sys/bus.h>
43 #include <sys/module.h>
44 #include <sys/nv.h>
45 #include <sys/pciio.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pci_private.h>
49
50 #include <machine/resource.h>
51
52 #include <linux/list.h>
53 #include <linux/dmapool.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/compiler.h>
56 #include <linux/errno.h>
57 #include <asm/atomic.h>
58 #include <asm/memtype.h>
59 #include <linux/device.h>
60 #include <linux/pci_ids.h>
61 #include <linux/pm.h>
62
63 /*
64 * <linux/ioport.h> should be included here, like Linux, but we can't have that
65 * because Linux `struct resource` definition would conflict with FreeBSD
66 * native definition.
67 *
68 * At least the amdgpu DRM driver (amdgpu_isp.c at the time of this writing)
69 * relies on this indirect include to get the definition of Linux `struct
70 * resource`. As a workaround, we include <linux/ioport.h> from
71 * <linux/mfd/core.h>.
72 */
73
74 #include <linux/kernel.h> /* pr_debug */
75
76 struct pci_device_id {
77 uint32_t vendor;
78 uint32_t device;
79 uint32_t subvendor;
80 uint32_t subdevice;
81 uint32_t class;
82 uint32_t class_mask;
83 uintptr_t driver_data;
84 };
85
86 #define MODULE_DEVICE_TABLE_BUS_pci(_bus, _table) \
87 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \
88 _bus, lkpi_ ## _table, _table, nitems(_table) - 1)
89
90 #define PCI_ANY_ID -1U
91
92 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
93 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
94 #define PCI_FUNC(devfn) ((devfn) & 0x07)
95 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
96 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn))
97
98 #define PCI_VDEVICE(_vendor, _device) \
99 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
100 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
101 #define PCI_DEVICE(_vendor, _device) \
102 .vendor = (_vendor), .device = (_device), \
103 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
104
105 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
106
107 #define PCI_STD_NUM_BARS 6
108 #define PCI_BASE_ADDRESS_0 PCIR_BARS
109 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64
110 #define PCI_VENDOR_ID PCIR_VENDOR
111 #define PCI_DEVICE_ID PCIR_DEVICE
112 #define PCI_COMMAND PCIR_COMMAND
113 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS
114 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN
115 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1
116 #define PCI_SECONDARY_BUS PCIR_SECBUS_1
117 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1
118 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1
119 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
120 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
121 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S
122 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1
123 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC
124 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */
125 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
126 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
127 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
128 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
129 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
130 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
131 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
132 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
133 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
134 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
135 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
136 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
137 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
138 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
139 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE
140 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE
141 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
142 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
143 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
144 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
145 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
146 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
147 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
148 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
149 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
150 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
151 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
152 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED
153 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
154 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
155 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
156 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */
157 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */
158 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */
159 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */
160 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
161 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
162 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
163 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
164 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */
165 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */
166 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */
167 #define PCI_EXP_LNKCTL2_TLS 0x000f
168 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
169 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
170 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
171 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
172 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
173 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */
174 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
175 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
176
177 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR
178 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH
179 #define PCI_MSI_FLAGS PCIR_MSI_CTRL
180 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE
181 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL
182 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE
183
184 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
185 #define PCI_EXP_DEVSTA_TRPND 0x0020
186
187 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
188 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
189 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
190
191 enum pci_bus_speed {
192 PCI_SPEED_UNKNOWN = -1,
193 PCIE_SPEED_2_5GT,
194 PCIE_SPEED_5_0GT,
195 PCIE_SPEED_8_0GT,
196 PCIE_SPEED_16_0GT,
197 PCIE_SPEED_32_0GT,
198 PCIE_SPEED_64_0GT,
199 };
200
201 enum pcie_link_width {
202 PCIE_LNK_WIDTH_RESRV = 0x00,
203 PCIE_LNK_X1 = 0x01,
204 PCIE_LNK_X2 = 0x02,
205 PCIE_LNK_X4 = 0x04,
206 PCIE_LNK_X8 = 0x08,
207 PCIE_LNK_X12 = 0x0c,
208 PCIE_LNK_X16 = 0x10,
209 PCIE_LNK_X32 = 0x20,
210 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
211 };
212
213 #define PCIE_LINK_STATE_L0S 0x00000001
214 #define PCIE_LINK_STATE_L1 0x00000002
215 #define PCIE_LINK_STATE_CLKPM 0x00000004
216
217 typedef int pci_power_t;
218
219 #define PCI_D0 PCI_POWERSTATE_D0
220 #define PCI_D1 PCI_POWERSTATE_D1
221 #define PCI_D2 PCI_POWERSTATE_D2
222 #define PCI_D3hot PCI_POWERSTATE_D3_HOT
223 #define PCI_D3cold PCI_POWERSTATE_D3_COLD
224
225 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
226
227 extern const char *pci_power_names[6];
228
229 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS
230 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS
231 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD
232 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID
233
234 #define PCI_EXT_CAP_ID_ERR PCIZ_AER
235 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM
236
237 #define PCI_L1SS_CTL1 0x8
238 #define PCI_L1SS_CTL1_L1SS_MASK 0xf
239
240 #define PCI_IRQ_INTX 0x01
241 #define PCI_IRQ_MSI 0x02
242 #define PCI_IRQ_MSIX 0x04
243 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX)
244
245 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000)
246 #define PCI_IRQ_LEGACY PCI_IRQ_INTX
247 #endif
248
249 /*
250 * Linux PCI code uses `PCI_SET_ERROR_RESPONSE()` to indicate to the caller of
251 * a `pci_read_*()` function that the read failed. An example of failure is
252 * whether the device was disconnected. It is a bit weird because Linux
253 * `pci_read_*()` can return an error value, as the read value is stored in a
254 * integer passed by pointer.
255 *
256 * We don't set PCI_ERROR_RESPONSE anywhere as of this commit, but the DRM
257 * drivers started to use `PCI_POSSIBLE_ERROR()`.
258 */
259 #define PCI_ERROR_RESPONSE (~0ULL)
260 #define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE))
261 #define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE))
262
263 struct pci_dev;
264
265 struct pci_driver {
266 struct list_head node;
267 char *name;
268 const struct pci_device_id *id_table;
269 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
270 void (*remove)(struct pci_dev *dev);
271 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
272 int (*resume) (struct pci_dev *dev); /* Device woken up */
273 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
274 driver_t bsddriver;
275 devclass_t bsdclass;
276 struct device_driver driver;
277 const struct pci_error_handlers *err_handler;
278 bool isdrm;
279 int bsd_probe_return;
280 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs,
281 const nvlist_t *pf_config);
282 void (*bsd_iov_uninit)(device_t dev);
283 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum,
284 const nvlist_t *vf_config);
285 };
286
287 struct pci_bus {
288 struct pci_dev *self;
289 /* struct pci_bus *parent */
290 int domain;
291 int number;
292 };
293
294 extern struct list_head pci_drivers;
295 extern struct list_head pci_devices;
296 extern spinlock_t pci_lock;
297
298 #define __devexit_p(x) x
299
300 #define module_pci_driver(_drv) \
301 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver)
302
303 struct msi_msg {
304 uint32_t data;
305 };
306
307 struct pci_msi_desc {
308 struct {
309 bool is_64;
310 } msi_attrib;
311 };
312
313 struct msi_desc {
314 struct msi_msg msg;
315 struct pci_msi_desc pci;
316 };
317
318 struct msix_entry {
319 int entry;
320 int vector;
321 };
322
323 /*
324 * If we find drivers accessing this from multiple KPIs we may have to
325 * refcount objects of this structure.
326 */
327 struct resource;
328 struct pci_mmio_region {
329 TAILQ_ENTRY(pci_mmio_region) next;
330 struct resource *res;
331 int rid;
332 int type;
333 };
334
335 struct pci_dev {
336 struct device dev;
337 struct list_head links;
338 struct pci_driver *pdrv;
339 struct pci_bus *bus;
340 struct pci_dev *root;
341 pci_power_t current_state;
342 uint16_t device;
343 uint16_t vendor;
344 uint16_t subsystem_vendor;
345 uint16_t subsystem_device;
346 unsigned int irq;
347 unsigned int devfn;
348 uint32_t class;
349 uint8_t revision;
350 uint8_t msi_cap;
351 uint8_t msix_cap;
352 bool managed; /* devres "pcim_*(). */
353 bool want_iomap_res;
354 bool msi_enabled;
355 bool msix_enabled;
356 phys_addr_t rom;
357 size_t romlen;
358 struct msi_desc **msi_desc;
359 char *path_name;
360 spinlock_t pcie_cap_lock;
361
362 TAILQ_HEAD(, pci_mmio_region) mmio;
363 };
364
365 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv,
366 unsigned int flags);
367 bool pci_device_is_present(struct pci_dev *pdev);
368
369 int linuxkpi_pcim_enable_device(struct pci_dev *pdev);
370 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev);
371 void *linuxkpi_pci_iomap_range(struct pci_dev *, int,
372 unsigned long, unsigned long);
373 void *linuxkpi_pci_iomap(struct pci_dev *, int, unsigned long);
374 void *linuxkpi_pcim_iomap(struct pci_dev *, int, unsigned long);
375 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res);
376 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask,
377 const char *name);
378 int linuxkpi_pci_request_region(struct pci_dev *, int, const char *);
379 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name);
380 int linuxkpi_pcim_request_all_regions(struct pci_dev *, const char *);
381 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar);
382 void linuxkpi_pci_release_regions(struct pci_dev *pdev);
383 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries,
384 int nreq);
385
386 /* Internal helper function(s). */
387 struct pci_dev *lkpinew_pci_dev(device_t);
388 void lkpi_pci_devres_release(struct device *, void *);
389 struct pci_dev *lkpi_pci_get_device(uint32_t, uint32_t, struct pci_dev *);
390 struct msi_desc *lkpi_pci_msi_desc_alloc(int);
391 struct device *lkpi_pci_find_irq_dev(unsigned int irq);
392 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec);
393
394 #define pci_err(pdev, fmt, ...) \
395 dev_err(&(pdev)->dev, fmt, ##__VA_ARGS__)
396 #define pci_info(pdev, fmt, ...) \
397 dev_info(&(pdev)->dev, fmt, ##__VA_ARGS__)
398
399 static inline bool
dev_is_pci(struct device * dev)400 dev_is_pci(struct device *dev)
401 {
402 return (is_pci_device(dev->bsddev));
403 }
404
405 static inline uint16_t
pci_dev_id(struct pci_dev * pdev)406 pci_dev_id(struct pci_dev *pdev)
407 {
408 return (PCI_DEVID(pdev->bus->number, pdev->devfn));
409 }
410
411 static inline int
pci_resource_type(struct pci_dev * pdev,int bar)412 pci_resource_type(struct pci_dev *pdev, int bar)
413 {
414 struct pci_map *pm;
415
416 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
417 if (!pm)
418 return (-1);
419
420 if (PCI_BAR_IO(pm->pm_value))
421 return (SYS_RES_IOPORT);
422 else
423 return (SYS_RES_MEMORY);
424 }
425
426 /*
427 * All drivers just seem to want to inspect the type not flags.
428 */
429 static inline int
pci_resource_flags(struct pci_dev * pdev,int bar)430 pci_resource_flags(struct pci_dev *pdev, int bar)
431 {
432 int type;
433
434 type = pci_resource_type(pdev, bar);
435 if (type < 0)
436 return (0);
437 return (1 << type);
438 }
439
440 static inline const char *
pci_name(struct pci_dev * d)441 pci_name(struct pci_dev *d)
442 {
443 return d->path_name;
444 }
445
446 static inline void *
pci_get_drvdata(struct pci_dev * pdev)447 pci_get_drvdata(struct pci_dev *pdev)
448 {
449
450 return dev_get_drvdata(&pdev->dev);
451 }
452
453 static inline void
pci_set_drvdata(struct pci_dev * pdev,void * data)454 pci_set_drvdata(struct pci_dev *pdev, void *data)
455 {
456
457 dev_set_drvdata(&pdev->dev, data);
458 }
459
460 static inline struct pci_dev *
pci_dev_get(struct pci_dev * pdev)461 pci_dev_get(struct pci_dev *pdev)
462 {
463
464 if (pdev != NULL)
465 get_device(&pdev->dev);
466 return (pdev);
467 }
468
469 static __inline void
pci_dev_put(struct pci_dev * pdev)470 pci_dev_put(struct pci_dev *pdev)
471 {
472
473 if (pdev != NULL)
474 put_device(&pdev->dev);
475 }
476
477 static inline int
pci_enable_device(struct pci_dev * pdev)478 pci_enable_device(struct pci_dev *pdev)
479 {
480
481 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
482 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
483 return (0);
484 }
485
486 static inline void
pci_disable_device(struct pci_dev * pdev)487 pci_disable_device(struct pci_dev *pdev)
488 {
489
490 pci_disable_busmaster(pdev->dev.bsddev);
491 }
492
493 static inline int
pci_set_master(struct pci_dev * pdev)494 pci_set_master(struct pci_dev *pdev)
495 {
496
497 pci_enable_busmaster(pdev->dev.bsddev);
498 return (0);
499 }
500
501 static inline int
pci_set_power_state(struct pci_dev * pdev,int state)502 pci_set_power_state(struct pci_dev *pdev, int state)
503 {
504
505 pci_set_powerstate(pdev->dev.bsddev, state);
506 return (0);
507 }
508
509 static inline int
pci_clear_master(struct pci_dev * pdev)510 pci_clear_master(struct pci_dev *pdev)
511 {
512
513 pci_disable_busmaster(pdev->dev.bsddev);
514 return (0);
515 }
516
517 static inline bool
pci_is_root_bus(struct pci_bus * pbus)518 pci_is_root_bus(struct pci_bus *pbus)
519 {
520
521 return (pbus->self == NULL);
522 }
523
524 static inline struct pci_dev *
pci_upstream_bridge(struct pci_dev * pdev)525 pci_upstream_bridge(struct pci_dev *pdev)
526 {
527
528 if (pci_is_root_bus(pdev->bus))
529 return (NULL);
530
531 /*
532 * If we do not have a (proper) "upstream bridge" set, e.g., we point
533 * to ourselves, try to handle this case on the fly like we do
534 * for pcie_find_root_port().
535 */
536 if (pdev == pdev->bus->self) {
537 device_t bridge;
538
539 /*
540 * In the case of DRM drivers, the passed device is a child of
541 * `vgapci`. We want to start the lookup from `vgapci`, so the
542 * parent of the passed `drmn`.
543 *
544 * We can use the `isdrm` flag to determine this.
545 */
546 bridge = pdev->dev.bsddev;
547 if (pdev->pdrv != NULL && pdev->pdrv->isdrm)
548 bridge = device_get_parent(bridge);
549 if (bridge == NULL)
550 goto done;
551
552 bridge = device_get_parent(bridge);
553 if (bridge == NULL)
554 goto done;
555 bridge = device_get_parent(bridge);
556 if (bridge == NULL)
557 goto done;
558 if (!is_pci_device(bridge))
559 goto done;
560
561 /*
562 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev
563 * for it so it can be returned.
564 */
565 pdev->bus->self = lkpinew_pci_dev(bridge);
566 }
567 done:
568 return (pdev->bus->self);
569 }
570
571 #define pci_request_region(pdev, bar, res_name) \
572 linuxkpi_pci_request_region(pdev, bar, res_name)
573 #define pci_release_region(pdev, bar) \
574 linuxkpi_pci_release_region(pdev, bar)
575 #define pci_request_regions(pdev, res_name) \
576 linuxkpi_pci_request_regions(pdev, res_name)
577 #define pci_release_regions(pdev) \
578 linuxkpi_pci_release_regions(pdev)
579 #define pcim_request_all_regions(pdev, name) \
580 linuxkpi_pcim_request_all_regions(pdev, name)
581
582 static inline void
lkpi_pci_disable_msix(struct pci_dev * pdev)583 lkpi_pci_disable_msix(struct pci_dev *pdev)
584 {
585
586 pci_release_msi(pdev->dev.bsddev);
587
588 /*
589 * The MSIX IRQ numbers associated with this PCI device are no
590 * longer valid and might be re-assigned. Make sure
591 * lkpi_pci_find_irq_dev() does no longer see them by
592 * resetting their references to zero:
593 */
594 pdev->dev.irq_start = 0;
595 pdev->dev.irq_end = 0;
596 pdev->msix_enabled = false;
597 }
598 /* Only for consistency. No conflict on that one. */
599 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev)
600
601 static inline void
lkpi_pci_disable_msi(struct pci_dev * pdev)602 lkpi_pci_disable_msi(struct pci_dev *pdev)
603 {
604
605 pci_release_msi(pdev->dev.bsddev);
606
607 pdev->dev.irq_start = 0;
608 pdev->dev.irq_end = 0;
609 pdev->irq = pdev->dev.irq;
610 pdev->msi_enabled = false;
611 }
612 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev)
613 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev)
614
615 unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
616 unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
617
618 static inline bus_addr_t
pci_bus_address(struct pci_dev * pdev,int bar)619 pci_bus_address(struct pci_dev *pdev, int bar)
620 {
621
622 return (pci_resource_start(pdev, bar));
623 }
624
625 #define PCI_CAP_ID_EXP PCIY_EXPRESS
626 #define PCI_CAP_ID_PCIX PCIY_PCIX
627 #define PCI_CAP_ID_AGP PCIY_AGP
628 #define PCI_CAP_ID_PM PCIY_PMG
629
630 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
631 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
632 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
633 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
634 #define PCI_EXP_LNKSTA PCIER_LINK_STA
635
636 static inline int
pci_find_capability(struct pci_dev * pdev,int capid)637 pci_find_capability(struct pci_dev *pdev, int capid)
638 {
639 int reg;
640
641 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
642 return (0);
643 return (reg);
644 }
645
pci_pcie_cap(struct pci_dev * dev)646 static inline int pci_pcie_cap(struct pci_dev *dev)
647 {
648 return pci_find_capability(dev, PCI_CAP_ID_EXP);
649 }
650
651 static inline int
pci_find_ext_capability(struct pci_dev * pdev,int capid)652 pci_find_ext_capability(struct pci_dev *pdev, int capid)
653 {
654 int reg;
655
656 if (pci_find_extcap(pdev->dev.bsddev, capid, ®))
657 return (0);
658 return (reg);
659 }
660
661 #define PCIM_PCAP_PME_SHIFT 11
662 static __inline bool
pci_pme_capable(struct pci_dev * pdev,uint32_t flag)663 pci_pme_capable(struct pci_dev *pdev, uint32_t flag)
664 {
665 struct pci_devinfo *dinfo;
666 pcicfgregs *cfg;
667
668 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT))
669 return (false);
670
671 dinfo = device_get_ivars(pdev->dev.bsddev);
672 cfg = &dinfo->cfg;
673
674 if (cfg->pp.pp_cap == 0)
675 return (false);
676
677 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0)
678 return (true);
679
680 return (false);
681 }
682
683 static inline int
pci_disable_link_state(struct pci_dev * pdev,uint32_t flags)684 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags)
685 {
686
687 if (!pci_enable_aspm)
688 return (-EPERM);
689
690 return (-ENXIO);
691 }
692
693 static inline int
pci_read_config_byte(const struct pci_dev * pdev,int where,u8 * val)694 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val)
695 {
696
697 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
698 return (0);
699 }
700
701 static inline int
pci_read_config_word(const struct pci_dev * pdev,int where,u16 * val)702 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val)
703 {
704
705 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
706 return (0);
707 }
708
709 static inline int
pci_read_config_dword(const struct pci_dev * pdev,int where,u32 * val)710 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val)
711 {
712
713 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
714 return (0);
715 }
716
717 static inline int
pci_write_config_byte(const struct pci_dev * pdev,int where,u8 val)718 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val)
719 {
720
721 pci_write_config(pdev->dev.bsddev, where, val, 1);
722 return (0);
723 }
724
725 static inline int
pci_write_config_word(const struct pci_dev * pdev,int where,u16 val)726 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val)
727 {
728
729 pci_write_config(pdev->dev.bsddev, where, val, 2);
730 return (0);
731 }
732
733 static inline int
pci_write_config_dword(const struct pci_dev * pdev,int where,u32 val)734 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val)
735 {
736
737 pci_write_config(pdev->dev.bsddev, where, val, 4);
738 return (0);
739 }
740
741 int linux_pci_register_driver(struct pci_driver *pdrv);
742 int linux_pci_register_drm_driver(struct pci_driver *pdrv);
743 void linux_pci_unregister_driver(struct pci_driver *pdrv);
744 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
745
746 #define pci_register_driver(pdrv) \
747 linux_pci_register_driver(pdrv)
748 #define pci_unregister_driver(pdrv) \
749 linux_pci_unregister_driver(pdrv)
750
751 /*
752 * Enable msix, positive errors indicate actual number of available
753 * vectors. Negative errors are failures.
754 *
755 * NB: define added to prevent this definition of pci_enable_msix from
756 * clashing with the native FreeBSD version.
757 */
758 #define pci_enable_msix(...) \
759 linuxkpi_pci_enable_msix(__VA_ARGS__)
760
761 #define pci_enable_msix_range(...) \
762 linux_pci_enable_msix_range(__VA_ARGS__)
763
764 static inline int
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)765 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
766 int minvec, int maxvec)
767 {
768 int nvec = maxvec;
769 int rc;
770
771 if (maxvec < minvec)
772 return (-ERANGE);
773
774 do {
775 rc = pci_enable_msix(dev, entries, nvec);
776 if (rc < 0) {
777 return (rc);
778 } else if (rc > 0) {
779 if (rc < minvec)
780 return (-ENOSPC);
781 nvec = rc;
782 }
783 } while (rc);
784 return (nvec);
785 }
786
787 #define pci_enable_msi(pdev) \
788 linux_pci_enable_msi(pdev)
789
790 static inline int
pci_enable_msi(struct pci_dev * pdev)791 pci_enable_msi(struct pci_dev *pdev)
792 {
793
794 return (_lkpi_pci_enable_msi_range(pdev, 1, 1));
795 }
796
797 static inline int
pci_channel_offline(struct pci_dev * pdev)798 pci_channel_offline(struct pci_dev *pdev)
799 {
800
801 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID);
802 }
803
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)804 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
805 {
806 return -ENODEV;
807 }
808
pci_disable_sriov(struct pci_dev * dev)809 static inline void pci_disable_sriov(struct pci_dev *dev)
810 {
811 }
812
813 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \
814 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size)
815 #define pci_iomap(pdev, mmio_bar, mmio_size) \
816 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size)
817 #define pcim_iomap(pdev, bar, maxlen) \
818 linuxkpi_pcim_iomap(pdev, bar, maxlen)
819 #define pci_iounmap(pdev, res) \
820 linuxkpi_pci_iounmap(pdev, res)
821
822 static inline void
lkpi_pci_save_state(struct pci_dev * pdev)823 lkpi_pci_save_state(struct pci_dev *pdev)
824 {
825
826 pci_save_state(pdev->dev.bsddev);
827 }
828
829 static inline void
lkpi_pci_restore_state(struct pci_dev * pdev)830 lkpi_pci_restore_state(struct pci_dev *pdev)
831 {
832
833 pci_restore_state(pdev->dev.bsddev);
834 }
835
836 #define pci_save_state(dev) lkpi_pci_save_state(dev)
837 #define pci_restore_state(dev) lkpi_pci_restore_state(dev)
838
839 static inline int
linuxkpi_pci_enable_wake(struct pci_dev * pdev,pci_power_t state,bool ena)840 linuxkpi_pci_enable_wake(struct pci_dev *pdev, pci_power_t state, bool ena)
841 {
842 /*
843 * We do not currently support this in device.h either to
844 * check if the device is allowed to wake up in first place.
845 */
846 pr_debug("%s: TODO\n", __func__);
847 return (0);
848 }
849 #define pci_enable_wake(dev, state, ena) \
850 linuxkpi_pci_enable_wake(dev, state, ena)
851
852 static inline int
pci_reset_function(struct pci_dev * pdev)853 pci_reset_function(struct pci_dev *pdev)
854 {
855
856 return (-ENOSYS);
857 }
858
859 #define DEFINE_PCI_DEVICE_TABLE(_table) \
860 const struct pci_device_id _table[] __devinitdata
861
862 /* XXX This should not be necessary. */
863 #define pcix_set_mmrbc(d, v) 0
864 #define pcix_get_max_mmrbc(d) 0
865 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v))
866
867 #define PCI_DMA_BIDIRECTIONAL 0
868 #define PCI_DMA_TODEVICE 1
869 #define PCI_DMA_FROMDEVICE 2
870 #define PCI_DMA_NONE 3
871
872 #define pci_pool dma_pool
873 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
874 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
875 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
876 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
877 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
878 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
879 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
880 _size, _vaddr, _dma_handle)
881 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
882 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
883 _sg, _nents, (enum dma_data_direction)_dir)
884 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
885 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
886 (_ptr), (_size), (enum dma_data_direction)_dir)
887 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
888 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
889 _addr, _size, (enum dma_data_direction)_dir)
890 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
891 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
892 _sg, _nents, (enum dma_data_direction)_dir)
893 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
894 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
895 _offset, _size, (enum dma_data_direction)_dir)
896 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
897 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
898 _dma_address, _size, (enum dma_data_direction)_dir)
899 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
900 #define pci_dma_mapping_error(_pdev, _dma_addr) \
901 dma_mapping_error(&(_pdev)->dev, _dma_addr)
902 #define pci_set_consistent_dma_mask(_pdev, _mask) \
903 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
904 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
905 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
906 #define pci_unmap_addr dma_unmap_addr
907 #define pci_unmap_addr_set dma_unmap_addr_set
908 #define pci_unmap_len dma_unmap_len
909 #define pci_unmap_len_set dma_unmap_len_set
910
911 typedef unsigned int __bitwise pci_channel_state_t;
912 typedef unsigned int __bitwise pci_ers_result_t;
913
914 enum pci_channel_state {
915 pci_channel_io_normal = 1,
916 pci_channel_io_frozen = 2,
917 pci_channel_io_perm_failure = 3,
918 };
919
920 enum pci_ers_result {
921 PCI_ERS_RESULT_NONE = 1,
922 PCI_ERS_RESULT_CAN_RECOVER = 2,
923 PCI_ERS_RESULT_NEED_RESET = 3,
924 PCI_ERS_RESULT_DISCONNECT = 4,
925 PCI_ERS_RESULT_RECOVERED = 5,
926 };
927
928 /* PCI bus error event callbacks */
929 struct pci_error_handlers {
930 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
931 enum pci_channel_state error);
932 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
933 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
934 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
935 void (*resume)(struct pci_dev *dev);
936 };
937
938 /* FreeBSD does not support SRIOV - yet */
pci_physfn(struct pci_dev * dev)939 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
940 {
941 return dev;
942 }
943
pci_is_pcie(struct pci_dev * dev)944 static inline bool pci_is_pcie(struct pci_dev *dev)
945 {
946 return !!pci_pcie_cap(dev);
947 }
948
pcie_flags_reg(struct pci_dev * dev)949 static inline u16 pcie_flags_reg(struct pci_dev *dev)
950 {
951 int pos;
952 u16 reg16;
953
954 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
955 if (!pos)
956 return 0;
957
958 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
959
960 return reg16;
961 }
962
pci_pcie_type(struct pci_dev * dev)963 static inline int pci_pcie_type(struct pci_dev *dev)
964 {
965 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
966 }
967
pcie_cap_version(struct pci_dev * dev)968 static inline int pcie_cap_version(struct pci_dev *dev)
969 {
970 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
971 }
972
pcie_cap_has_lnkctl(struct pci_dev * dev)973 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
974 {
975 int type = pci_pcie_type(dev);
976
977 return pcie_cap_version(dev) > 1 ||
978 type == PCI_EXP_TYPE_ROOT_PORT ||
979 type == PCI_EXP_TYPE_ENDPOINT ||
980 type == PCI_EXP_TYPE_LEG_END;
981 }
982
pcie_cap_has_devctl(const struct pci_dev * dev)983 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
984 {
985 return true;
986 }
987
pcie_cap_has_sltctl(struct pci_dev * dev)988 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
989 {
990 int type = pci_pcie_type(dev);
991
992 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
993 (type == PCI_EXP_TYPE_DOWNSTREAM &&
994 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
995 }
996
pcie_cap_has_rtctl(struct pci_dev * dev)997 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
998 {
999 int type = pci_pcie_type(dev);
1000
1001 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
1002 type == PCI_EXP_TYPE_RC_EC;
1003 }
1004
pcie_capability_reg_implemented(struct pci_dev * dev,int pos)1005 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
1006 {
1007 if (!pci_is_pcie(dev))
1008 return false;
1009
1010 switch (pos) {
1011 case PCI_EXP_FLAGS_TYPE:
1012 return true;
1013 case PCI_EXP_DEVCAP:
1014 case PCI_EXP_DEVCTL:
1015 case PCI_EXP_DEVSTA:
1016 return pcie_cap_has_devctl(dev);
1017 case PCI_EXP_LNKCAP:
1018 case PCI_EXP_LNKCTL:
1019 case PCI_EXP_LNKSTA:
1020 return pcie_cap_has_lnkctl(dev);
1021 case PCI_EXP_SLTCAP:
1022 case PCI_EXP_SLTCTL:
1023 case PCI_EXP_SLTSTA:
1024 return pcie_cap_has_sltctl(dev);
1025 case PCI_EXP_RTCTL:
1026 case PCI_EXP_RTCAP:
1027 case PCI_EXP_RTSTA:
1028 return pcie_cap_has_rtctl(dev);
1029 case PCI_EXP_DEVCAP2:
1030 case PCI_EXP_DEVCTL2:
1031 case PCI_EXP_LNKCAP2:
1032 case PCI_EXP_LNKCTL2:
1033 case PCI_EXP_LNKSTA2:
1034 return pcie_cap_version(dev) > 1;
1035 default:
1036 return false;
1037 }
1038 }
1039
1040 static inline int
pcie_capability_read_dword(struct pci_dev * dev,int pos,u32 * dst)1041 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
1042 {
1043 *dst = 0;
1044 if (pos & 3)
1045 return -EINVAL;
1046
1047 if (!pcie_capability_reg_implemented(dev, pos))
1048 return -EINVAL;
1049
1050 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
1051 }
1052
1053 static inline int
pcie_capability_read_word(struct pci_dev * dev,int pos,u16 * dst)1054 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
1055 {
1056 *dst = 0;
1057 if (pos & 3)
1058 return -EINVAL;
1059
1060 if (!pcie_capability_reg_implemented(dev, pos))
1061 return -EINVAL;
1062
1063 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
1064 }
1065
1066 static inline int
pcie_capability_write_word(struct pci_dev * dev,int pos,u16 val)1067 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
1068 {
1069 if (pos & 1)
1070 return -EINVAL;
1071
1072 if (!pcie_capability_reg_implemented(dev, pos))
1073 return 0;
1074
1075 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
1076 }
1077
1078 static inline int
pcie_capability_clear_and_set_word(struct pci_dev * dev,int pos,uint16_t clear,uint16_t set)1079 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1080 uint16_t clear, uint16_t set)
1081 {
1082 int error;
1083 uint16_t v;
1084
1085 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL)
1086 spin_lock(&dev->pcie_cap_lock);
1087
1088 error = pcie_capability_read_word(dev, pos, &v);
1089 if (error == 0) {
1090 v &= ~clear;
1091 v |= set;
1092 error = pcie_capability_write_word(dev, pos, v);
1093 }
1094
1095 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL)
1096 spin_unlock(&dev->pcie_cap_lock);
1097
1098 return (error);
1099 }
1100
1101 static inline int
pcie_capability_set_word(struct pci_dev * dev,int pos,uint16_t val)1102 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val)
1103 {
1104 return (pcie_capability_clear_and_set_word(dev, pos, 0, val));
1105 }
1106
1107 static inline int
pcie_capability_clear_word(struct pci_dev * dev,int pos,uint16_t val)1108 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val)
1109 {
1110 return (pcie_capability_clear_and_set_word(dev, pos, val, 0));
1111 }
1112
pcie_get_minimum_link(struct pci_dev * dev,enum pci_bus_speed * speed,enum pcie_link_width * width)1113 static inline int pcie_get_minimum_link(struct pci_dev *dev,
1114 enum pci_bus_speed *speed, enum pcie_link_width *width)
1115 {
1116 *speed = PCI_SPEED_UNKNOWN;
1117 *width = PCIE_LNK_WIDTH_UNKNOWN;
1118 return (0);
1119 }
1120
1121 static inline int
pci_num_vf(struct pci_dev * dev)1122 pci_num_vf(struct pci_dev *dev)
1123 {
1124 return (0);
1125 }
1126
1127 static inline enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev * dev)1128 pcie_get_speed_cap(struct pci_dev *dev)
1129 {
1130 struct pci_dev *pbus;
1131 device_t root;
1132 uint32_t lnkcap, lnkcap2;
1133 int error, pos;
1134
1135 /*
1136 * We should always be called on a PCI device.
1137 * The only current consumer I could find was amdgpu which either
1138 * calls us directly on a pdev(drmn?) or with the result of
1139 * pci_upstream_bridge().
1140 *
1141 * Treat "drmn" as special again as it is not a PCI device.
1142 */
1143 if (dev->pdrv != NULL && dev->pdrv->isdrm) {
1144 pbus = pci_upstream_bridge(dev);
1145 if (pbus == NULL)
1146 return (PCI_SPEED_UNKNOWN);
1147 } else
1148 pbus = dev;
1149
1150 /* "root" may be misleading as it may not be that. */
1151 root = pbus->dev.bsddev;
1152
1153 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
1154 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
1155 return (PCI_SPEED_UNKNOWN);
1156
1157 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
1158 return (PCI_SPEED_UNKNOWN);
1159
1160 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
1161
1162 if (lnkcap2) { /* PCIe r3.0-compliant */
1163 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
1164 return (PCIE_SPEED_2_5GT);
1165 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
1166 return (PCIE_SPEED_5_0GT);
1167 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
1168 return (PCIE_SPEED_8_0GT);
1169 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
1170 return (PCIE_SPEED_16_0GT);
1171 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
1172 return (PCIE_SPEED_32_0GT);
1173 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB)
1174 return (PCIE_SPEED_64_0GT);
1175 } else { /* pre-r3.0 */
1176 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
1177 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
1178 return (PCIE_SPEED_2_5GT);
1179 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
1180 return (PCIE_SPEED_5_0GT);
1181 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
1182 return (PCIE_SPEED_8_0GT);
1183 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
1184 return (PCIE_SPEED_16_0GT);
1185 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB)
1186 return (PCIE_SPEED_32_0GT);
1187 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB)
1188 return (PCIE_SPEED_64_0GT);
1189 }
1190 return (PCI_SPEED_UNKNOWN);
1191 }
1192
1193 static inline enum pcie_link_width
pcie_get_width_cap(struct pci_dev * dev)1194 pcie_get_width_cap(struct pci_dev *dev)
1195 {
1196 uint32_t lnkcap;
1197
1198 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
1199 if (lnkcap)
1200 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
1201
1202 return (PCIE_LNK_WIDTH_UNKNOWN);
1203 }
1204
1205 static inline int
pcie_get_mps(struct pci_dev * dev)1206 pcie_get_mps(struct pci_dev *dev)
1207 {
1208 return (pci_get_max_payload(dev->dev.bsddev));
1209 }
1210
1211 static inline uint32_t
PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)1212 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)
1213 {
1214
1215 switch(spd) {
1216 case PCIE_SPEED_64_0GT:
1217 return (64000 * 128 / 130);
1218 case PCIE_SPEED_32_0GT:
1219 return (32000 * 128 / 130);
1220 case PCIE_SPEED_16_0GT:
1221 return (16000 * 128 / 130);
1222 case PCIE_SPEED_8_0GT:
1223 return (8000 * 128 / 130);
1224 case PCIE_SPEED_5_0GT:
1225 return (5000 * 8 / 10);
1226 case PCIE_SPEED_2_5GT:
1227 return (2500 * 8 / 10);
1228 default:
1229 return (0);
1230 }
1231 }
1232
1233 static inline uint32_t
pcie_bandwidth_available(struct pci_dev * pdev,struct pci_dev ** limiting,enum pci_bus_speed * speed,enum pcie_link_width * width)1234 pcie_bandwidth_available(struct pci_dev *pdev,
1235 struct pci_dev **limiting,
1236 enum pci_bus_speed *speed,
1237 enum pcie_link_width *width)
1238 {
1239 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev);
1240 enum pcie_link_width nwidth = pcie_get_width_cap(pdev);
1241
1242 if (speed)
1243 *speed = nspeed;
1244 if (width)
1245 *width = nwidth;
1246
1247 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed));
1248 }
1249
1250 static inline bool
pcie_aspm_enabled(struct pci_dev * pdev)1251 pcie_aspm_enabled(struct pci_dev *pdev)
1252 {
1253 return (false);
1254 }
1255
1256 static inline struct pci_dev *
pcie_find_root_port(struct pci_dev * pdev)1257 pcie_find_root_port(struct pci_dev *pdev)
1258 {
1259 device_t root;
1260
1261 if (pdev->root != NULL)
1262 return (pdev->root);
1263
1264 root = pci_find_pcie_root_port(pdev->dev.bsddev);
1265 if (root == NULL)
1266 return (NULL);
1267
1268 pdev->root = lkpinew_pci_dev(root);
1269 return (pdev->root);
1270 }
1271
1272 /* This is needed when people rip out the device "HotPlug". */
1273 static inline void
pci_lock_rescan_remove(void)1274 pci_lock_rescan_remove(void)
1275 {
1276 }
1277
1278 static inline void
pci_unlock_rescan_remove(void)1279 pci_unlock_rescan_remove(void)
1280 {
1281 }
1282
1283 static __inline void
pci_stop_and_remove_bus_device(struct pci_dev * pdev)1284 pci_stop_and_remove_bus_device(struct pci_dev *pdev)
1285 {
1286 }
1287
1288 static inline int
pci_rescan_bus(struct pci_bus * pbus)1289 pci_rescan_bus(struct pci_bus *pbus)
1290 {
1291 device_t *devlist, parent;
1292 int devcount, error;
1293
1294 if (!device_is_attached(pbus->self->dev.bsddev))
1295 return (0);
1296 /* pci_rescan_method() will work on the pcib (parent). */
1297 error = BUS_RESCAN(pbus->self->dev.bsddev);
1298 if (error != 0)
1299 return (0);
1300
1301 parent = device_get_parent(pbus->self->dev.bsddev);
1302 error = device_get_children(parent, &devlist, &devcount);
1303 if (error != 0)
1304 return (0);
1305 if (devcount != 0)
1306 free(devlist, M_TEMP);
1307
1308 return (devcount);
1309 }
1310
1311 /*
1312 * The following functions can be used to attach/detach the LinuxKPI's
1313 * PCI device runtime. The pci_driver and pci_device_id pointer is
1314 * allowed to be NULL. Other pointers must be all valid.
1315 * The pci_dev structure should be zero-initialized before passed
1316 * to the linux_pci_attach_device function.
1317 */
1318 extern int linux_pci_attach_device(device_t, struct pci_driver *,
1319 const struct pci_device_id *, struct pci_dev *);
1320 extern int linux_pci_detach_device(struct pci_dev *);
1321
1322 static inline int
pci_dev_present(const struct pci_device_id * cur)1323 pci_dev_present(const struct pci_device_id *cur)
1324 {
1325 while (cur != NULL && (cur->vendor || cur->device)) {
1326 if (pci_find_device(cur->vendor, cur->device) != NULL) {
1327 return (1);
1328 }
1329 cur++;
1330 }
1331 return (0);
1332 }
1333
1334 static inline bool
pci_dev_is_disconnected(const struct pci_dev * pdev)1335 pci_dev_is_disconnected(const struct pci_dev *pdev)
1336 {
1337 pr_debug("TODO: %s\n", __func__);
1338 return (false);
1339 }
1340
1341 static inline const struct pci_device_id *
pci_match_id(const struct pci_device_id * ids,struct pci_dev * pdev)1342 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev)
1343 {
1344 if (ids == NULL)
1345 return (NULL);
1346
1347 for (;
1348 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0;
1349 ids++)
1350 if ((ids->vendor == PCI_ANY_ID ||
1351 ids->vendor == pdev->vendor) &&
1352 (ids->device == PCI_ANY_ID ||
1353 ids->device == pdev->device) &&
1354 (ids->subvendor == PCI_ANY_ID ||
1355 ids->subvendor == pdev->subsystem_vendor) &&
1356 (ids->subdevice == PCI_ANY_ID ||
1357 ids->subdevice == pdev->subsystem_device) &&
1358 ((ids->class ^ pdev->class) & ids->class_mask) == 0)
1359 return (ids);
1360
1361 return (NULL);
1362 }
1363
1364 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
1365 unsigned int bus, unsigned int devfn);
1366 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \
1367 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
1368
1369 struct pci_dev *lkpi_pci_get_slot(struct pci_bus *, unsigned int);
1370 #ifndef WANT_NATIVE_PCI_GET_SLOT
1371 #define pci_get_slot(_pbus, _devfn) \
1372 lkpi_pci_get_slot(_pbus, _devfn)
1373 #endif
1374
1375 static inline int
pci_domain_nr(struct pci_bus * pbus)1376 pci_domain_nr(struct pci_bus *pbus)
1377 {
1378
1379 return (pbus->domain);
1380 }
1381
1382 static inline int
pci_bus_read_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t * val,int len)1383 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn,
1384 int pos, uint32_t *val, int len)
1385 {
1386
1387 *val = pci_read_config(bus->self->dev.bsddev, pos, len);
1388 return (0);
1389 }
1390
1391 static inline int
pci_bus_read_config_word(struct pci_bus * bus,unsigned int devfn,int pos,u16 * val)1392 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val)
1393 {
1394 uint32_t tmp;
1395 int ret;
1396
1397 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2);
1398 *val = (u16)tmp;
1399 return (ret);
1400 }
1401
1402 static inline int
pci_bus_read_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,u8 * val)1403 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val)
1404 {
1405 uint32_t tmp;
1406 int ret;
1407
1408 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1);
1409 *val = (u8)tmp;
1410 return (ret);
1411 }
1412
1413 static inline int
pci_bus_write_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t val,int size)1414 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos,
1415 uint32_t val, int size)
1416 {
1417
1418 pci_write_config(bus->self->dev.bsddev, pos, val, size);
1419 return (0);
1420 }
1421
1422 static inline int
pci_bus_write_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,uint8_t val)1423 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos,
1424 uint8_t val)
1425 {
1426 return (pci_bus_write_config(bus, devfn, pos, val, 1));
1427 }
1428
1429 static inline int
pci_bus_write_config_word(struct pci_bus * bus,unsigned int devfn,int pos,uint16_t val)1430 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos,
1431 uint16_t val)
1432 {
1433 return (pci_bus_write_config(bus, devfn, pos, val, 2));
1434 }
1435
1436 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from);
1437 #define pci_get_class(class, from) lkpi_pci_get_class(class, from)
1438 struct pci_dev *lkpi_pci_get_base_class(unsigned int class,
1439 struct pci_dev *from);
1440 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from)
1441
1442 /* -------------------------------------------------------------------------- */
1443
1444 #define pcim_enable_device(pdev) \
1445 linuxkpi_pcim_enable_device(pdev)
1446 #define pcim_iomap_table(pdev) \
1447 linuxkpi_pcim_iomap_table(pdev)
1448 #define pcim_iomap_regions(pdev, mask, name) \
1449 linuxkpi_pcim_iomap_regions(pdev, mask, name)
1450
1451 static inline int
pcim_iomap_regions_request_all(struct pci_dev * pdev,uint32_t mask,char * name)1452 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name)
1453 {
1454 uint32_t requests, req_mask;
1455 int bar, error;
1456
1457 /* Request all the BARs ("regions") we do not iomap. */
1458 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask;
1459 for (bar = requests = 0; requests != req_mask; bar++) {
1460 if ((req_mask & (1 << bar)) == 0)
1461 continue;
1462 error = pci_request_region(pdev, bar, name);
1463 if (error != 0 && error != -ENODEV)
1464 goto err;
1465 requests |= (1 << bar);
1466 }
1467
1468 error = pcim_iomap_regions(pdev, mask, name);
1469 if (error != 0)
1470 goto err;
1471
1472 return (0);
1473
1474 err:
1475 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) {
1476 if ((requests & (1 << bar)) != 0)
1477 pci_release_region(pdev, bar);
1478 }
1479
1480 return (-EINVAL);
1481 }
1482
1483 /*
1484 * We cannot simply re-define pci_get_device() as we would normally do
1485 * and then hide it in linux_pci.c as too many semi-native drivers still
1486 * include linux/pci.h and run into the conflict with native PCI. Linux drivers
1487 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device().
1488 */
1489 static inline struct pci_dev *
linuxkpi_pci_get_device(uint32_t vendor,uint32_t device,struct pci_dev * odev)1490 linuxkpi_pci_get_device(uint32_t vendor, uint32_t device, struct pci_dev *odev)
1491 {
1492
1493 return (lkpi_pci_get_device(vendor, device, odev));
1494 }
1495
1496 #define for_each_pci_dev(_pdev) \
1497 while ((_pdev = linuxkpi_pci_get_device(PCI_ANY_ID, PCI_ANY_ID, _pdev)) != NULL)
1498
1499 /* This is a FreeBSD extension so we can use bus_*(). */
1500 static inline void
linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev * pdev)1501 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev)
1502 {
1503 pdev->want_iomap_res = true;
1504 }
1505
1506 static inline bool
pci_is_thunderbolt_attached(struct pci_dev * pdev)1507 pci_is_thunderbolt_attached(struct pci_dev *pdev)
1508 {
1509
1510 return (false);
1511 }
1512
1513 static inline void *
pci_platform_rom(struct pci_dev * pdev,size_t * size)1514 pci_platform_rom(struct pci_dev *pdev, size_t *size)
1515 {
1516
1517 return (NULL);
1518 }
1519
1520 static inline void
pci_ignore_hotplug(struct pci_dev * pdev)1521 pci_ignore_hotplug(struct pci_dev *pdev)
1522 {
1523 }
1524
1525 static inline const char *
pci_power_name(pci_power_t state)1526 pci_power_name(pci_power_t state)
1527 {
1528 int pstate = state + 1;
1529
1530 if (pstate >= 0 && pstate < nitems(pci_power_names))
1531 return (pci_power_names[pstate]);
1532 else
1533 return (pci_power_names[0]);
1534 }
1535
1536 static inline int
pcie_get_readrq(struct pci_dev * dev)1537 pcie_get_readrq(struct pci_dev *dev)
1538 {
1539 u16 ctl;
1540
1541 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl))
1542 return (-EINVAL);
1543
1544 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12));
1545 }
1546
1547 static inline bool
pci_is_enabled(struct pci_dev * pdev)1548 pci_is_enabled(struct pci_dev *pdev)
1549 {
1550
1551 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) &
1552 PCIM_CMD_BUSMASTEREN) != 0);
1553 }
1554
1555 static inline int
pci_wait_for_pending_transaction(struct pci_dev * pdev)1556 pci_wait_for_pending_transaction(struct pci_dev *pdev)
1557 {
1558
1559 return (0);
1560 }
1561
1562 static inline int
pci_assign_resource(struct pci_dev * pdev,int bar)1563 pci_assign_resource(struct pci_dev *pdev, int bar)
1564 {
1565
1566 return (0);
1567 }
1568
1569 static inline int
pci_irq_vector(struct pci_dev * pdev,unsigned int vector)1570 pci_irq_vector(struct pci_dev *pdev, unsigned int vector)
1571 {
1572
1573 if (!pdev->msix_enabled && !pdev->msi_enabled) {
1574 if (vector != 0)
1575 return (-EINVAL);
1576 return (pdev->irq);
1577 }
1578
1579 if (pdev->msix_enabled || pdev->msi_enabled) {
1580 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end)
1581 return (-EINVAL);
1582 return (pdev->dev.irq_start + vector);
1583 }
1584
1585 return (-ENXIO);
1586 }
1587
1588 static inline int
pci_wake_from_d3(struct pci_dev * pdev,bool enable)1589 pci_wake_from_d3(struct pci_dev *pdev, bool enable)
1590 {
1591
1592 pr_debug("%s: TODO\n", __func__);
1593 return (0);
1594 }
1595
1596 #endif /* _LINUXKPI_LINUX_PCI_H_ */
1597