1 /*-
2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
6 * All rights reserved.
7 * Copyright (c) 2020-2022 The FreeBSD Foundation
8 *
9 * Portions of this software were developed by Björn Zeeb
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
17 * disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33 #ifndef _LINUXKPI_LINUX_PCI_H_
34 #define _LINUXKPI_LINUX_PCI_H_
35
36 #define CONFIG_PCI_MSI
37
38 #include <linux/types.h>
39 #include <linux/device/driver.h>
40
41 #include <sys/param.h>
42 #include <sys/bus.h>
43 #include <sys/module.h>
44 #include <sys/nv.h>
45 #include <sys/pciio.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pci_private.h>
49
50 #include <machine/resource.h>
51
52 #include <linux/list.h>
53 #include <linux/dmapool.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/compiler.h>
56 #include <linux/errno.h>
57 #include <asm/atomic.h>
58 #include <asm/memtype.h>
59 #include <linux/device.h>
60 #include <linux/pci_ids.h>
61 #include <linux/pm.h>
62
63 #include <linux/kernel.h> /* pr_debug */
64
65 struct pci_device_id {
66 uint32_t vendor;
67 uint32_t device;
68 uint32_t subvendor;
69 uint32_t subdevice;
70 uint32_t class;
71 uint32_t class_mask;
72 uintptr_t driver_data;
73 };
74
75 /* Linux has an empty element at the end of the ID table -> nitems() - 1. */
76 #define MODULE_DEVICE_TABLE(_bus, _table) \
77 \
78 static device_method_t _ ## _bus ## _ ## _table ## _methods[] = { \
79 DEVMETHOD_END \
80 }; \
81 \
82 static driver_t _ ## _bus ## _ ## _table ## _driver = { \
83 "lkpi_" #_bus #_table, \
84 _ ## _bus ## _ ## _table ## _methods, \
85 0 \
86 }; \
87 \
88 DRIVER_MODULE(lkpi_ ## _table, pci, _ ## _bus ## _ ## _table ## _driver,\
89 0, 0); \
90 \
91 MODULE_PNP_INFO("U32:vendor;U32:device;V32:subvendor;V32:subdevice", \
92 _bus, lkpi_ ## _table, _table, nitems(_table) - 1)
93
94 #define PCI_ANY_ID -1U
95
96 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
97 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
98 #define PCI_FUNC(devfn) ((devfn) & 0x07)
99 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff)
100 #define PCI_DEVID(bus, devfn) ((((uint16_t)(bus)) << 8) | (devfn))
101
102 #define PCI_VDEVICE(_vendor, _device) \
103 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
104 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
105 #define PCI_DEVICE(_vendor, _device) \
106 .vendor = (_vendor), .device = (_device), \
107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
108
109 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
110
111 #define PCI_STD_NUM_BARS 6
112 #define PCI_BASE_ADDRESS_0 PCIR_BARS
113 #define PCI_BASE_ADDRESS_MEM_TYPE_64 PCIM_BAR_MEM_64
114 #define PCI_VENDOR_ID PCIR_VENDOR
115 #define PCI_DEVICE_ID PCIR_DEVICE
116 #define PCI_COMMAND PCIR_COMMAND
117 #define PCI_COMMAND_INTX_DISABLE PCIM_CMD_INTxDIS
118 #define PCI_COMMAND_MEMORY PCIM_CMD_MEMEN
119 #define PCI_PRIMARY_BUS PCIR_PRIBUS_1
120 #define PCI_SECONDARY_BUS PCIR_SECBUS_1
121 #define PCI_SUBORDINATE_BUS PCIR_SUBBUS_1
122 #define PCI_SEC_LATENCY_TIMER PCIR_SECLAT_1
123 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
124 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
125 #define PCI_EXP_LNKCTL_ASPM_L0S PCIEM_LINK_CTL_ASPMC_L0S
126 #define PCI_EXP_LNKCTL_ASPM_L1 PCIEM_LINK_CTL_ASPMC_L1
127 #define PCI_EXP_LNKCTL_ASPMC PCIEM_LINK_CTL_ASPMC
128 #define PCI_EXP_LNKCTL_CLKREQ_EN PCIEM_LINK_CTL_ECPM /* Enable clock PM */
129 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
130 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
131 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
132 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
133 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
134 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
135 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
136 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
137 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
138 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
139 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
140 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
141 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
142 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
143 #define PCI_EXP_DEVCTL2_LTR_EN PCIEM_CTL2_LTR_ENABLE
144 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS PCIEM_CTL2_COMP_TIMO_DISABLE
145 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
146 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
147 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
148 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
149 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
150 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
151 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
152 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
153 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
154 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
155 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
156 #define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED
157 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
158 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
159 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
160 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x03 /* Supported Link Speed 8.0GT/s */
161 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x04 /* Supported Link Speed 16.0GT/s */
162 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x05 /* Supported Link Speed 32.0GT/s */
163 #define PCI_EXP_LNKCAP_SLS_64_0GB 0x06 /* Supported Link Speed 64.0GT/s */
164 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
165 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
166 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
167 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
168 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */
169 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x20 /* Supported Link Speed 32.0GT/s */
170 #define PCI_EXP_LNKCAP2_SLS_64_0GB 0x40 /* Supported Link Speed 64.0GT/s */
171 #define PCI_EXP_LNKCTL2_TLS 0x000f
172 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
173 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
174 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
175 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
176 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */
177 #define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */
178 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */
179 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */
180
181 #define PCI_MSI_ADDRESS_LO PCIR_MSI_ADDR
182 #define PCI_MSI_ADDRESS_HI PCIR_MSI_ADDR_HIGH
183 #define PCI_MSI_FLAGS PCIR_MSI_CTRL
184 #define PCI_MSI_FLAGS_ENABLE PCIM_MSICTRL_MSI_ENABLE
185 #define PCI_MSIX_FLAGS PCIR_MSIX_CTRL
186 #define PCI_MSIX_FLAGS_ENABLE PCIM_MSIXCTRL_MSIX_ENABLE
187
188 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
189 #define PCI_EXP_DEVSTA_TRPND 0x0020
190
191 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
192 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
193 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
194
195 enum pci_bus_speed {
196 PCI_SPEED_UNKNOWN = -1,
197 PCIE_SPEED_2_5GT,
198 PCIE_SPEED_5_0GT,
199 PCIE_SPEED_8_0GT,
200 PCIE_SPEED_16_0GT,
201 PCIE_SPEED_32_0GT,
202 PCIE_SPEED_64_0GT,
203 };
204
205 enum pcie_link_width {
206 PCIE_LNK_WIDTH_RESRV = 0x00,
207 PCIE_LNK_X1 = 0x01,
208 PCIE_LNK_X2 = 0x02,
209 PCIE_LNK_X4 = 0x04,
210 PCIE_LNK_X8 = 0x08,
211 PCIE_LNK_X12 = 0x0c,
212 PCIE_LNK_X16 = 0x10,
213 PCIE_LNK_X32 = 0x20,
214 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
215 };
216
217 #define PCIE_LINK_STATE_L0S 0x00000001
218 #define PCIE_LINK_STATE_L1 0x00000002
219 #define PCIE_LINK_STATE_CLKPM 0x00000004
220
221 typedef int pci_power_t;
222
223 #define PCI_D0 PCI_POWERSTATE_D0
224 #define PCI_D1 PCI_POWERSTATE_D1
225 #define PCI_D2 PCI_POWERSTATE_D2
226 #define PCI_D3hot PCI_POWERSTATE_D3
227 #define PCI_D3cold 4
228
229 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
230
231 extern const char *pci_power_names[6];
232
233 #define PCI_ERR_UNCOR_STATUS PCIR_AER_UC_STATUS
234 #define PCI_ERR_COR_STATUS PCIR_AER_COR_STATUS
235 #define PCI_ERR_ROOT_COMMAND PCIR_AER_ROOTERR_CMD
236 #define PCI_ERR_ROOT_ERR_SRC PCIR_AER_COR_SOURCE_ID
237
238 #define PCI_EXT_CAP_ID_ERR PCIZ_AER
239 #define PCI_EXT_CAP_ID_L1SS PCIZ_L1PM
240
241 #define PCI_L1SS_CTL1 0x8
242 #define PCI_L1SS_CTL1_L1SS_MASK 0xf
243
244 #define PCI_IRQ_INTX 0x01
245 #define PCI_IRQ_MSI 0x02
246 #define PCI_IRQ_MSIX 0x04
247 #define PCI_IRQ_ALL_TYPES (PCI_IRQ_MSIX|PCI_IRQ_MSI|PCI_IRQ_INTX)
248
249 #if defined(LINUXKPI_VERSION) && (LINUXKPI_VERSION <= 61000)
250 #define PCI_IRQ_LEGACY PCI_IRQ_INTX
251 #endif
252
253 struct pci_dev;
254
255 struct pci_driver {
256 struct list_head node;
257 char *name;
258 const struct pci_device_id *id_table;
259 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
260 void (*remove)(struct pci_dev *dev);
261 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
262 int (*resume) (struct pci_dev *dev); /* Device woken up */
263 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
264 driver_t bsddriver;
265 devclass_t bsdclass;
266 struct device_driver driver;
267 const struct pci_error_handlers *err_handler;
268 bool isdrm;
269 int bsd_probe_return;
270 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs,
271 const nvlist_t *pf_config);
272 void (*bsd_iov_uninit)(device_t dev);
273 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum,
274 const nvlist_t *vf_config);
275 };
276
277 struct pci_bus {
278 struct pci_dev *self;
279 /* struct pci_bus *parent */
280 int domain;
281 int number;
282 };
283
284 extern struct list_head pci_drivers;
285 extern struct list_head pci_devices;
286 extern spinlock_t pci_lock;
287
288 #define __devexit_p(x) x
289
290 #define module_pci_driver(_drv) \
291 module_driver(_drv, linux_pci_register_driver, linux_pci_unregister_driver)
292
293 struct msi_msg {
294 uint32_t data;
295 };
296
297 struct pci_msi_desc {
298 struct {
299 bool is_64;
300 } msi_attrib;
301 };
302
303 struct msi_desc {
304 struct msi_msg msg;
305 struct pci_msi_desc pci;
306 };
307
308 struct msix_entry {
309 int entry;
310 int vector;
311 };
312
313 /*
314 * If we find drivers accessing this from multiple KPIs we may have to
315 * refcount objects of this structure.
316 */
317 struct resource;
318 struct pci_mmio_region {
319 TAILQ_ENTRY(pci_mmio_region) next;
320 struct resource *res;
321 int rid;
322 int type;
323 };
324
325 struct pci_dev {
326 struct device dev;
327 struct list_head links;
328 struct pci_driver *pdrv;
329 struct pci_bus *bus;
330 struct pci_dev *root;
331 pci_power_t current_state;
332 uint16_t device;
333 uint16_t vendor;
334 uint16_t subsystem_vendor;
335 uint16_t subsystem_device;
336 unsigned int irq;
337 unsigned int devfn;
338 uint32_t class;
339 uint8_t revision;
340 uint8_t msi_cap;
341 uint8_t msix_cap;
342 bool managed; /* devres "pcim_*(). */
343 bool want_iomap_res;
344 bool msi_enabled;
345 bool msix_enabled;
346 phys_addr_t rom;
347 size_t romlen;
348 struct msi_desc **msi_desc;
349 char *path_name;
350 spinlock_t pcie_cap_lock;
351
352 TAILQ_HEAD(, pci_mmio_region) mmio;
353 };
354
355 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name);
356 int pci_alloc_irq_vectors(struct pci_dev *pdev, int minv, int maxv,
357 unsigned int flags);
358 bool pci_device_is_present(struct pci_dev *pdev);
359
360 int linuxkpi_pcim_enable_device(struct pci_dev *pdev);
361 void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev);
362 void *linuxkpi_pci_iomap_range(struct pci_dev *pdev, int mmio_bar,
363 unsigned long mmio_off, unsigned long mmio_size);
364 void *linuxkpi_pci_iomap(struct pci_dev *pdev, int mmio_bar, int mmio_size);
365 void linuxkpi_pci_iounmap(struct pci_dev *pdev, void *res);
366 int linuxkpi_pcim_iomap_regions(struct pci_dev *pdev, uint32_t mask,
367 const char *name);
368 int linuxkpi_pci_request_regions(struct pci_dev *pdev, const char *res_name);
369 void linuxkpi_pci_release_region(struct pci_dev *pdev, int bar);
370 void linuxkpi_pci_release_regions(struct pci_dev *pdev);
371 int linuxkpi_pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries,
372 int nreq);
373
374 /* Internal helper function(s). */
375 struct pci_dev *lkpinew_pci_dev(device_t);
376 void lkpi_pci_devres_release(struct device *, void *);
377 struct pci_dev *lkpi_pci_get_device(uint16_t, uint16_t, struct pci_dev *);
378 struct msi_desc *lkpi_pci_msi_desc_alloc(int);
379 struct device *lkpi_pci_find_irq_dev(unsigned int irq);
380 int _lkpi_pci_enable_msi_range(struct pci_dev *pdev, int minvec, int maxvec);
381
382 #define pci_err(pdev, fmt, ...) \
383 dev_err(&(pdev)->dev, fmt, __VA_ARGS__)
384
385 static inline bool
dev_is_pci(struct device * dev)386 dev_is_pci(struct device *dev)
387 {
388
389 return (device_get_devclass(dev->bsddev) == devclass_find("pci"));
390 }
391
392 static inline uint16_t
pci_dev_id(struct pci_dev * pdev)393 pci_dev_id(struct pci_dev *pdev)
394 {
395 return (PCI_DEVID(pdev->bus->number, pdev->devfn));
396 }
397
398 static inline int
pci_resource_type(struct pci_dev * pdev,int bar)399 pci_resource_type(struct pci_dev *pdev, int bar)
400 {
401 struct pci_map *pm;
402
403 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
404 if (!pm)
405 return (-1);
406
407 if (PCI_BAR_IO(pm->pm_value))
408 return (SYS_RES_IOPORT);
409 else
410 return (SYS_RES_MEMORY);
411 }
412
413 /*
414 * All drivers just seem to want to inspect the type not flags.
415 */
416 static inline int
pci_resource_flags(struct pci_dev * pdev,int bar)417 pci_resource_flags(struct pci_dev *pdev, int bar)
418 {
419 int type;
420
421 type = pci_resource_type(pdev, bar);
422 if (type < 0)
423 return (0);
424 return (1 << type);
425 }
426
427 static inline const char *
pci_name(struct pci_dev * d)428 pci_name(struct pci_dev *d)
429 {
430 return d->path_name;
431 }
432
433 static inline void *
pci_get_drvdata(struct pci_dev * pdev)434 pci_get_drvdata(struct pci_dev *pdev)
435 {
436
437 return dev_get_drvdata(&pdev->dev);
438 }
439
440 static inline void
pci_set_drvdata(struct pci_dev * pdev,void * data)441 pci_set_drvdata(struct pci_dev *pdev, void *data)
442 {
443
444 dev_set_drvdata(&pdev->dev, data);
445 }
446
447 static inline struct pci_dev *
pci_dev_get(struct pci_dev * pdev)448 pci_dev_get(struct pci_dev *pdev)
449 {
450
451 if (pdev != NULL)
452 get_device(&pdev->dev);
453 return (pdev);
454 }
455
456 static __inline void
pci_dev_put(struct pci_dev * pdev)457 pci_dev_put(struct pci_dev *pdev)
458 {
459
460 if (pdev != NULL)
461 put_device(&pdev->dev);
462 }
463
464 static inline int
pci_enable_device(struct pci_dev * pdev)465 pci_enable_device(struct pci_dev *pdev)
466 {
467
468 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
469 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
470 return (0);
471 }
472
473 static inline void
pci_disable_device(struct pci_dev * pdev)474 pci_disable_device(struct pci_dev *pdev)
475 {
476
477 pci_disable_busmaster(pdev->dev.bsddev);
478 }
479
480 static inline int
pci_set_master(struct pci_dev * pdev)481 pci_set_master(struct pci_dev *pdev)
482 {
483
484 pci_enable_busmaster(pdev->dev.bsddev);
485 return (0);
486 }
487
488 static inline int
pci_set_power_state(struct pci_dev * pdev,int state)489 pci_set_power_state(struct pci_dev *pdev, int state)
490 {
491
492 pci_set_powerstate(pdev->dev.bsddev, state);
493 return (0);
494 }
495
496 static inline int
pci_clear_master(struct pci_dev * pdev)497 pci_clear_master(struct pci_dev *pdev)
498 {
499
500 pci_disable_busmaster(pdev->dev.bsddev);
501 return (0);
502 }
503
504 static inline bool
pci_is_root_bus(struct pci_bus * pbus)505 pci_is_root_bus(struct pci_bus *pbus)
506 {
507
508 return (pbus->self == NULL);
509 }
510
511 static inline struct pci_dev *
pci_upstream_bridge(struct pci_dev * pdev)512 pci_upstream_bridge(struct pci_dev *pdev)
513 {
514
515 if (pci_is_root_bus(pdev->bus))
516 return (NULL);
517
518 /*
519 * If we do not have a (proper) "upstream bridge" set, e.g., we point
520 * to ourselves, try to handle this case on the fly like we do
521 * for pcie_find_root_port().
522 */
523 if (pdev == pdev->bus->self) {
524 device_t bridge;
525
526 /*
527 * In the case of DRM drivers, the passed device is a child of
528 * `vgapci`. We want to start the lookup from `vgapci`, so the
529 * parent of the passed `drmn`.
530 *
531 * We can use the `isdrm` flag to determine this.
532 */
533 bridge = pdev->dev.bsddev;
534 if (pdev->pdrv != NULL && pdev->pdrv->isdrm)
535 bridge = device_get_parent(bridge);
536 if (bridge == NULL)
537 goto done;
538
539 bridge = device_get_parent(bridge);
540 if (bridge == NULL)
541 goto done;
542 bridge = device_get_parent(bridge);
543 if (bridge == NULL)
544 goto done;
545 if (device_get_devclass(device_get_parent(bridge)) !=
546 devclass_find("pci"))
547 goto done;
548
549 /*
550 * "bridge" is a PCI-to-PCI bridge. Create a Linux pci_dev
551 * for it so it can be returned.
552 */
553 pdev->bus->self = lkpinew_pci_dev(bridge);
554 }
555 done:
556 return (pdev->bus->self);
557 }
558
559 #define pci_release_region(pdev, bar) linuxkpi_pci_release_region(pdev, bar)
560 #define pci_release_regions(pdev) linuxkpi_pci_release_regions(pdev)
561 #define pci_request_regions(pdev, res_name) \
562 linuxkpi_pci_request_regions(pdev, res_name)
563
564 static inline void
lkpi_pci_disable_msix(struct pci_dev * pdev)565 lkpi_pci_disable_msix(struct pci_dev *pdev)
566 {
567
568 pci_release_msi(pdev->dev.bsddev);
569
570 /*
571 * The MSIX IRQ numbers associated with this PCI device are no
572 * longer valid and might be re-assigned. Make sure
573 * lkpi_pci_find_irq_dev() does no longer see them by
574 * resetting their references to zero:
575 */
576 pdev->dev.irq_start = 0;
577 pdev->dev.irq_end = 0;
578 pdev->msix_enabled = false;
579 }
580 /* Only for consistency. No conflict on that one. */
581 #define pci_disable_msix(pdev) lkpi_pci_disable_msix(pdev)
582
583 static inline void
lkpi_pci_disable_msi(struct pci_dev * pdev)584 lkpi_pci_disable_msi(struct pci_dev *pdev)
585 {
586
587 pci_release_msi(pdev->dev.bsddev);
588
589 pdev->dev.irq_start = 0;
590 pdev->dev.irq_end = 0;
591 pdev->irq = pdev->dev.irq;
592 pdev->msi_enabled = false;
593 }
594 #define pci_disable_msi(pdev) lkpi_pci_disable_msi(pdev)
595 #define pci_free_irq_vectors(pdev) lkpi_pci_disable_msi(pdev)
596
597 unsigned long pci_resource_start(struct pci_dev *pdev, int bar);
598 unsigned long pci_resource_len(struct pci_dev *pdev, int bar);
599
600 static inline bus_addr_t
pci_bus_address(struct pci_dev * pdev,int bar)601 pci_bus_address(struct pci_dev *pdev, int bar)
602 {
603
604 return (pci_resource_start(pdev, bar));
605 }
606
607 #define PCI_CAP_ID_EXP PCIY_EXPRESS
608 #define PCI_CAP_ID_PCIX PCIY_PCIX
609 #define PCI_CAP_ID_AGP PCIY_AGP
610 #define PCI_CAP_ID_PM PCIY_PMG
611
612 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
613 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
614 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
615 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
616 #define PCI_EXP_LNKSTA PCIER_LINK_STA
617
618 static inline int
pci_find_capability(struct pci_dev * pdev,int capid)619 pci_find_capability(struct pci_dev *pdev, int capid)
620 {
621 int reg;
622
623 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
624 return (0);
625 return (reg);
626 }
627
pci_pcie_cap(struct pci_dev * dev)628 static inline int pci_pcie_cap(struct pci_dev *dev)
629 {
630 return pci_find_capability(dev, PCI_CAP_ID_EXP);
631 }
632
633 static inline int
pci_find_ext_capability(struct pci_dev * pdev,int capid)634 pci_find_ext_capability(struct pci_dev *pdev, int capid)
635 {
636 int reg;
637
638 if (pci_find_extcap(pdev->dev.bsddev, capid, ®))
639 return (0);
640 return (reg);
641 }
642
643 #define PCIM_PCAP_PME_SHIFT 11
644 static __inline bool
pci_pme_capable(struct pci_dev * pdev,uint32_t flag)645 pci_pme_capable(struct pci_dev *pdev, uint32_t flag)
646 {
647 struct pci_devinfo *dinfo;
648 pcicfgregs *cfg;
649
650 if (flag > (PCIM_PCAP_D3PME_COLD >> PCIM_PCAP_PME_SHIFT))
651 return (false);
652
653 dinfo = device_get_ivars(pdev->dev.bsddev);
654 cfg = &dinfo->cfg;
655
656 if (cfg->pp.pp_cap == 0)
657 return (false);
658
659 if ((cfg->pp.pp_cap & (1 << (PCIM_PCAP_PME_SHIFT + flag))) != 0)
660 return (true);
661
662 return (false);
663 }
664
665 static inline int
pci_disable_link_state(struct pci_dev * pdev,uint32_t flags)666 pci_disable_link_state(struct pci_dev *pdev, uint32_t flags)
667 {
668
669 if (!pci_enable_aspm)
670 return (-EPERM);
671
672 return (-ENXIO);
673 }
674
675 static inline int
pci_read_config_byte(const struct pci_dev * pdev,int where,u8 * val)676 pci_read_config_byte(const struct pci_dev *pdev, int where, u8 *val)
677 {
678
679 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
680 return (0);
681 }
682
683 static inline int
pci_read_config_word(const struct pci_dev * pdev,int where,u16 * val)684 pci_read_config_word(const struct pci_dev *pdev, int where, u16 *val)
685 {
686
687 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
688 return (0);
689 }
690
691 static inline int
pci_read_config_dword(const struct pci_dev * pdev,int where,u32 * val)692 pci_read_config_dword(const struct pci_dev *pdev, int where, u32 *val)
693 {
694
695 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
696 return (0);
697 }
698
699 static inline int
pci_write_config_byte(const struct pci_dev * pdev,int where,u8 val)700 pci_write_config_byte(const struct pci_dev *pdev, int where, u8 val)
701 {
702
703 pci_write_config(pdev->dev.bsddev, where, val, 1);
704 return (0);
705 }
706
707 static inline int
pci_write_config_word(const struct pci_dev * pdev,int where,u16 val)708 pci_write_config_word(const struct pci_dev *pdev, int where, u16 val)
709 {
710
711 pci_write_config(pdev->dev.bsddev, where, val, 2);
712 return (0);
713 }
714
715 static inline int
pci_write_config_dword(const struct pci_dev * pdev,int where,u32 val)716 pci_write_config_dword(const struct pci_dev *pdev, int where, u32 val)
717 {
718
719 pci_write_config(pdev->dev.bsddev, where, val, 4);
720 return (0);
721 }
722
723 int linux_pci_register_driver(struct pci_driver *pdrv);
724 int linux_pci_register_drm_driver(struct pci_driver *pdrv);
725 void linux_pci_unregister_driver(struct pci_driver *pdrv);
726 void linux_pci_unregister_drm_driver(struct pci_driver *pdrv);
727
728 #define pci_register_driver(pdrv) linux_pci_register_driver(pdrv)
729 #define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv)
730
731 /*
732 * Enable msix, positive errors indicate actual number of available
733 * vectors. Negative errors are failures.
734 *
735 * NB: define added to prevent this definition of pci_enable_msix from
736 * clashing with the native FreeBSD version.
737 */
738 #define pci_enable_msix(...) linuxkpi_pci_enable_msix(__VA_ARGS__)
739
740 #define pci_enable_msix_range(...) \
741 linux_pci_enable_msix_range(__VA_ARGS__)
742
743 static inline int
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)744 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
745 int minvec, int maxvec)
746 {
747 int nvec = maxvec;
748 int rc;
749
750 if (maxvec < minvec)
751 return (-ERANGE);
752
753 do {
754 rc = pci_enable_msix(dev, entries, nvec);
755 if (rc < 0) {
756 return (rc);
757 } else if (rc > 0) {
758 if (rc < minvec)
759 return (-ENOSPC);
760 nvec = rc;
761 }
762 } while (rc);
763 return (nvec);
764 }
765
766 #define pci_enable_msi(pdev) \
767 linux_pci_enable_msi(pdev)
768
769 static inline int
pci_enable_msi(struct pci_dev * pdev)770 pci_enable_msi(struct pci_dev *pdev)
771 {
772
773 return (_lkpi_pci_enable_msi_range(pdev, 1, 1));
774 }
775
776 static inline int
pci_channel_offline(struct pci_dev * pdev)777 pci_channel_offline(struct pci_dev *pdev)
778 {
779
780 return (pci_read_config(pdev->dev.bsddev, PCIR_VENDOR, 2) == PCIV_INVALID);
781 }
782
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)783 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
784 {
785 return -ENODEV;
786 }
787
pci_disable_sriov(struct pci_dev * dev)788 static inline void pci_disable_sriov(struct pci_dev *dev)
789 {
790 }
791
792 #define pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size) \
793 linuxkpi_pci_iomap_range(pdev, mmio_bar, mmio_off, mmio_size)
794 #define pci_iomap(pdev, mmio_bar, mmio_size) \
795 linuxkpi_pci_iomap(pdev, mmio_bar, mmio_size)
796 #define pci_iounmap(pdev, res) linuxkpi_pci_iounmap(pdev, res)
797
798 static inline void
lkpi_pci_save_state(struct pci_dev * pdev)799 lkpi_pci_save_state(struct pci_dev *pdev)
800 {
801
802 pci_save_state(pdev->dev.bsddev);
803 }
804
805 static inline void
lkpi_pci_restore_state(struct pci_dev * pdev)806 lkpi_pci_restore_state(struct pci_dev *pdev)
807 {
808
809 pci_restore_state(pdev->dev.bsddev);
810 }
811
812 #define pci_save_state(dev) lkpi_pci_save_state(dev)
813 #define pci_restore_state(dev) lkpi_pci_restore_state(dev)
814
815 static inline int
pci_reset_function(struct pci_dev * pdev)816 pci_reset_function(struct pci_dev *pdev)
817 {
818
819 return (-ENOSYS);
820 }
821
822 #define DEFINE_PCI_DEVICE_TABLE(_table) \
823 const struct pci_device_id _table[] __devinitdata
824
825 /* XXX This should not be necessary. */
826 #define pcix_set_mmrbc(d, v) 0
827 #define pcix_get_max_mmrbc(d) 0
828 #define pcie_set_readrq(d, v) pci_set_max_read_req((d)->dev.bsddev, (v))
829
830 #define PCI_DMA_BIDIRECTIONAL 0
831 #define PCI_DMA_TODEVICE 1
832 #define PCI_DMA_FROMDEVICE 2
833 #define PCI_DMA_NONE 3
834
835 #define pci_pool dma_pool
836 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
837 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
838 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
839 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
840 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
841 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
842 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
843 _size, _vaddr, _dma_handle)
844 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
845 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
846 _sg, _nents, (enum dma_data_direction)_dir)
847 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
848 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
849 (_ptr), (_size), (enum dma_data_direction)_dir)
850 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
851 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
852 _addr, _size, (enum dma_data_direction)_dir)
853 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
854 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
855 _sg, _nents, (enum dma_data_direction)_dir)
856 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
857 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
858 _offset, _size, (enum dma_data_direction)_dir)
859 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
860 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
861 _dma_address, _size, (enum dma_data_direction)_dir)
862 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
863 #define pci_dma_mapping_error(_pdev, _dma_addr) \
864 dma_mapping_error(&(_pdev)->dev, _dma_addr)
865 #define pci_set_consistent_dma_mask(_pdev, _mask) \
866 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
867 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
868 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
869 #define pci_unmap_addr dma_unmap_addr
870 #define pci_unmap_addr_set dma_unmap_addr_set
871 #define pci_unmap_len dma_unmap_len
872 #define pci_unmap_len_set dma_unmap_len_set
873
874 typedef unsigned int __bitwise pci_channel_state_t;
875 typedef unsigned int __bitwise pci_ers_result_t;
876
877 enum pci_channel_state {
878 pci_channel_io_normal = 1,
879 pci_channel_io_frozen = 2,
880 pci_channel_io_perm_failure = 3,
881 };
882
883 enum pci_ers_result {
884 PCI_ERS_RESULT_NONE = 1,
885 PCI_ERS_RESULT_CAN_RECOVER = 2,
886 PCI_ERS_RESULT_NEED_RESET = 3,
887 PCI_ERS_RESULT_DISCONNECT = 4,
888 PCI_ERS_RESULT_RECOVERED = 5,
889 };
890
891 /* PCI bus error event callbacks */
892 struct pci_error_handlers {
893 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
894 enum pci_channel_state error);
895 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
896 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
897 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
898 void (*resume)(struct pci_dev *dev);
899 };
900
901 /* FreeBSD does not support SRIOV - yet */
pci_physfn(struct pci_dev * dev)902 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
903 {
904 return dev;
905 }
906
pci_is_pcie(struct pci_dev * dev)907 static inline bool pci_is_pcie(struct pci_dev *dev)
908 {
909 return !!pci_pcie_cap(dev);
910 }
911
pcie_flags_reg(struct pci_dev * dev)912 static inline u16 pcie_flags_reg(struct pci_dev *dev)
913 {
914 int pos;
915 u16 reg16;
916
917 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
918 if (!pos)
919 return 0;
920
921 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
922
923 return reg16;
924 }
925
pci_pcie_type(struct pci_dev * dev)926 static inline int pci_pcie_type(struct pci_dev *dev)
927 {
928 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
929 }
930
pcie_cap_version(struct pci_dev * dev)931 static inline int pcie_cap_version(struct pci_dev *dev)
932 {
933 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
934 }
935
pcie_cap_has_lnkctl(struct pci_dev * dev)936 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
937 {
938 int type = pci_pcie_type(dev);
939
940 return pcie_cap_version(dev) > 1 ||
941 type == PCI_EXP_TYPE_ROOT_PORT ||
942 type == PCI_EXP_TYPE_ENDPOINT ||
943 type == PCI_EXP_TYPE_LEG_END;
944 }
945
pcie_cap_has_devctl(const struct pci_dev * dev)946 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
947 {
948 return true;
949 }
950
pcie_cap_has_sltctl(struct pci_dev * dev)951 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
952 {
953 int type = pci_pcie_type(dev);
954
955 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
956 (type == PCI_EXP_TYPE_DOWNSTREAM &&
957 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
958 }
959
pcie_cap_has_rtctl(struct pci_dev * dev)960 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
961 {
962 int type = pci_pcie_type(dev);
963
964 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT ||
965 type == PCI_EXP_TYPE_RC_EC;
966 }
967
pcie_capability_reg_implemented(struct pci_dev * dev,int pos)968 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
969 {
970 if (!pci_is_pcie(dev))
971 return false;
972
973 switch (pos) {
974 case PCI_EXP_FLAGS_TYPE:
975 return true;
976 case PCI_EXP_DEVCAP:
977 case PCI_EXP_DEVCTL:
978 case PCI_EXP_DEVSTA:
979 return pcie_cap_has_devctl(dev);
980 case PCI_EXP_LNKCAP:
981 case PCI_EXP_LNKCTL:
982 case PCI_EXP_LNKSTA:
983 return pcie_cap_has_lnkctl(dev);
984 case PCI_EXP_SLTCAP:
985 case PCI_EXP_SLTCTL:
986 case PCI_EXP_SLTSTA:
987 return pcie_cap_has_sltctl(dev);
988 case PCI_EXP_RTCTL:
989 case PCI_EXP_RTCAP:
990 case PCI_EXP_RTSTA:
991 return pcie_cap_has_rtctl(dev);
992 case PCI_EXP_DEVCAP2:
993 case PCI_EXP_DEVCTL2:
994 case PCI_EXP_LNKCAP2:
995 case PCI_EXP_LNKCTL2:
996 case PCI_EXP_LNKSTA2:
997 return pcie_cap_version(dev) > 1;
998 default:
999 return false;
1000 }
1001 }
1002
1003 static inline int
pcie_capability_read_dword(struct pci_dev * dev,int pos,u32 * dst)1004 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
1005 {
1006 *dst = 0;
1007 if (pos & 3)
1008 return -EINVAL;
1009
1010 if (!pcie_capability_reg_implemented(dev, pos))
1011 return -EINVAL;
1012
1013 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
1014 }
1015
1016 static inline int
pcie_capability_read_word(struct pci_dev * dev,int pos,u16 * dst)1017 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
1018 {
1019 *dst = 0;
1020 if (pos & 3)
1021 return -EINVAL;
1022
1023 if (!pcie_capability_reg_implemented(dev, pos))
1024 return -EINVAL;
1025
1026 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
1027 }
1028
1029 static inline int
pcie_capability_write_word(struct pci_dev * dev,int pos,u16 val)1030 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
1031 {
1032 if (pos & 1)
1033 return -EINVAL;
1034
1035 if (!pcie_capability_reg_implemented(dev, pos))
1036 return 0;
1037
1038 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
1039 }
1040
1041 static inline int
pcie_capability_clear_and_set_word(struct pci_dev * dev,int pos,uint16_t clear,uint16_t set)1042 pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1043 uint16_t clear, uint16_t set)
1044 {
1045 int error;
1046 uint16_t v;
1047
1048 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL)
1049 spin_lock(&dev->pcie_cap_lock);
1050
1051 error = pcie_capability_read_word(dev, pos, &v);
1052 if (error == 0) {
1053 v &= ~clear;
1054 v |= set;
1055 error = pcie_capability_write_word(dev, pos, v);
1056 }
1057
1058 if (pos == PCI_EXP_LNKCTL || pos == PCI_EXP_RTCTL)
1059 spin_unlock(&dev->pcie_cap_lock);
1060
1061 return (error);
1062 }
1063
1064 static inline int
pcie_capability_set_word(struct pci_dev * dev,int pos,uint16_t val)1065 pcie_capability_set_word(struct pci_dev *dev, int pos, uint16_t val)
1066 {
1067 return (pcie_capability_clear_and_set_word(dev, pos, 0, val));
1068 }
1069
1070 static inline int
pcie_capability_clear_word(struct pci_dev * dev,int pos,uint16_t val)1071 pcie_capability_clear_word(struct pci_dev *dev, int pos, uint16_t val)
1072 {
1073 return (pcie_capability_clear_and_set_word(dev, pos, val, 0));
1074 }
1075
pcie_get_minimum_link(struct pci_dev * dev,enum pci_bus_speed * speed,enum pcie_link_width * width)1076 static inline int pcie_get_minimum_link(struct pci_dev *dev,
1077 enum pci_bus_speed *speed, enum pcie_link_width *width)
1078 {
1079 *speed = PCI_SPEED_UNKNOWN;
1080 *width = PCIE_LNK_WIDTH_UNKNOWN;
1081 return (0);
1082 }
1083
1084 static inline int
pci_num_vf(struct pci_dev * dev)1085 pci_num_vf(struct pci_dev *dev)
1086 {
1087 return (0);
1088 }
1089
1090 static inline enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev * dev)1091 pcie_get_speed_cap(struct pci_dev *dev)
1092 {
1093 device_t root;
1094 uint32_t lnkcap, lnkcap2;
1095 int error, pos;
1096
1097 root = device_get_parent(dev->dev.bsddev);
1098 if (root == NULL)
1099 return (PCI_SPEED_UNKNOWN);
1100 root = device_get_parent(root);
1101 if (root == NULL)
1102 return (PCI_SPEED_UNKNOWN);
1103 root = device_get_parent(root);
1104 if (root == NULL)
1105 return (PCI_SPEED_UNKNOWN);
1106
1107 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA ||
1108 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS)
1109 return (PCI_SPEED_UNKNOWN);
1110
1111 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0)
1112 return (PCI_SPEED_UNKNOWN);
1113
1114 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4);
1115
1116 if (lnkcap2) { /* PCIe r3.0-compliant */
1117 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
1118 return (PCIE_SPEED_2_5GT);
1119 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
1120 return (PCIE_SPEED_5_0GT);
1121 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
1122 return (PCIE_SPEED_8_0GT);
1123 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
1124 return (PCIE_SPEED_16_0GT);
1125 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB)
1126 return (PCIE_SPEED_32_0GT);
1127 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_64_0GB)
1128 return (PCIE_SPEED_64_0GT);
1129 } else { /* pre-r3.0 */
1130 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4);
1131 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
1132 return (PCIE_SPEED_2_5GT);
1133 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
1134 return (PCIE_SPEED_5_0GT);
1135 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
1136 return (PCIE_SPEED_8_0GT);
1137 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
1138 return (PCIE_SPEED_16_0GT);
1139 if (lnkcap & PCI_EXP_LNKCAP_SLS_32_0GB)
1140 return (PCIE_SPEED_32_0GT);
1141 if (lnkcap & PCI_EXP_LNKCAP_SLS_64_0GB)
1142 return (PCIE_SPEED_64_0GT);
1143 }
1144 return (PCI_SPEED_UNKNOWN);
1145 }
1146
1147 static inline enum pcie_link_width
pcie_get_width_cap(struct pci_dev * dev)1148 pcie_get_width_cap(struct pci_dev *dev)
1149 {
1150 uint32_t lnkcap;
1151
1152 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
1153 if (lnkcap)
1154 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4);
1155
1156 return (PCIE_LNK_WIDTH_UNKNOWN);
1157 }
1158
1159 static inline int
pcie_get_mps(struct pci_dev * dev)1160 pcie_get_mps(struct pci_dev *dev)
1161 {
1162 return (pci_get_max_payload(dev->dev.bsddev));
1163 }
1164
1165 static inline uint32_t
PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)1166 PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd)
1167 {
1168
1169 switch(spd) {
1170 case PCIE_SPEED_64_0GT:
1171 return (64000 * 128 / 130);
1172 case PCIE_SPEED_32_0GT:
1173 return (32000 * 128 / 130);
1174 case PCIE_SPEED_16_0GT:
1175 return (16000 * 128 / 130);
1176 case PCIE_SPEED_8_0GT:
1177 return (8000 * 128 / 130);
1178 case PCIE_SPEED_5_0GT:
1179 return (5000 * 8 / 10);
1180 case PCIE_SPEED_2_5GT:
1181 return (2500 * 8 / 10);
1182 default:
1183 return (0);
1184 }
1185 }
1186
1187 static inline uint32_t
pcie_bandwidth_available(struct pci_dev * pdev,struct pci_dev ** limiting,enum pci_bus_speed * speed,enum pcie_link_width * width)1188 pcie_bandwidth_available(struct pci_dev *pdev,
1189 struct pci_dev **limiting,
1190 enum pci_bus_speed *speed,
1191 enum pcie_link_width *width)
1192 {
1193 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev);
1194 enum pcie_link_width nwidth = pcie_get_width_cap(pdev);
1195
1196 if (speed)
1197 *speed = nspeed;
1198 if (width)
1199 *width = nwidth;
1200
1201 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed));
1202 }
1203
1204 static inline bool
pcie_aspm_enabled(struct pci_dev * pdev)1205 pcie_aspm_enabled(struct pci_dev *pdev)
1206 {
1207 return (false);
1208 }
1209
1210 static inline struct pci_dev *
pcie_find_root_port(struct pci_dev * pdev)1211 pcie_find_root_port(struct pci_dev *pdev)
1212 {
1213 device_t root;
1214
1215 if (pdev->root != NULL)
1216 return (pdev->root);
1217
1218 root = pci_find_pcie_root_port(pdev->dev.bsddev);
1219 if (root == NULL)
1220 return (NULL);
1221
1222 pdev->root = lkpinew_pci_dev(root);
1223 return (pdev->root);
1224 }
1225
1226 /* This is needed when people rip out the device "HotPlug". */
1227 static inline void
pci_lock_rescan_remove(void)1228 pci_lock_rescan_remove(void)
1229 {
1230 }
1231
1232 static inline void
pci_unlock_rescan_remove(void)1233 pci_unlock_rescan_remove(void)
1234 {
1235 }
1236
1237 static __inline void
pci_stop_and_remove_bus_device(struct pci_dev * pdev)1238 pci_stop_and_remove_bus_device(struct pci_dev *pdev)
1239 {
1240 }
1241
1242 static inline int
pci_rescan_bus(struct pci_bus * pbus)1243 pci_rescan_bus(struct pci_bus *pbus)
1244 {
1245 device_t *devlist, parent;
1246 int devcount, error;
1247
1248 if (!device_is_attached(pbus->self->dev.bsddev))
1249 return (0);
1250 /* pci_rescan_method() will work on the pcib (parent). */
1251 error = BUS_RESCAN(pbus->self->dev.bsddev);
1252 if (error != 0)
1253 return (0);
1254
1255 parent = device_get_parent(pbus->self->dev.bsddev);
1256 error = device_get_children(parent, &devlist, &devcount);
1257 if (error != 0)
1258 return (0);
1259 if (devcount != 0)
1260 free(devlist, M_TEMP);
1261
1262 return (devcount);
1263 }
1264
1265 /*
1266 * The following functions can be used to attach/detach the LinuxKPI's
1267 * PCI device runtime. The pci_driver and pci_device_id pointer is
1268 * allowed to be NULL. Other pointers must be all valid.
1269 * The pci_dev structure should be zero-initialized before passed
1270 * to the linux_pci_attach_device function.
1271 */
1272 extern int linux_pci_attach_device(device_t, struct pci_driver *,
1273 const struct pci_device_id *, struct pci_dev *);
1274 extern int linux_pci_detach_device(struct pci_dev *);
1275
1276 static inline int
pci_dev_present(const struct pci_device_id * cur)1277 pci_dev_present(const struct pci_device_id *cur)
1278 {
1279 while (cur != NULL && (cur->vendor || cur->device)) {
1280 if (pci_find_device(cur->vendor, cur->device) != NULL) {
1281 return (1);
1282 }
1283 cur++;
1284 }
1285 return (0);
1286 }
1287
1288 static inline const struct pci_device_id *
pci_match_id(const struct pci_device_id * ids,struct pci_dev * pdev)1289 pci_match_id(const struct pci_device_id *ids, struct pci_dev *pdev)
1290 {
1291 if (ids == NULL)
1292 return (NULL);
1293
1294 for (;
1295 ids->vendor != 0 || ids->subvendor != 0 || ids->class_mask != 0;
1296 ids++)
1297 if ((ids->vendor == PCI_ANY_ID ||
1298 ids->vendor == pdev->vendor) &&
1299 (ids->device == PCI_ANY_ID ||
1300 ids->device == pdev->device) &&
1301 (ids->subvendor == PCI_ANY_ID ||
1302 ids->subvendor == pdev->subsystem_vendor) &&
1303 (ids->subdevice == PCI_ANY_ID ||
1304 ids->subdevice == pdev->subsystem_device) &&
1305 ((ids->class ^ pdev->class) & ids->class_mask) == 0)
1306 return (ids);
1307
1308 return (NULL);
1309 }
1310
1311 struct pci_dev *lkpi_pci_get_domain_bus_and_slot(int domain,
1312 unsigned int bus, unsigned int devfn);
1313 #define pci_get_domain_bus_and_slot(domain, bus, devfn) \
1314 lkpi_pci_get_domain_bus_and_slot(domain, bus, devfn)
1315
1316 static inline int
pci_domain_nr(struct pci_bus * pbus)1317 pci_domain_nr(struct pci_bus *pbus)
1318 {
1319
1320 return (pbus->domain);
1321 }
1322
1323 static inline int
pci_bus_read_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t * val,int len)1324 pci_bus_read_config(struct pci_bus *bus, unsigned int devfn,
1325 int pos, uint32_t *val, int len)
1326 {
1327
1328 *val = pci_read_config(bus->self->dev.bsddev, pos, len);
1329 return (0);
1330 }
1331
1332 static inline int
pci_bus_read_config_word(struct pci_bus * bus,unsigned int devfn,int pos,u16 * val)1333 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int pos, u16 *val)
1334 {
1335 uint32_t tmp;
1336 int ret;
1337
1338 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 2);
1339 *val = (u16)tmp;
1340 return (ret);
1341 }
1342
1343 static inline int
pci_bus_read_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,u8 * val)1344 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int pos, u8 *val)
1345 {
1346 uint32_t tmp;
1347 int ret;
1348
1349 ret = pci_bus_read_config(bus, devfn, pos, &tmp, 1);
1350 *val = (u8)tmp;
1351 return (ret);
1352 }
1353
1354 static inline int
pci_bus_write_config(struct pci_bus * bus,unsigned int devfn,int pos,uint32_t val,int size)1355 pci_bus_write_config(struct pci_bus *bus, unsigned int devfn, int pos,
1356 uint32_t val, int size)
1357 {
1358
1359 pci_write_config(bus->self->dev.bsddev, pos, val, size);
1360 return (0);
1361 }
1362
1363 static inline int
pci_bus_write_config_byte(struct pci_bus * bus,unsigned int devfn,int pos,uint8_t val)1364 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, int pos,
1365 uint8_t val)
1366 {
1367 return (pci_bus_write_config(bus, devfn, pos, val, 1));
1368 }
1369
1370 static inline int
pci_bus_write_config_word(struct pci_bus * bus,unsigned int devfn,int pos,uint16_t val)1371 pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, int pos,
1372 uint16_t val)
1373 {
1374 return (pci_bus_write_config(bus, devfn, pos, val, 2));
1375 }
1376
1377 struct pci_dev *lkpi_pci_get_class(unsigned int class, struct pci_dev *from);
1378 #define pci_get_class(class, from) lkpi_pci_get_class(class, from)
1379 struct pci_dev *lkpi_pci_get_base_class(unsigned int class,
1380 struct pci_dev *from);
1381 #define pci_get_base_class(class, from) lkpi_pci_get_base_class(class, from)
1382
1383 /* -------------------------------------------------------------------------- */
1384
1385 #define pcim_enable_device(pdev) linuxkpi_pcim_enable_device(pdev)
1386 #define pcim_iomap_table(pdev) linuxkpi_pcim_iomap_table(pdev)
1387 #define pcim_iomap_regions(pdev, mask, name) \
1388 linuxkpi_pcim_iomap_regions(pdev, mask, name)
1389
1390 static inline int
pcim_iomap_regions_request_all(struct pci_dev * pdev,uint32_t mask,char * name)1391 pcim_iomap_regions_request_all(struct pci_dev *pdev, uint32_t mask, char *name)
1392 {
1393 uint32_t requests, req_mask;
1394 int bar, error;
1395
1396 /* Request all the BARs ("regions") we do not iomap. */
1397 req_mask = ((1 << (PCIR_MAX_BAR_0 + 1)) - 1) & ~mask;
1398 for (bar = requests = 0; requests != req_mask; bar++) {
1399 if ((req_mask & (1 << bar)) == 0)
1400 continue;
1401 error = pci_request_region(pdev, bar, name);
1402 if (error != 0 && error != -ENODEV)
1403 goto err;
1404 requests |= (1 << bar);
1405 }
1406
1407 error = pcim_iomap_regions(pdev, mask, name);
1408 if (error != 0)
1409 goto err;
1410
1411 return (0);
1412
1413 err:
1414 for (bar = PCIR_MAX_BAR_0; bar >= 0; bar--) {
1415 if ((requests & (1 << bar)) != 0)
1416 pci_release_region(pdev, bar);
1417 }
1418
1419 return (-EINVAL);
1420 }
1421
1422 /*
1423 * We cannot simply re-define pci_get_device() as we would normally do
1424 * and then hide it in linux_pci.c as too many semi-native drivers still
1425 * include linux/pci.h and run into the conflict with native PCI. Linux drivers
1426 * using pci_get_device() need to be changed to call linuxkpi_pci_get_device().
1427 */
1428 static inline struct pci_dev *
linuxkpi_pci_get_device(uint16_t vendor,uint16_t device,struct pci_dev * odev)1429 linuxkpi_pci_get_device(uint16_t vendor, uint16_t device, struct pci_dev *odev)
1430 {
1431
1432 return (lkpi_pci_get_device(vendor, device, odev));
1433 }
1434
1435 /* This is a FreeBSD extension so we can use bus_*(). */
1436 static inline void
linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev * pdev)1437 linuxkpi_pcim_want_to_use_bus_functions(struct pci_dev *pdev)
1438 {
1439 pdev->want_iomap_res = true;
1440 }
1441
1442 static inline bool
pci_is_thunderbolt_attached(struct pci_dev * pdev)1443 pci_is_thunderbolt_attached(struct pci_dev *pdev)
1444 {
1445
1446 return (false);
1447 }
1448
1449 static inline void *
pci_platform_rom(struct pci_dev * pdev,size_t * size)1450 pci_platform_rom(struct pci_dev *pdev, size_t *size)
1451 {
1452
1453 return (NULL);
1454 }
1455
1456 static inline void
pci_ignore_hotplug(struct pci_dev * pdev)1457 pci_ignore_hotplug(struct pci_dev *pdev)
1458 {
1459 }
1460
1461 static inline const char *
pci_power_name(pci_power_t state)1462 pci_power_name(pci_power_t state)
1463 {
1464 int pstate = state + 1;
1465
1466 if (pstate >= 0 && pstate < nitems(pci_power_names))
1467 return (pci_power_names[pstate]);
1468 else
1469 return (pci_power_names[0]);
1470 }
1471
1472 static inline int
pcie_get_readrq(struct pci_dev * dev)1473 pcie_get_readrq(struct pci_dev *dev)
1474 {
1475 u16 ctl;
1476
1477 if (pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl))
1478 return (-EINVAL);
1479
1480 return (128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12));
1481 }
1482
1483 static inline bool
pci_is_enabled(struct pci_dev * pdev)1484 pci_is_enabled(struct pci_dev *pdev)
1485 {
1486
1487 return ((pci_read_config(pdev->dev.bsddev, PCIR_COMMAND, 2) &
1488 PCIM_CMD_BUSMASTEREN) != 0);
1489 }
1490
1491 static inline int
pci_wait_for_pending_transaction(struct pci_dev * pdev)1492 pci_wait_for_pending_transaction(struct pci_dev *pdev)
1493 {
1494
1495 return (0);
1496 }
1497
1498 static inline int
pci_assign_resource(struct pci_dev * pdev,int bar)1499 pci_assign_resource(struct pci_dev *pdev, int bar)
1500 {
1501
1502 return (0);
1503 }
1504
1505 static inline int
pci_irq_vector(struct pci_dev * pdev,unsigned int vector)1506 pci_irq_vector(struct pci_dev *pdev, unsigned int vector)
1507 {
1508
1509 if (!pdev->msix_enabled && !pdev->msi_enabled) {
1510 if (vector != 0)
1511 return (-EINVAL);
1512 return (pdev->irq);
1513 }
1514
1515 if (pdev->msix_enabled || pdev->msi_enabled) {
1516 if ((pdev->dev.irq_start + vector) >= pdev->dev.irq_end)
1517 return (-EINVAL);
1518 return (pdev->dev.irq_start + vector);
1519 }
1520
1521 return (-ENXIO);
1522 }
1523
1524 static inline int
pci_wake_from_d3(struct pci_dev * pdev,bool enable)1525 pci_wake_from_d3(struct pci_dev *pdev, bool enable)
1526 {
1527
1528 pr_debug("%s: TODO\n", __func__);
1529 return (0);
1530 }
1531
1532 #endif /* _LINUXKPI_LINUX_PCI_H_ */
1533