Home
last modified time | relevance | path

Searched refs:opc2 (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Darm_acle.h779 #define __arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2) \ argument
780 __builtin_arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2)
786 #define __arm_mcr(coproc, opc1, value, CRn, CRm, opc2) \ argument
787 __builtin_arm_mcr(coproc, opc1, value, CRn, CRm, opc2)
788 #define __arm_mrc(coproc, opc1, CRn, CRm, opc2) \ argument
789 __builtin_arm_mrc(coproc, opc1, CRn, CRm, opc2)
797 #define __arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2) \ argument
798 __builtin_arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2)
806 #define __arm_cdp2(coproc, opc1, CRd, CRn, CRm, opc2) \ argument
807 __builtin_arm_cdp2(coproc, opc1, CRd, CRn, CRm, opc2)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
212 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
217 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
220 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
224 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
229 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
245 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
250 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
256 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
261 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.td5390 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5391 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5393 timm:$CRm, timm:$opc2)]>,
5399 bits<3> opc2;
5404 let Inst{7-5} = opc2;
5414 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5415 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5417 timm:$CRm, timm:$opc2)]>,
5424 bits<3> opc2;
5429 let Inst{7-5} = opc2;
[all …]
H A DARMInstrThumb2.td4605 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4614 bits<3> opc2;
4621 let Inst{7-5} = opc2;
4654 c_imm:$CRm, imm0_7:$opc2),
4656 timm:$CRm, timm:$opc2)]>,
4663 c_imm:$CRm, imm0_7:$opc2),
4665 timm:$CRm, timm:$opc2)]> {
4675 c_imm:$CRm, imm0_7:$opc2), []>;
4682 c_imm:$CRm, imm0_7:$opc2), []> {
4689 def : T2v6Pat<(int_arm_mrc timm:$cop, timm:$opc1, timm:$CRn, timm:$CRm, timm:$opc2),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrMMX.td51 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
65 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
H A DX86InstrSSE.td3579 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3602 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3611 multiclass PDI_binop_rmi_all<bits<8> opc, bits<8> opc2, Format ImmForm,
3618 defm V#NAME : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3622 defm V#NAME#Y : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3627 defm NAME : PDI_binop_rmi<opc, opc2, ImmForm, OpcodeStr, OpNode, OpNode2,
H A DX86InstrAVX512.td2945 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2953 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2955 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td2285 class BaseOneOperandData<bit sf, bit S, bits<5> opc2, bits<6> opc,
2298 let Inst{20-16} = opc2;
4807 class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
4817 let Inst{11-10} = opc2;
4847 class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
4849 : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> {
11469 bit opc1, bit opc2, RegisterOperand dst_reg,
11497 let Inst{12} = opc2;
11507 multiclass SIMDIndexedTiedComplexHSD<bit opc1, bit opc2, Operand rottype,
11510 def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
[all …]
H A DSVEInstrFormats.td2857 class sve_int_read_vl_a<bit op, bits<5> opc2, string asm, bit streaming_sve = 0b0>
2867 let Inst{20-16} = opc2{4-0};
H A DAArch64InstrInfo.td10003 // size opc opc2