1 /* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #ifndef Q_STRUCT_H 29 #define Q_STRUCT_H 30 31 #define __LITTLE_ENDIAN_BITFIELD 32 33 /* Load transaction types for reading segment bytes specified by 34 * NIC_SEND_GATHER_S[LD_TYPE]. 35 */ 36 enum nic_send_ld_type_e { 37 NIC_SEND_LD_TYPE_E_LDD = 0x0, 38 NIC_SEND_LD_TYPE_E_LDT = 0x1, 39 NIC_SEND_LD_TYPE_E_LDWB = 0x2, 40 NIC_SEND_LD_TYPE_E_ENUM_LAST = 0x3, 41 }; 42 43 enum ether_type_algorithm { 44 ETYPE_ALG_NONE = 0x0, 45 ETYPE_ALG_SKIP = 0x1, 46 ETYPE_ALG_ENDPARSE = 0x2, 47 ETYPE_ALG_VLAN = 0x3, 48 ETYPE_ALG_VLAN_STRIP = 0x4, 49 }; 50 51 enum layer3_type { 52 L3TYPE_NONE = 0x00, 53 L3TYPE_GRH = 0x01, 54 L3TYPE_IPV4 = 0x04, 55 L3TYPE_IPV4_OPTIONS = 0x05, 56 L3TYPE_IPV6 = 0x06, 57 L3TYPE_IPV6_OPTIONS = 0x07, 58 L3TYPE_ET_STOP = 0x0D, 59 L3TYPE_OTHER = 0x0E, 60 }; 61 62 enum layer4_type { 63 L4TYPE_NONE = 0x00, 64 L4TYPE_IPSEC_ESP = 0x01, 65 L4TYPE_IPFRAG = 0x02, 66 L4TYPE_IPCOMP = 0x03, 67 L4TYPE_TCP = 0x04, 68 L4TYPE_UDP = 0x05, 69 L4TYPE_SCTP = 0x06, 70 L4TYPE_GRE = 0x07, 71 L4TYPE_ROCE_BTH = 0x08, 72 L4TYPE_OTHER = 0x0E, 73 }; 74 75 /* CPI and RSSI configuration */ 76 enum cpi_algorithm_type { 77 CPI_ALG_NONE = 0x0, 78 CPI_ALG_VLAN = 0x1, 79 CPI_ALG_VLAN16 = 0x2, 80 CPI_ALG_DIFF = 0x3, 81 }; 82 83 enum rss_algorithm_type { 84 RSS_ALG_NONE = 0x00, 85 RSS_ALG_PORT = 0x01, 86 RSS_ALG_IP = 0x02, 87 RSS_ALG_TCP_IP = 0x03, 88 RSS_ALG_UDP_IP = 0x04, 89 RSS_ALG_SCTP_IP = 0x05, 90 RSS_ALG_GRE_IP = 0x06, 91 RSS_ALG_ROCE = 0x07, 92 }; 93 94 enum rss_hash_cfg { 95 RSS_HASH_L2ETC = 0x00, 96 RSS_HASH_IP = 0x01, 97 RSS_HASH_TCP = 0x02, 98 RSS_HASH_TCP_SYN_DIS = 0x03, 99 RSS_HASH_UDP = 0x04, 100 RSS_HASH_L4ETC = 0x05, 101 RSS_HASH_ROCE = 0x06, 102 RSS_L3_BIDI = 0x07, 103 RSS_L4_BIDI = 0x08, 104 }; 105 106 /* Completion queue entry types */ 107 enum cqe_type { 108 CQE_TYPE_INVALID = 0x0, 109 CQE_TYPE_RX = 0x2, 110 CQE_TYPE_RX_SPLIT = 0x3, 111 CQE_TYPE_RX_TCP = 0x4, 112 CQE_TYPE_SEND = 0x8, 113 CQE_TYPE_SEND_PTP = 0x9, 114 }; 115 116 enum cqe_rx_tcp_status { 117 CQE_RX_STATUS_VALID_TCP_CNXT = 0x00, 118 CQE_RX_STATUS_INVALID_TCP_CNXT = 0x0F, 119 }; 120 121 enum cqe_send_status { 122 CQE_SEND_STATUS_GOOD = 0x00, 123 CQE_SEND_STATUS_DESC_FAULT = 0x01, 124 CQE_SEND_STATUS_HDR_CONS_ERR = 0x11, 125 CQE_SEND_STATUS_SUBDESC_ERR = 0x12, 126 CQE_SEND_STATUS_IMM_SIZE_OFLOW = 0x80, 127 CQE_SEND_STATUS_CRC_SEQ_ERR = 0x81, 128 CQE_SEND_STATUS_DATA_SEQ_ERR = 0x82, 129 CQE_SEND_STATUS_MEM_SEQ_ERR = 0x83, 130 CQE_SEND_STATUS_LOCK_VIOL = 0x84, 131 CQE_SEND_STATUS_LOCK_UFLOW = 0x85, 132 CQE_SEND_STATUS_DATA_FAULT = 0x86, 133 CQE_SEND_STATUS_TSTMP_CONFLICT = 0x87, 134 CQE_SEND_STATUS_TSTMP_TIMEOUT = 0x88, 135 CQE_SEND_STATUS_MEM_FAULT = 0x89, 136 CQE_SEND_STATUS_CSUM_OVERLAP = 0x8A, 137 CQE_SEND_STATUS_CSUM_OVERFLOW = 0x8B, 138 }; 139 140 enum cqe_rx_tcp_end_reason { 141 CQE_RX_TCP_END_FIN_FLAG_DET = 0, 142 CQE_RX_TCP_END_INVALID_FLAG = 1, 143 CQE_RX_TCP_END_TIMEOUT = 2, 144 CQE_RX_TCP_END_OUT_OF_SEQ = 3, 145 CQE_RX_TCP_END_PKT_ERR = 4, 146 CQE_RX_TCP_END_QS_DISABLED = 0x0F, 147 }; 148 149 /* Packet protocol level error enumeration */ 150 enum cqe_rx_err_level { 151 CQE_RX_ERRLVL_RE = 0x0, 152 CQE_RX_ERRLVL_L2 = 0x1, 153 CQE_RX_ERRLVL_L3 = 0x2, 154 CQE_RX_ERRLVL_L4 = 0x3, 155 }; 156 157 /* Packet protocol level error type enumeration */ 158 enum cqe_rx_err_opcode { 159 CQE_RX_ERR_RE_NONE = 0x0, 160 CQE_RX_ERR_RE_PARTIAL = 0x1, 161 CQE_RX_ERR_RE_JABBER = 0x2, 162 CQE_RX_ERR_RE_FCS = 0x7, 163 CQE_RX_ERR_RE_TERMINATE = 0x9, 164 CQE_RX_ERR_RE_RX_CTL = 0xb, 165 CQE_RX_ERR_PREL2_ERR = 0x1f, 166 CQE_RX_ERR_L2_FRAGMENT = 0x20, 167 CQE_RX_ERR_L2_OVERRUN = 0x21, 168 CQE_RX_ERR_L2_PFCS = 0x22, 169 CQE_RX_ERR_L2_PUNY = 0x23, 170 CQE_RX_ERR_L2_MAL = 0x24, 171 CQE_RX_ERR_L2_OVERSIZE = 0x25, 172 CQE_RX_ERR_L2_UNDERSIZE = 0x26, 173 CQE_RX_ERR_L2_LENMISM = 0x27, 174 CQE_RX_ERR_L2_PCLP = 0x28, 175 CQE_RX_ERR_IP_NOT = 0x41, 176 CQE_RX_ERR_IP_CHK = 0x42, 177 CQE_RX_ERR_IP_MAL = 0x43, 178 CQE_RX_ERR_IP_MALD = 0x44, 179 CQE_RX_ERR_IP_HOP = 0x45, 180 CQE_RX_ERR_L3_ICRC = 0x46, 181 CQE_RX_ERR_L3_PCLP = 0x47, 182 CQE_RX_ERR_L4_MAL = 0x61, 183 CQE_RX_ERR_L4_CHK = 0x62, 184 CQE_RX_ERR_UDP_LEN = 0x63, 185 CQE_RX_ERR_L4_PORT = 0x64, 186 CQE_RX_ERR_TCP_FLAG = 0x65, 187 CQE_RX_ERR_TCP_OFFSET = 0x66, 188 CQE_RX_ERR_L4_PCLP = 0x67, 189 CQE_RX_ERR_RBDR_TRUNC = 0x70, 190 }; 191 192 struct cqe_rx_t { 193 #if defined(__BIG_ENDIAN_BITFIELD) 194 uint64_t cqe_type:4; /* W0 */ 195 uint64_t stdn_fault:1; 196 uint64_t rsvd0:1; 197 uint64_t rq_qs:7; 198 uint64_t rq_idx:3; 199 uint64_t rsvd1:12; 200 uint64_t rss_alg:4; 201 uint64_t rsvd2:4; 202 uint64_t rb_cnt:4; 203 uint64_t vlan_found:1; 204 uint64_t vlan_stripped:1; 205 uint64_t vlan2_found:1; 206 uint64_t vlan2_stripped:1; 207 uint64_t l4_type:4; 208 uint64_t l3_type:4; 209 uint64_t l2_present:1; 210 uint64_t err_level:3; 211 uint64_t err_opcode:8; 212 213 uint64_t pkt_len:16; /* W1 */ 214 uint64_t l2_ptr:8; 215 uint64_t l3_ptr:8; 216 uint64_t l4_ptr:8; 217 uint64_t cq_pkt_len:8; 218 uint64_t align_pad:3; 219 uint64_t rsvd3:1; 220 uint64_t chan:12; 221 222 uint64_t rss_tag:32; /* W2 */ 223 uint64_t vlan_tci:16; 224 uint64_t vlan_ptr:8; 225 uint64_t vlan2_ptr:8; 226 227 uint64_t rb3_sz:16; /* W3 */ 228 uint64_t rb2_sz:16; 229 uint64_t rb1_sz:16; 230 uint64_t rb0_sz:16; 231 232 uint64_t rb7_sz:16; /* W4 */ 233 uint64_t rb6_sz:16; 234 uint64_t rb5_sz:16; 235 uint64_t rb4_sz:16; 236 237 uint64_t rb11_sz:16; /* W5 */ 238 uint64_t rb10_sz:16; 239 uint64_t rb9_sz:16; 240 uint64_t rb8_sz:16; 241 #elif defined(__LITTLE_ENDIAN_BITFIELD) 242 uint64_t err_opcode:8; 243 uint64_t err_level:3; 244 uint64_t l2_present:1; 245 uint64_t l3_type:4; 246 uint64_t l4_type:4; 247 uint64_t vlan2_stripped:1; 248 uint64_t vlan2_found:1; 249 uint64_t vlan_stripped:1; 250 uint64_t vlan_found:1; 251 uint64_t rb_cnt:4; 252 uint64_t rsvd2:4; 253 uint64_t rss_alg:4; 254 uint64_t rsvd1:12; 255 uint64_t rq_idx:3; 256 uint64_t rq_qs:7; 257 uint64_t rsvd0:1; 258 uint64_t stdn_fault:1; 259 uint64_t cqe_type:4; /* W0 */ 260 uint64_t chan:12; 261 uint64_t rsvd3:1; 262 uint64_t align_pad:3; 263 uint64_t cq_pkt_len:8; 264 uint64_t l4_ptr:8; 265 uint64_t l3_ptr:8; 266 uint64_t l2_ptr:8; 267 uint64_t pkt_len:16; /* W1 */ 268 uint64_t vlan2_ptr:8; 269 uint64_t vlan_ptr:8; 270 uint64_t vlan_tci:16; 271 uint64_t rss_tag:32; /* W2 */ 272 uint64_t rb0_sz:16; 273 uint64_t rb1_sz:16; 274 uint64_t rb2_sz:16; 275 uint64_t rb3_sz:16; /* W3 */ 276 uint64_t rb4_sz:16; 277 uint64_t rb5_sz:16; 278 uint64_t rb6_sz:16; 279 uint64_t rb7_sz:16; /* W4 */ 280 uint64_t rb8_sz:16; 281 uint64_t rb9_sz:16; 282 uint64_t rb10_sz:16; 283 uint64_t rb11_sz:16; /* W5 */ 284 #endif 285 uint64_t rb0_ptr:64; 286 uint64_t rb1_ptr:64; 287 uint64_t rb2_ptr:64; 288 uint64_t rb3_ptr:64; 289 uint64_t rb4_ptr:64; 290 uint64_t rb5_ptr:64; 291 uint64_t rb6_ptr:64; 292 uint64_t rb7_ptr:64; 293 uint64_t rb8_ptr:64; 294 uint64_t rb9_ptr:64; 295 uint64_t rb10_ptr:64; 296 uint64_t rb11_ptr:64; 297 }; 298 299 struct cqe_rx_tcp_err_t { 300 #if defined(__BIG_ENDIAN_BITFIELD) 301 uint64_t cqe_type:4; /* W0 */ 302 uint64_t rsvd0:60; 303 304 uint64_t rsvd1:4; /* W1 */ 305 uint64_t partial_first:1; 306 uint64_t rsvd2:27; 307 uint64_t rbdr_bytes:8; 308 uint64_t rsvd3:24; 309 #elif defined(__LITTLE_ENDIAN_BITFIELD) 310 uint64_t rsvd0:60; 311 uint64_t cqe_type:4; 312 313 uint64_t rsvd3:24; 314 uint64_t rbdr_bytes:8; 315 uint64_t rsvd2:27; 316 uint64_t partial_first:1; 317 uint64_t rsvd1:4; 318 #endif 319 }; 320 321 struct cqe_rx_tcp_t { 322 #if defined(__BIG_ENDIAN_BITFIELD) 323 uint64_t cqe_type:4; /* W0 */ 324 uint64_t rsvd0:52; 325 uint64_t cq_tcp_status:8; 326 327 uint64_t rsvd1:32; /* W1 */ 328 uint64_t tcp_cntx_bytes:8; 329 uint64_t rsvd2:8; 330 uint64_t tcp_err_bytes:16; 331 #elif defined(__LITTLE_ENDIAN_BITFIELD) 332 uint64_t cq_tcp_status:8; 333 uint64_t rsvd0:52; 334 uint64_t cqe_type:4; /* W0 */ 335 336 uint64_t tcp_err_bytes:16; 337 uint64_t rsvd2:8; 338 uint64_t tcp_cntx_bytes:8; 339 uint64_t rsvd1:32; /* W1 */ 340 #endif 341 }; 342 343 struct cqe_send_t { 344 #if defined(__BIG_ENDIAN_BITFIELD) 345 uint64_t cqe_type:4; /* W0 */ 346 uint64_t rsvd0:4; 347 uint64_t sqe_ptr:16; 348 uint64_t rsvd1:4; 349 uint64_t rsvd2:10; 350 uint64_t sq_qs:7; 351 uint64_t sq_idx:3; 352 uint64_t rsvd3:8; 353 uint64_t send_status:8; 354 355 uint64_t ptp_timestamp:64; /* W1 */ 356 #elif defined(__LITTLE_ENDIAN_BITFIELD) 357 uint64_t send_status:8; 358 uint64_t rsvd3:8; 359 uint64_t sq_idx:3; 360 uint64_t sq_qs:7; 361 uint64_t rsvd2:10; 362 uint64_t rsvd1:4; 363 uint64_t sqe_ptr:16; 364 uint64_t rsvd0:4; 365 uint64_t cqe_type:4; /* W0 */ 366 367 uint64_t ptp_timestamp:64; /* W1 */ 368 #endif 369 }; 370 371 union cq_desc_t { 372 uint64_t u[64]; 373 struct cqe_send_t snd_hdr; 374 struct cqe_rx_t rx_hdr; 375 struct cqe_rx_tcp_t rx_tcp_hdr; 376 struct cqe_rx_tcp_err_t rx_tcp_err_hdr; 377 }; 378 379 struct rbdr_entry_t { 380 #if defined(__BIG_ENDIAN_BITFIELD) 381 uint64_t rsvd0:15; 382 uint64_t buf_addr:42; 383 uint64_t cache_align:7; 384 #elif defined(__LITTLE_ENDIAN_BITFIELD) 385 uint64_t cache_align:7; 386 uint64_t buf_addr:42; 387 uint64_t rsvd0:15; 388 #endif 389 }; 390 391 /* TCP reassembly context */ 392 struct rbe_tcp_cnxt_t { 393 #if defined(__BIG_ENDIAN_BITFIELD) 394 uint64_t tcp_pkt_cnt:12; 395 uint64_t rsvd1:4; 396 uint64_t align_hdr_bytes:4; 397 uint64_t align_ptr_bytes:4; 398 uint64_t ptr_bytes:16; 399 uint64_t rsvd2:24; 400 uint64_t cqe_type:4; 401 uint64_t rsvd0:54; 402 uint64_t tcp_end_reason:2; 403 uint64_t tcp_status:4; 404 #elif defined(__LITTLE_ENDIAN_BITFIELD) 405 uint64_t tcp_status:4; 406 uint64_t tcp_end_reason:2; 407 uint64_t rsvd0:54; 408 uint64_t cqe_type:4; 409 uint64_t rsvd2:24; 410 uint64_t ptr_bytes:16; 411 uint64_t align_ptr_bytes:4; 412 uint64_t align_hdr_bytes:4; 413 uint64_t rsvd1:4; 414 uint64_t tcp_pkt_cnt:12; 415 #endif 416 }; 417 418 /* Always Big endian */ 419 struct rx_hdr_t { 420 uint64_t opaque:32; 421 uint64_t rss_flow:8; 422 uint64_t skip_length:6; 423 uint64_t disable_rss:1; 424 uint64_t disable_tcp_reassembly:1; 425 uint64_t nodrop:1; 426 uint64_t dest_alg:2; 427 uint64_t rsvd0:2; 428 uint64_t dest_rq:11; 429 }; 430 431 enum send_l4_csum_type { 432 SEND_L4_CSUM_DISABLE = 0x00, 433 SEND_L4_CSUM_UDP = 0x01, 434 SEND_L4_CSUM_TCP = 0x02, 435 SEND_L4_CSUM_SCTP = 0x03, 436 }; 437 438 enum send_crc_alg { 439 SEND_CRCALG_CRC32 = 0x00, 440 SEND_CRCALG_CRC32C = 0x01, 441 SEND_CRCALG_ICRC = 0x02, 442 }; 443 444 enum send_load_type { 445 SEND_LD_TYPE_LDD = 0x00, 446 SEND_LD_TYPE_LDT = 0x01, 447 SEND_LD_TYPE_LDWB = 0x02, 448 }; 449 450 enum send_mem_alg_type { 451 SEND_MEMALG_SET = 0x00, 452 SEND_MEMALG_ADD = 0x08, 453 SEND_MEMALG_SUB = 0x09, 454 SEND_MEMALG_ADDLEN = 0x0A, 455 SEND_MEMALG_SUBLEN = 0x0B, 456 }; 457 458 enum send_mem_dsz_type { 459 SEND_MEMDSZ_B64 = 0x00, 460 SEND_MEMDSZ_B32 = 0x01, 461 SEND_MEMDSZ_B8 = 0x03, 462 }; 463 464 enum sq_subdesc_type { 465 SQ_DESC_TYPE_INVALID = 0x00, 466 SQ_DESC_TYPE_HEADER = 0x01, 467 SQ_DESC_TYPE_CRC = 0x02, 468 SQ_DESC_TYPE_IMMEDIATE = 0x03, 469 SQ_DESC_TYPE_GATHER = 0x04, 470 SQ_DESC_TYPE_MEMORY = 0x05, 471 }; 472 473 struct sq_crc_subdesc { 474 #if defined(__BIG_ENDIAN_BITFIELD) 475 uint64_t rsvd1:32; 476 uint64_t crc_ival:32; 477 uint64_t subdesc_type:4; 478 uint64_t crc_alg:2; 479 uint64_t rsvd0:10; 480 uint64_t crc_insert_pos:16; 481 uint64_t hdr_start:16; 482 uint64_t crc_len:16; 483 #elif defined(__LITTLE_ENDIAN_BITFIELD) 484 uint64_t crc_len:16; 485 uint64_t hdr_start:16; 486 uint64_t crc_insert_pos:16; 487 uint64_t rsvd0:10; 488 uint64_t crc_alg:2; 489 uint64_t subdesc_type:4; 490 uint64_t crc_ival:32; 491 uint64_t rsvd1:32; 492 #endif 493 }; 494 495 struct sq_gather_subdesc { 496 #if defined(__BIG_ENDIAN_BITFIELD) 497 uint64_t subdesc_type:4; /* W0 */ 498 uint64_t ld_type:2; 499 uint64_t rsvd0:42; 500 uint64_t size:16; 501 502 uint64_t rsvd1:15; /* W1 */ 503 uint64_t addr:49; 504 #elif defined(__LITTLE_ENDIAN_BITFIELD) 505 uint64_t size:16; 506 uint64_t rsvd0:42; 507 uint64_t ld_type:2; 508 uint64_t subdesc_type:4; /* W0 */ 509 510 uint64_t addr:49; 511 uint64_t rsvd1:15; /* W1 */ 512 #endif 513 }; 514 515 /* SQ immediate subdescriptor */ 516 struct sq_imm_subdesc { 517 #if defined(__BIG_ENDIAN_BITFIELD) 518 uint64_t subdesc_type:4; /* W0 */ 519 uint64_t rsvd0:46; 520 uint64_t len:14; 521 522 uint64_t data:64; /* W1 */ 523 #elif defined(__LITTLE_ENDIAN_BITFIELD) 524 uint64_t len:14; 525 uint64_t rsvd0:46; 526 uint64_t subdesc_type:4; /* W0 */ 527 528 uint64_t data:64; /* W1 */ 529 #endif 530 }; 531 532 struct sq_mem_subdesc { 533 #if defined(__BIG_ENDIAN_BITFIELD) 534 uint64_t subdesc_type:4; /* W0 */ 535 uint64_t mem_alg:4; 536 uint64_t mem_dsz:2; 537 uint64_t wmem:1; 538 uint64_t rsvd0:21; 539 uint64_t offset:32; 540 541 uint64_t rsvd1:15; /* W1 */ 542 uint64_t addr:49; 543 #elif defined(__LITTLE_ENDIAN_BITFIELD) 544 uint64_t offset:32; 545 uint64_t rsvd0:21; 546 uint64_t wmem:1; 547 uint64_t mem_dsz:2; 548 uint64_t mem_alg:4; 549 uint64_t subdesc_type:4; /* W0 */ 550 551 uint64_t addr:49; 552 uint64_t rsvd1:15; /* W1 */ 553 #endif 554 }; 555 556 struct sq_hdr_subdesc { 557 #if defined(__BIG_ENDIAN_BITFIELD) 558 uint64_t subdesc_type:4; 559 uint64_t tso:1; 560 uint64_t post_cqe:1; /* Post CQE on no error also */ 561 uint64_t dont_send:1; 562 uint64_t tstmp:1; 563 uint64_t subdesc_cnt:8; 564 uint64_t csum_l4:2; 565 uint64_t csum_l3:1; 566 uint64_t csum_inner_l4:2; 567 uint64_t csum_inner_l3:1; 568 uint64_t rsvd0:2; 569 uint64_t l4_offset:8; 570 uint64_t l3_offset:8; 571 uint64_t rsvd1:4; 572 uint64_t tot_len:20; /* W0 */ 573 574 uint64_t rsvd2:24; 575 uint64_t inner_l4_offset:8; 576 uint64_t inner_l3_offset:8; 577 uint64_t tso_start:8; 578 uint64_t rsvd3:2; 579 uint64_t tso_max_paysize:14; /* W1 */ 580 #elif defined(__LITTLE_ENDIAN_BITFIELD) 581 uint64_t tot_len:20; 582 uint64_t rsvd1:4; 583 uint64_t l3_offset:8; 584 uint64_t l4_offset:8; 585 uint64_t rsvd0:2; 586 uint64_t csum_inner_l3:1; 587 uint64_t csum_inner_l4:2; 588 uint64_t csum_l3:1; 589 uint64_t csum_l4:2; 590 uint64_t subdesc_cnt:8; 591 uint64_t tstmp:1; 592 uint64_t dont_send:1; 593 uint64_t post_cqe:1; /* Post CQE on no error also */ 594 uint64_t tso:1; 595 uint64_t subdesc_type:4; /* W0 */ 596 597 uint64_t tso_max_paysize:14; 598 uint64_t rsvd3:2; 599 uint64_t tso_start:8; 600 uint64_t inner_l3_offset:8; 601 uint64_t inner_l4_offset:8; 602 uint64_t rsvd2:24; 603 #endif 604 }; 605 606 /* Queue config register formats */ 607 struct rq_cfg { 608 #if defined(__BIG_ENDIAN_BITFIELD) 609 uint64_t reserved_2_63:62; 610 uint64_t ena:1; 611 uint64_t tcp_ena:1; 612 #elif defined(__LITTLE_ENDIAN_BITFIELD) 613 uint64_t tcp_ena:1; 614 uint64_t ena:1; 615 uint64_t reserved_2_63:62; 616 #endif 617 }; 618 619 struct cq_cfg { 620 #if defined(__BIG_ENDIAN_BITFIELD) 621 uint64_t reserved_43_63:21; 622 uint64_t ena:1; 623 uint64_t reset:1; 624 uint64_t caching:1; 625 uint64_t reserved_35_39:5; 626 uint64_t qsize:3; 627 uint64_t reserved_25_31:7; 628 uint64_t avg_con:9; 629 uint64_t reserved_0_15:16; 630 #elif defined(__LITTLE_ENDIAN_BITFIELD) 631 uint64_t reserved_0_15:16; 632 uint64_t avg_con:9; 633 uint64_t reserved_25_31:7; 634 uint64_t qsize:3; 635 uint64_t reserved_35_39:5; 636 uint64_t caching:1; 637 uint64_t reset:1; 638 uint64_t ena:1; 639 uint64_t reserved_43_63:21; 640 #endif 641 }; 642 643 struct sq_cfg { 644 #if defined(__BIG_ENDIAN_BITFIELD) 645 uint64_t reserved_20_63:44; 646 uint64_t ena:1; 647 uint64_t reserved_18_18:1; 648 uint64_t reset:1; 649 uint64_t ldwb:1; 650 uint64_t reserved_11_15:5; 651 uint64_t qsize:3; 652 uint64_t reserved_3_7:5; 653 uint64_t tstmp_bgx_intf:3; 654 #elif defined(__LITTLE_ENDIAN_BITFIELD) 655 uint64_t tstmp_bgx_intf:3; 656 uint64_t reserved_3_7:5; 657 uint64_t qsize:3; 658 uint64_t reserved_11_15:5; 659 uint64_t ldwb:1; 660 uint64_t reset:1; 661 uint64_t reserved_18_18:1; 662 uint64_t ena:1; 663 uint64_t reserved_20_63:44; 664 #endif 665 }; 666 667 struct rbdr_cfg { 668 #if defined(__BIG_ENDIAN_BITFIELD) 669 uint64_t reserved_45_63:19; 670 uint64_t ena:1; 671 uint64_t reset:1; 672 uint64_t ldwb:1; 673 uint64_t reserved_36_41:6; 674 uint64_t qsize:4; 675 uint64_t reserved_25_31:7; 676 uint64_t avg_con:9; 677 uint64_t reserved_12_15:4; 678 uint64_t lines:12; 679 #elif defined(__LITTLE_ENDIAN_BITFIELD) 680 uint64_t lines:12; 681 uint64_t reserved_12_15:4; 682 uint64_t avg_con:9; 683 uint64_t reserved_25_31:7; 684 uint64_t qsize:4; 685 uint64_t reserved_36_41:6; 686 uint64_t ldwb:1; 687 uint64_t reset:1; 688 uint64_t ena: 1; 689 uint64_t reserved_45_63:19; 690 #endif 691 }; 692 693 struct qs_cfg { 694 #if defined(__BIG_ENDIAN_BITFIELD) 695 uint64_t reserved_32_63:32; 696 uint64_t ena:1; 697 uint64_t reserved_27_30:4; 698 uint64_t sq_ins_ena:1; 699 uint64_t sq_ins_pos:6; 700 uint64_t lock_ena:1; 701 uint64_t lock_viol_cqe_ena:1; 702 uint64_t send_tstmp_ena:1; 703 uint64_t be:1; 704 uint64_t reserved_7_15:9; 705 uint64_t vnic:7; 706 #elif defined(__LITTLE_ENDIAN_BITFIELD) 707 uint64_t vnic:7; 708 uint64_t reserved_7_15:9; 709 uint64_t be:1; 710 uint64_t send_tstmp_ena:1; 711 uint64_t lock_viol_cqe_ena:1; 712 uint64_t lock_ena:1; 713 uint64_t sq_ins_pos:6; 714 uint64_t sq_ins_ena:1; 715 uint64_t reserved_27_30:4; 716 uint64_t ena:1; 717 uint64_t reserved_32_63:32; 718 #endif 719 }; 720 721 #endif /* Q_STRUCT_H */ 722