Searched refs:n_width (Results 1 – 2 of 2) sorted by relevance
| /freebsd/sys/arm/nvidia/tegra124/ |
| H A D | tegra124_clk_pll.c | 97 uint32_t n_width; member
497 *n = get_masked(val, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in get_divisors()
509 val = set_masked(val, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in set_divisors()
711 if (n >= (1 << mnp_bits->n_width)) in pll_set_std()
734 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pll_set_std()
833 if (n >= (1 << mnp_bits->n_width)) in plld2_set_freq()
900 if (n >= (1 << mnp_bits->n_width)) in pllx_set_freq()
921 reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width); in pllx_set_freq()
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| /freebsd/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_clk_pll.c | 122 uint32_t n_width; member
690 *n = get_masked(val, mnp_bits->n_shift, mnp_bits->n_width); in get_divisors()
702 val = set_masked(val, n, mnp_bits->n_shift, mnp_bits->n_width); in set_divisors()
909 if (n >= (1 << mnp_bits->n_width)) in pll_set_std()
932 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); in pll_set_std()
1056 if (n >= (1 << mnp_bits->n_width)) in plld2_set_freq()
1138 if (n >= (1 << mnp_bits->n_width)) in pllx_set_freq()
1192 mnp_bits->n_width); in pllx_set_freq()
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