Home
last modified time | relevance | path

Searched refs:msr (Results 1 – 25 of 111) sorted by relevance

12345

/freebsd/sys/x86/cpufreq/
H A Dhwpstate_amd.c80 #define AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) (((msr) >> 4) & 0x7)
81 #define AMD_10H_11H_GET_PSTATE_LIMIT(msr) (((msr)) & 0x7) argument
83 #define AMD_10H_11H_CUR_VID(msr) (((msr) >> 9) & 0x7F) argument
84 #define AMD_10H_11H_CUR_DID(msr) (((msr) >> 6) & 0x07)
85 #define AMD_10H_11H_CUR_FID(msr) ((msr) argument
78 AMD_10H_11H_GET_PSTATE_MAX_VAL(msr) global() argument
79 AMD_10H_11H_GET_PSTATE_LIMIT(msr) global() argument
82 AMD_10H_11H_CUR_DID(msr) global() argument
86 AMD_17H_CUR_IDD(msr) global() argument
87 AMD_17H_CUR_VID(msr) global() argument
88 AMD_17H_CUR_DID(msr) global() argument
89 AMD_17H_CUR_FID(msr) global() argument
174 uint64_t msr; hwpstate_goto_pstate() local
266 uint64_t msr; hwpstate_get() local
352 uint64_t msr; hwpstate_probe() local
430 uint64_t msr; hwpstate_get_info_from_msr() local
[all...]
H A Dp4tcc.c261 uint64_t mask, msr; in p4tcc_set() local
282 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_set()
284 msr &= ~(mask | TCC_ENABLE_ONDEMAND); in p4tcc_set()
286 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; in p4tcc_set()
287 wrmsr(MSR_THERM_CONTROL, msr); in p4tcc_set()
296 if (msr & TCC_ENABLE_ONDEMAND) in p4tcc_set()
308 uint64_t msr; in p4tcc_get() local
324 msr = rdmsr(MSR_THERM_CONTROL); in p4tcc_get()
325 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); in p4tcc_get()
H A Dest.c861 static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs,
863 static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs,
954 uint64_t msr; in est_probe() local
972 msr = rdmsr(MSR_MISC_ENABLE); in est_probe()
973 if ((msr & MSR_SS_ENABLE) == 0) { in est_probe()
974 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); in est_probe()
979 msr = rdmsr(MSR_MISC_ENABLE); in est_probe()
980 if ((msr & MSR_SS_ENABLE) == 0) { in est_probe()
1036 uint64_t msr; in est_get_info() local
1040 msr = rdmsr(MSR_PERF_STATUS); in est_get_info()
[all …]
/freebsd/sys/amd64/amd64/
H A Dinitcpu.c67 uint64_t msr; in init_amd() local
116 msr = rdmsr(MSR_NB_CFG1); in init_amd()
117 msr |= (uint64_t)1 << 54; in init_amd()
118 wrmsr(MSR_NB_CFG1, msr); in init_amd()
130 msr = rdmsr(0xc001102a); in init_amd()
131 msr &= ~((uint64_t)1 << 24); in init_amd()
132 wrmsr(0xc001102a, msr); in init_amd()
144 msr = rdmsr(MSR_LS_CFG); in init_amd()
145 msr |= (uint64_t)1 << 15; in init_amd()
146 wrmsr(MSR_LS_CFG, msr); in init_amd()
[all …]
/freebsd/usr.sbin/bhyve/
H A Duart_emul.c91 uint8_t msr; /* Modem status register (R/W) */
108 uint8_t msr; in modem_status()
115 msr = 0; in modem_status()
117 msr |= MSR_CTS; in modem_status()
119 msr |= MSR_DSR; in modem_status()
121 msr |= MSR_RI; in modem_status()
123 msr |= MSR_DCD; in modem_status()
129 msr = MSR_DCD | MSR_DSR; in modem_status()
131 assert((msr & MSR_DELTA_MASK) == 0); in modem_status()
133 return (msr); in modem_status()
92 uint8_t msr; /* Modem status register (R/W) */ global() member
109 uint8_t msr; modem_status() local
221 uint8_t msr; uart_ns16550_write() local
[all...]
/freebsd/sys/powerpc/powerpc/
H A Dfpu.c49 register_t msr; in save_fpu_int() local
57 msr = mfmsr(); in save_fpu_int()
59 mtmsr(msr | PSL_FP | PSL_VSX); in save_fpu_int()
61 mtmsr(msr | PSL_FP); in save_fpu_int()
97 mtmsr(msr); in save_fpu_int()
103 register_t msr; in enable_fpu() local
137 msr = mfmsr(); in enable_fpu()
139 mtmsr(msr | PSL_FP | PSL_VSX); in enable_fpu()
141 mtmsr(msr | PSL_FP); in enable_fpu()
178 mtmsr(msr); in enable_fpu()
[all …]
H A Daltivec.c48 int msr; in save_vec_int() local
56 msr = mfmsr(); in save_vec_int()
57 mtmsr(msr | PSL_VEC); in save_vec_int()
80 mtmsr(msr); in save_vec_int()
87 int msr; in enable_vec() local
118 msr = mfmsr(); in enable_vec()
119 mtmsr(msr | PSL_VEC); in enable_vec()
142 mtmsr(msr); in enable_vec()
183 register_t msr; in disable_vec() local
191 msr = mfmsr() & ~PSL_VEC; in disable_vec()
[all …]
/freebsd/sys/dev/coretemp/
H A Dcoretemp.c157 uint64_t msr; in coretemp_attach() local
190 msr = rdmsr(MSR_BIOS_SIGN); in coretemp_attach()
191 msr = msr >> 32; in coretemp_attach()
192 if (msr < 0x39) { in coretemp_attach()
213 msr = rdmsr(MSR_IA32_EXT_CONFIG); in coretemp_attach()
214 if (msr & (1 << 30)) in coretemp_attach()
240 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); in coretemp_attach()
242 tjtarget = (msr >> 16) & 0xff; in coretemp_attach()
311 u_int msr; member
346 uint64_t msr; in coretemp_get_val_sysctl() local
[all …]
/freebsd/sys/amd64/vmm/
H A Dvmm_lapic.c131 x2apic_msr(u_int msr) in x2apic_msr() argument
133 return (msr >= 0x800 && msr <= 0xBFF); in x2apic_msr()
137 x2apic_msr_to_regoff(u_int msr) in x2apic_msr_to_regoff() argument
140 return ((msr - 0x800) << 4); in x2apic_msr_to_regoff()
144 lapic_msr(u_int msr) in lapic_msr() argument
147 return (x2apic_msr(msr) || msr == MSR_APICBASE); in lapic_msr()
151 lapic_rdmsr(struct vcpu *vcpu, u_int msr, uint64_t *rval, bool *retu) in lapic_rdmsr() argument
159 if (msr == MSR_APICBASE) { in lapic_rdmsr()
163 offset = x2apic_msr_to_regoff(msr); in lapic_rdmsr()
171 lapic_wrmsr(struct vcpu *vcpu, u_int msr, uint64_t val, bool *retu) in lapic_wrmsr() argument
[all …]
/freebsd/sys/x86/x86/
H A Dx86_mem.c202 int i, j, msr; in x86_mrfetch() local
208 msr = MSR_MTRR64kBase; in x86_mrfetch()
209 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) { in x86_mrfetch()
210 msrv = rdmsr(msr); in x86_mrfetch()
220 msr = MSR_MTRR16kBase; in x86_mrfetch()
221 for (i = 0; i < MTRR_N16K / 8; i++, msr++) { in x86_mrfetch()
222 msrv = rdmsr(msr); in x86_mrfetch()
232 msr = MSR_MTRR4kBase; in x86_mrfetch()
233 for (i = 0; i < MTRR_N4K / 8; i++, msr++) { in x86_mrfetch()
234 msrv = rdmsr(msr); in x86_mrfetch()
[all …]
/freebsd/sys/arm64/vmm/
H A Dvmm_nvhe_exception.S72 msr vbar_el2, x6
77 msr vttbr_el2, x9
79 msr ttbr0_el2, x0
87 msr mair_el2, x9
89 msr tcr_el2, x2
92 msr sctlr_el2, x3
94 msr vtcr_el2, x4
110 msr vbar_el2, x1
116 msr sctlr_el2, x2
/freebsd/sys/arm64/arm64/
H A Dlocore.S71 msr contextidr_el1, xzr
123 msr sp_el0, x15
233 msr daifset, #DAIF_INTR
239 msr contextidr_el1, xzr
279 msr sp_el0, x15
283 msr ttbr0_el1, x27
297 msr tpidr_el1, x18
320 msr sctlr_el1, x2
331 msr spsr_el1, x2
332 msr elr_el1, lr
[all …]
H A Dswtch.S44 msr mdscr_el1, \tmp
53 msr mdscr_el1, \tmp
69 msr contextidr_el1, x10
109 msr sp_el0, x19
119 msr tpidr_el0, x6
121 msr tpidrro_el0, x6
191 msr sp_el0, x20
214 msr tpidr_el0, x6
216 msr tpidrro_el0, x6
239 msr daifset, #(DAIF_D | DAIF_INTR)
[all …]
/freebsd/sys/dev/hyperv/vmbus/aarch64/
H A Dhyperv_machdep.h52 void arm_hv_set_vreg(u32 msr, u64 val);
53 #define WRMSR(msr, val) arm_hv_set_vreg(msr, val) argument
54 u64 arm_hv_get_vreg(u32 msr);
55 #define RDMSR(msr) arm_hv_get_vreg(msr) argument
H A Dhyperv_machdep.c51 arm_hv_set_vreg(u32 msr, u64 value) in arm_hv_set_vreg() argument
56 HV_PARTITION_ID_SELF, HV_VP_INDEX_SELF, msr, 0, value, NULL); in arm_hv_set_vreg()
60 hv_get_vpreg_128(u32 msr, struct hv_get_vp_registers_output *result) in hv_get_vpreg_128() argument
70 args.a4 = msr; in hv_get_vpreg_128()
83 arm_hv_get_vreg(u32 msr) in arm_hv_get_vreg() argument
87 hv_get_vpreg_128(msr, &output); in arm_hv_get_vreg()
/freebsd/sys/powerpc/cpufreq/
H A Dpcr.c107 register_t msr; in write_scom() local
112 msr = mfmsr(); in write_scom()
113 mtmsr(msr & ~PSL_EE); isync(); in write_scom()
126 mtmsr(msr); isync(); in write_scom()
132 register_t msr; in read_scom() local
135 msr = mfmsr(); in read_scom()
136 mtmsr(msr & ~PSL_EE); isync(); in read_scom()
146 mtmsr(msr); isync(); in read_scom()
262 register_t pcr, msr; in pcr_set() local
280 msr = mfmsr(); in pcr_set()
[all …]
/freebsd/sys/amd64/vmm/intel/
H A Dvmx_msr.h64 int msr_bitmap_change_access(char *bitmap, u_int msr, int access);
66 #define guest_msr_rw(vmx, msr) \ argument
67 msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_RW)
69 #define guest_msr_ro(vmx, msr) \ argument
70 msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_READ)
/freebsd/sys/compat/linuxkpi/common/include/asm/
H A Dmsr.h32 #define rdmsrl(msr, val) ((val) = rdmsr(msr)) argument
33 #define rdmsrl_safe(msr, val) rdmsr_safe(msr, val) argument
/freebsd/sys/dev/hyperv/vmbus/x86/
H A Dhyperv_machdep.h35 #define WRMSR(msr, val) wrmsr(msr, val) argument
36 #define RDMSR(msr) rdmsr(msr) argument
/freebsd/sys/arm/arm/
H A Dsetstack.S66 msr cpsr_fsxc, r2
70 msr cpsr_fsxc, r3 /* Restore the old mode */
85 msr cpsr_fsxc, r2
89 msr cpsr_fsxc, r3 /* Restore the old mode */
/freebsd/sys/powerpc/booke/
H A Dmp_cpudep.c53 uint32_t msr, csr; in cpudep_ap_bootstrap() local
71 msr = PSL_CM | PSL_ME; in cpudep_ap_bootstrap()
73 msr = PSL_ME; in cpudep_ap_bootstrap()
75 mtmsr(msr); in cpudep_ap_bootstrap()
H A Dspe.c56 int msr; in save_vec_int() local
64 msr = mfmsr(); in save_vec_int()
65 mtmsr(msr | PSL_VEC); in save_vec_int()
91 mtmsr(msr); in save_vec_int()
98 int msr; in enable_vec() local
129 msr = mfmsr(); in enable_vec()
130 mtmsr(msr | PSL_VEC); in enable_vec()
154 mtmsr(msr); in enable_vec()
481 uint32_t msr; in spe_handle_fpdata() local
492 msr = mfmsr(); in spe_handle_fpdata()
[all …]
/freebsd/sys/powerpc/aim/
H A Daim_machdep.c163 extern void __restartkernel(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr);
164 extern void __restartkernel_virtual(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr);
240 register_t msr; in aim_cpu_init() local
305 msr = mfmsr(); in aim_cpu_init()
306 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); in aim_cpu_init()
466 mtmsr(msr); in aim_cpu_init()
647 register_t msr; in flush_disable_caches()
654 msr = mfmsr(); in flush_disable_caches()
656 mtmsr(msr & ~(PSL_EE | PSL_DR)); in flush_disable_caches()
744 mtmsr(msr); in flush_disable_caches()
646 register_t msr; flush_disable_caches() local
758 register_t msr; mpc745x_sleep() local
[all...]
/freebsd/sys/powerpc/include/
H A Dcpufunc.h235 register_t msr; in intr_disable() local
237 msr = mfmsr(); in intr_disable()
238 mtmsr(msr & ~PSL_EE); in intr_disable()
239 return (msr); in intr_disable()
243 intr_restore(register_t msr) in intr_restore() argument
246 mtmsr(msr); in intr_restore()
/freebsd/sys/i386/i386/
H A Dinitcpu.c644 uint64_t msr; in initializecpu() local
766 msr = rdmsr(MSR_EFER) | EFER_NXE; in initializecpu()
767 wrmsr(MSR_EFER, msr); in initializecpu()
814 u_int64_t msr; in enable_K5_wt_alloc() local
823 msr = rdmsr(0x83); /* HWCR */ in enable_K5_wt_alloc()
824 wrmsr(0x83, msr & !(0x10)); in enable_K5_wt_alloc()
832 msr = Maxmem / 16; in enable_K5_wt_alloc()
834 msr = 0; in enable_K5_wt_alloc()
835 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; in enable_K5_wt_alloc()
842 msr |= AMD_WT_ALLOC_PRE; in enable_K5_wt_alloc()
[all …]

12345