1 /*-
2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2022 NVIDIA corporation & affiliates.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include "opt_ipsec.h"
28 #include "opt_kern_tls.h"
29 #include "opt_rss.h"
30 #include "opt_ratelimit.h"
31
32 #include <dev/mlx5/mlx5_en/en.h>
33 #include <dev/mlx5/mlx5_accel/ipsec.h>
34
35 #include <sys/eventhandler.h>
36 #include <sys/sockio.h>
37 #include <machine/atomic.h>
38
39 #include <net/debugnet.h>
40 #include <netinet/tcp_ratelimit.h>
41 #include <netipsec/keydb.h>
42 #include <netipsec/ipsec_offload.h>
43
44 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
45 static if_snd_tag_query_t mlx5e_ul_snd_tag_query;
46 static if_snd_tag_free_t mlx5e_ul_snd_tag_free;
47
48 struct mlx5e_channel_param {
49 struct mlx5e_rq_param rq;
50 struct mlx5e_sq_param sq;
51 struct mlx5e_cq_param rx_cq;
52 struct mlx5e_cq_param tx_cq;
53 };
54
55 struct media {
56 u32 subtype;
57 u64 baudrate;
58 };
59
60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER] =
61 {
62 [MLX5E_1000BASE_CX_SGMII] = {
63 .subtype = IFM_1000_CX_SGMII,
64 .baudrate = IF_Mbps(1000ULL),
65 },
66 [MLX5E_1000BASE_KX] = {
67 .subtype = IFM_1000_KX,
68 .baudrate = IF_Mbps(1000ULL),
69 },
70 [MLX5E_10GBASE_CX4] = {
71 .subtype = IFM_10G_CX4,
72 .baudrate = IF_Gbps(10ULL),
73 },
74 [MLX5E_10GBASE_KX4] = {
75 .subtype = IFM_10G_KX4,
76 .baudrate = IF_Gbps(10ULL),
77 },
78 [MLX5E_10GBASE_KR] = {
79 .subtype = IFM_10G_KR,
80 .baudrate = IF_Gbps(10ULL),
81 },
82 [MLX5E_20GBASE_KR2] = {
83 .subtype = IFM_20G_KR2,
84 .baudrate = IF_Gbps(20ULL),
85 },
86 [MLX5E_40GBASE_CR4] = {
87 .subtype = IFM_40G_CR4,
88 .baudrate = IF_Gbps(40ULL),
89 },
90 [MLX5E_40GBASE_KR4] = {
91 .subtype = IFM_40G_KR4,
92 .baudrate = IF_Gbps(40ULL),
93 },
94 [MLX5E_56GBASE_R4] = {
95 .subtype = IFM_56G_R4,
96 .baudrate = IF_Gbps(56ULL),
97 },
98 [MLX5E_10GBASE_CR] = {
99 .subtype = IFM_10G_CR1,
100 .baudrate = IF_Gbps(10ULL),
101 },
102 [MLX5E_10GBASE_SR] = {
103 .subtype = IFM_10G_SR,
104 .baudrate = IF_Gbps(10ULL),
105 },
106 [MLX5E_10GBASE_ER_LR] = {
107 .subtype = IFM_10G_ER,
108 .baudrate = IF_Gbps(10ULL),
109 },
110 [MLX5E_40GBASE_SR4] = {
111 .subtype = IFM_40G_SR4,
112 .baudrate = IF_Gbps(40ULL),
113 },
114 [MLX5E_40GBASE_LR4_ER4] = {
115 .subtype = IFM_40G_LR4,
116 .baudrate = IF_Gbps(40ULL),
117 },
118 [MLX5E_100GBASE_CR4] = {
119 .subtype = IFM_100G_CR4,
120 .baudrate = IF_Gbps(100ULL),
121 },
122 [MLX5E_100GBASE_SR4] = {
123 .subtype = IFM_100G_SR4,
124 .baudrate = IF_Gbps(100ULL),
125 },
126 [MLX5E_100GBASE_KR4] = {
127 .subtype = IFM_100G_KR4,
128 .baudrate = IF_Gbps(100ULL),
129 },
130 [MLX5E_100GBASE_LR4] = {
131 .subtype = IFM_100G_LR4,
132 .baudrate = IF_Gbps(100ULL),
133 },
134 [MLX5E_100BASE_TX] = {
135 .subtype = IFM_100_TX,
136 .baudrate = IF_Mbps(100ULL),
137 },
138 [MLX5E_1000BASE_T] = {
139 .subtype = IFM_1000_T,
140 .baudrate = IF_Mbps(1000ULL),
141 },
142 [MLX5E_10GBASE_T] = {
143 .subtype = IFM_10G_T,
144 .baudrate = IF_Gbps(10ULL),
145 },
146 [MLX5E_25GBASE_CR] = {
147 .subtype = IFM_25G_CR,
148 .baudrate = IF_Gbps(25ULL),
149 },
150 [MLX5E_25GBASE_KR] = {
151 .subtype = IFM_25G_KR,
152 .baudrate = IF_Gbps(25ULL),
153 },
154 [MLX5E_25GBASE_SR] = {
155 .subtype = IFM_25G_SR,
156 .baudrate = IF_Gbps(25ULL),
157 },
158 [MLX5E_50GBASE_CR2] = {
159 .subtype = IFM_50G_CR2,
160 .baudrate = IF_Gbps(50ULL),
161 },
162 [MLX5E_50GBASE_KR2] = {
163 .subtype = IFM_50G_KR2,
164 .baudrate = IF_Gbps(50ULL),
165 },
166 [MLX5E_50GBASE_KR4] = {
167 .subtype = IFM_50G_KR4,
168 .baudrate = IF_Gbps(50ULL),
169 },
170 };
171
172 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_CABLE_TYPE_NUMBER] =
173 {
174 /**/
175 [MLX5E_SGMII_100M][MLX5E_CABLE_TYPE_UNKNOWN] = {
176 .subtype = IFM_100_SGMII,
177 .baudrate = IF_Mbps(100),
178 },
179
180 /**/
181 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_UNKNOWN] = {
182 .subtype = IFM_1000_CX,
183 .baudrate = IF_Mbps(1000),
184 },
185 [MLX5E_1000BASE_X_SGMII][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
186 .subtype = IFM_1000_SX,
187 .baudrate = IF_Mbps(1000),
188 },
189
190 /**/
191 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_UNKNOWN] = {
192 .subtype = IFM_5000_KR,
193 .baudrate = IF_Mbps(5000),
194 },
195 [MLX5E_5GBASE_R][MLX5E_CABLE_TYPE_TWISTED_PAIR] = {
196 .subtype = IFM_5000_T,
197 .baudrate = IF_Mbps(5000),
198 },
199
200 /**/
201 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_UNKNOWN] = {
202 .subtype = IFM_10G_KR,
203 .baudrate = IF_Gbps(10ULL),
204 },
205 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
206 .subtype = IFM_10G_CR1,
207 .baudrate = IF_Gbps(10ULL),
208 },
209 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
210 .subtype = IFM_10G_SR,
211 .baudrate = IF_Gbps(10ULL),
212 },
213
214 /**/
215 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_UNKNOWN] = {
216 .subtype = IFM_40G_KR4,
217 .baudrate = IF_Gbps(40ULL),
218 },
219 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
220 .subtype = IFM_40G_CR4,
221 .baudrate = IF_Gbps(40ULL),
222 },
223 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
224 .subtype = IFM_40G_SR4,
225 .baudrate = IF_Gbps(40ULL),
226 },
227
228 /**/
229 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = {
230 .subtype = IFM_25G_KR,
231 .baudrate = IF_Gbps(25ULL),
232 },
233 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
234 .subtype = IFM_25G_CR,
235 .baudrate = IF_Gbps(25ULL),
236 },
237 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
238 .subtype = IFM_25G_SR,
239 .baudrate = IF_Gbps(25ULL),
240 },
241 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CABLE_TYPE_TWISTED_PAIR] = {
242 .subtype = IFM_25G_T,
243 .baudrate = IF_Gbps(25ULL),
244 },
245
246 /**/
247 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = {
248 .subtype = IFM_50G_KR2,
249 .baudrate = IF_Gbps(50ULL),
250 },
251 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
252 .subtype = IFM_50G_CR2,
253 .baudrate = IF_Gbps(50ULL),
254 },
255 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
256 .subtype = IFM_50G_SR2,
257 .baudrate = IF_Gbps(50ULL),
258 },
259
260 /**/
261 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = {
262 .subtype = IFM_50G_KR_PAM4,
263 .baudrate = IF_Gbps(50ULL),
264 },
265 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
266 .subtype = IFM_50G_CP,
267 .baudrate = IF_Gbps(50ULL),
268 },
269 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
270 .subtype = IFM_50G_SR,
271 .baudrate = IF_Gbps(50ULL),
272 },
273
274 /**/
275 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = {
276 .subtype = IFM_100G_KR4,
277 .baudrate = IF_Gbps(100ULL),
278 },
279 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
280 .subtype = IFM_100G_CR4,
281 .baudrate = IF_Gbps(100ULL),
282 },
283 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
284 .subtype = IFM_100G_SR4,
285 .baudrate = IF_Gbps(100ULL),
286 },
287
288 /**/
289 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_UNKNOWN] = {
290 .subtype = IFM_100G_KR_PAM4,
291 .baudrate = IF_Gbps(100ULL),
292 },
293 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
294 .subtype = IFM_100G_CR_PAM4,
295 .baudrate = IF_Gbps(100ULL),
296 },
297 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
298 .subtype = IFM_100G_SR2, /* XXX */
299 .baudrate = IF_Gbps(100ULL),
300 },
301
302 /**/
303 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = {
304 .subtype = IFM_100G_KR4,
305 .baudrate = IF_Gbps(100ULL),
306 },
307 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
308 .subtype = IFM_100G_CP2,
309 .baudrate = IF_Gbps(100ULL),
310 },
311 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
312 .subtype = IFM_100G_SR2,
313 .baudrate = IF_Gbps(100ULL),
314 },
315
316 /**/
317 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_UNKNOWN] = {
318 .subtype = IFM_200G_KR4_PAM4, /* XXX */
319 .baudrate = IF_Gbps(200ULL),
320 },
321 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
322 .subtype = IFM_200G_CR4_PAM4, /* XXX */
323 .baudrate = IF_Gbps(200ULL),
324 },
325 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
326 .subtype = IFM_200G_SR4, /* XXX */
327 .baudrate = IF_Gbps(200ULL),
328 },
329
330 /**/
331 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = {
332 .subtype = IFM_200G_KR4_PAM4,
333 .baudrate = IF_Gbps(200ULL),
334 },
335 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_PASSIVE_COPPER] = {
336 .subtype = IFM_200G_CR4_PAM4,
337 .baudrate = IF_Gbps(200ULL),
338 },
339 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CABLE_TYPE_OPTICAL_MODULE] = {
340 .subtype = IFM_200G_SR4,
341 .baudrate = IF_Gbps(200ULL),
342 },
343
344 /**/
345 [MLX5E_400GAUI_8][MLX5E_CABLE_TYPE_UNKNOWN] = {
346 .subtype = IFM_400G_LR8, /* XXX */
347 .baudrate = IF_Gbps(400ULL),
348 },
349
350 /**/
351 [MLX5E_400GAUI_4_400GBASE_CR4_KR4][MLX5E_CABLE_TYPE_UNKNOWN] = {
352 .subtype = IFM_400G_LR8, /* XXX */
353 .baudrate = IF_Gbps(400ULL),
354 },
355 };
356
357 static const struct if_snd_tag_sw mlx5e_ul_snd_tag_sw = {
358 .snd_tag_query = mlx5e_ul_snd_tag_query,
359 .snd_tag_free = mlx5e_ul_snd_tag_free,
360 .type = IF_SND_TAG_TYPE_UNLIMITED
361 };
362
363 DEBUGNET_DEFINE(mlx5_en);
364
365 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
366
367 static void
mlx5e_update_carrier(struct mlx5e_priv * priv)368 mlx5e_update_carrier(struct mlx5e_priv *priv)
369 {
370 struct mlx5_core_dev *mdev = priv->mdev;
371 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
372 u32 eth_proto_oper;
373 int error;
374 u8 i;
375 u8 cable_type;
376 u8 port_state;
377 u8 is_er_type;
378 bool ext;
379 struct media media_entry = {};
380
381 port_state = mlx5_query_vport_state(mdev,
382 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
383
384 if (port_state == VPORT_STATE_UP) {
385 priv->media_status_last |= IFM_ACTIVE;
386 } else {
387 priv->media_status_last &= ~IFM_ACTIVE;
388 priv->media_active_last = IFM_ETHER;
389 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
390 return;
391 }
392
393 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
394 MLX5_PTYS_EN, 1);
395 if (error) {
396 priv->media_active_last = IFM_ETHER;
397 if_setbaudrate(priv->ifp, 1);
398 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
399 error);
400 return;
401 }
402
403 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
404 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
405 eth_proto_oper);
406
407 i = ilog2(eth_proto_oper);
408
409 if (ext) {
410 error = mlx5_query_pddr_cable_type(mdev, 1, &cable_type);
411 if (error != 0) {
412 /* use fallback entry */
413 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN];
414
415 mlx5_en_err(priv->ifp,
416 "query port pddr failed: %d\n", error);
417 } else {
418 media_entry = mlx5e_ext_mode_table[i][cable_type];
419
420 /* check if we should use fallback entry */
421 if (media_entry.subtype == 0)
422 media_entry = mlx5e_ext_mode_table[i][MLX5E_CABLE_TYPE_UNKNOWN];
423 }
424 } else {
425 media_entry = mlx5e_mode_table[i];
426 }
427
428 if (media_entry.subtype == 0) {
429 mlx5_en_err(priv->ifp,
430 "Could not find operational media subtype\n");
431 return;
432 }
433
434 switch (media_entry.subtype) {
435 case IFM_10G_ER:
436 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
437 if (error != 0) {
438 mlx5_en_err(priv->ifp,
439 "query port pddr failed: %d\n", error);
440 }
441 if (error != 0 || is_er_type == 0)
442 media_entry.subtype = IFM_10G_LR;
443 break;
444 case IFM_40G_LR4:
445 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
446 if (error != 0) {
447 mlx5_en_err(priv->ifp,
448 "query port pddr failed: %d\n", error);
449 }
450 if (error == 0 && is_er_type != 0)
451 media_entry.subtype = IFM_40G_ER4;
452 break;
453 }
454 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
455 if_setbaudrate(priv->ifp, media_entry.baudrate);
456
457 if_link_state_change(priv->ifp, LINK_STATE_UP);
458 }
459
460 static void
mlx5e_media_status(if_t dev,struct ifmediareq * ifmr)461 mlx5e_media_status(if_t dev, struct ifmediareq *ifmr)
462 {
463 struct mlx5e_priv *priv = if_getsoftc(dev);
464
465 ifmr->ifm_status = priv->media_status_last;
466 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last |
467 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
468 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
469
470 }
471
472 static u32
mlx5e_find_link_mode(u32 subtype,bool ext)473 mlx5e_find_link_mode(u32 subtype, bool ext)
474 {
475 u32 link_mode = 0;
476
477 switch (subtype) {
478 case 0:
479 goto done;
480 case IFM_10G_LR:
481 subtype = IFM_10G_ER;
482 break;
483 case IFM_40G_ER4:
484 subtype = IFM_40G_LR4;
485 break;
486 default:
487 break;
488 }
489
490 if (ext) {
491 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) {
492 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) {
493 if (mlx5e_ext_mode_table[i][j].subtype == subtype)
494 link_mode |= MLX5E_PROT_MASK(i);
495 }
496 }
497 } else {
498 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) {
499 if (mlx5e_mode_table[i].subtype == subtype)
500 link_mode |= MLX5E_PROT_MASK(i);
501 }
502 }
503 done:
504 return (link_mode);
505 }
506
507 static int
mlx5e_set_port_pause_and_pfc(struct mlx5e_priv * priv)508 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
509 {
510 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
511 priv->params.rx_pauseframe_control,
512 priv->params.tx_pauseframe_control,
513 priv->params.rx_priority_flow_control,
514 priv->params.tx_priority_flow_control));
515 }
516
517 static int
mlx5e_set_port_pfc(struct mlx5e_priv * priv)518 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
519 {
520 int error;
521
522 if (priv->gone != 0) {
523 error = -ENXIO;
524 } else if (priv->params.rx_pauseframe_control ||
525 priv->params.tx_pauseframe_control) {
526 mlx5_en_err(priv->ifp,
527 "Global pauseframes must be disabled before enabling PFC.\n");
528 error = -EINVAL;
529 } else {
530 error = mlx5e_set_port_pause_and_pfc(priv);
531 }
532 return (error);
533 }
534
535 static int
mlx5e_media_change(if_t dev)536 mlx5e_media_change(if_t dev)
537 {
538 struct mlx5e_priv *priv = if_getsoftc(dev);
539 struct mlx5_core_dev *mdev = priv->mdev;
540 u32 eth_proto_cap;
541 u32 link_mode;
542 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
543 int was_opened;
544 int locked;
545 int error;
546 bool ext;
547
548 locked = PRIV_LOCKED(priv);
549 if (!locked)
550 PRIV_LOCK(priv);
551
552 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
553 error = EINVAL;
554 goto done;
555 }
556
557 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
558 MLX5_PTYS_EN, 1);
559 if (error != 0) {
560 mlx5_en_err(dev, "Query port media capability failed\n");
561 goto done;
562 }
563
564 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
565 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
566
567 /* query supported capabilities */
568 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
569 eth_proto_capability);
570
571 /* check for autoselect */
572 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
573 link_mode = eth_proto_cap;
574 if (link_mode == 0) {
575 mlx5_en_err(dev, "Port media capability is zero\n");
576 error = EINVAL;
577 goto done;
578 }
579 } else {
580 link_mode = link_mode & eth_proto_cap;
581 if (link_mode == 0) {
582 mlx5_en_err(dev, "Not supported link mode requested\n");
583 error = EINVAL;
584 goto done;
585 }
586 }
587 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
588 /* check if PFC is enabled */
589 if (priv->params.rx_priority_flow_control ||
590 priv->params.tx_priority_flow_control) {
591 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
592 error = EINVAL;
593 goto done;
594 }
595 }
596 /* update pauseframe control bits */
597 priv->params.rx_pauseframe_control =
598 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
599 priv->params.tx_pauseframe_control =
600 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
601
602 /* check if device is opened */
603 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
604
605 /* reconfigure the hardware */
606 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
607 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
608 error = -mlx5e_set_port_pause_and_pfc(priv);
609 if (was_opened)
610 mlx5_set_port_status(mdev, MLX5_PORT_UP);
611
612 done:
613 if (!locked)
614 PRIV_UNLOCK(priv);
615 return (error);
616 }
617
618 static void
mlx5e_update_carrier_work(struct work_struct * work)619 mlx5e_update_carrier_work(struct work_struct *work)
620 {
621 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
622 update_carrier_work);
623
624 PRIV_LOCK(priv);
625 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
626 mlx5e_update_carrier(priv);
627 PRIV_UNLOCK(priv);
628 }
629
630 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \
631 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
632
633 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \
634 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
635
636 static void
mlx5e_update_pcie_counters(struct mlx5e_priv * priv)637 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
638 {
639 struct mlx5_core_dev *mdev = priv->mdev;
640 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
641 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
642 void *out;
643 void *in;
644 int err;
645
646 /* allocate firmware request structures */
647 in = mlx5_vzalloc(sz);
648 out = mlx5_vzalloc(sz);
649 if (in == NULL || out == NULL)
650 goto free_out;
651
652 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
653 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
654 if (err != 0)
655 goto free_out;
656
657 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
658 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
659
660 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
661 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
662 if (err != 0)
663 goto free_out;
664
665 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
666
667 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
668 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
669 if (err != 0)
670 goto free_out;
671
672 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
673
674 free_out:
675 /* free firmware request structures */
676 kvfree(in);
677 kvfree(out);
678 }
679
680 /*
681 * This function reads the physical port counters from the firmware
682 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
683 * macros. The output is converted from big-endian 64-bit values into
684 * host endian ones and stored in the "priv->stats.pport" structure.
685 */
686 static void
mlx5e_update_pport_counters(struct mlx5e_priv * priv)687 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
688 {
689 struct mlx5_core_dev *mdev = priv->mdev;
690 struct mlx5e_pport_stats *s = &priv->stats.pport;
691 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
692 u32 *in;
693 u32 *out;
694 const u64 *ptr;
695 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
696 unsigned x;
697 unsigned y;
698 unsigned z;
699
700 /* allocate firmware request structures */
701 in = mlx5_vzalloc(sz);
702 out = mlx5_vzalloc(sz);
703 if (in == NULL || out == NULL)
704 goto free_out;
705
706 /*
707 * Get pointer to the 64-bit counter set which is located at a
708 * fixed offset in the output firmware request structure:
709 */
710 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
711
712 MLX5_SET(ppcnt_reg, in, local_port, 1);
713
714 /* read IEEE802_3 counter group using predefined counter layout */
715 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
716 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
717 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
718 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
719 s->arg[y] = be64toh(ptr[x]);
720
721 /* read RFC2819 counter group using predefined counter layout */
722 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
723 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
724 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
725 s->arg[y] = be64toh(ptr[x]);
726
727 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
728 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
729 s_debug->arg[y] = be64toh(ptr[x]);
730
731 /* read RFC2863 counter group using predefined counter layout */
732 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
733 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
734 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
735 s_debug->arg[y] = be64toh(ptr[x]);
736
737 /* read physical layer stats counter group using predefined counter layout */
738 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
739 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
740 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
741 s_debug->arg[y] = be64toh(ptr[x]);
742
743 /* read Extended Ethernet counter group using predefined counter layout */
744 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
745 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
746 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
747 s_debug->arg[y] = be64toh(ptr[x]);
748
749 /* read Extended Statistical Group */
750 if (MLX5_CAP_GEN(mdev, pcam_reg) &&
751 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
752 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
753 /* read Extended Statistical counter group using predefined counter layout */
754 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
755 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
756
757 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
758 s_debug->arg[y] = be64toh(ptr[x]);
759 }
760
761 /* read PCIE counters */
762 mlx5e_update_pcie_counters(priv);
763
764 /* read per-priority counters */
765 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
766
767 /* iterate all the priorities */
768 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
769 MLX5_SET(ppcnt_reg, in, prio_tc, z);
770 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
771
772 /* read per priority stats counter group using predefined counter layout */
773 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
774 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
775 s->arg[y] = be64toh(ptr[x]);
776 }
777
778 free_out:
779 /* free firmware request structures */
780 kvfree(in);
781 kvfree(out);
782 }
783
784 static void
mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv * priv)785 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
786 {
787 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
788 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
789
790 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
791 return;
792
793 MLX5_SET(query_vnic_env_in, in, opcode,
794 MLX5_CMD_OP_QUERY_VNIC_ENV);
795 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
796 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
797
798 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
799 return;
800
801 priv->stats.vport.rx_steer_missed_packets =
802 MLX5_GET64(query_vnic_env_out, out,
803 vport_env.nic_receive_steering_discard);
804 }
805
806 /*
807 * This function is called regularly to collect all statistics
808 * counters from the firmware. The values can be viewed through the
809 * sysctl interface. Execution is serialized using the priv's global
810 * configuration lock.
811 */
812 static void
mlx5e_update_stats_locked(struct mlx5e_priv * priv)813 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
814 {
815 struct mlx5_core_dev *mdev = priv->mdev;
816 struct mlx5e_vport_stats *s = &priv->stats.vport;
817 struct mlx5e_sq_stats *sq_stats;
818 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
819 u32 *out;
820 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
821 u64 tso_packets = 0;
822 u64 tso_bytes = 0;
823 u64 tx_queue_dropped = 0;
824 u64 tx_defragged = 0;
825 u64 tx_offload_none = 0;
826 u64 lro_packets = 0;
827 u64 lro_bytes = 0;
828 u64 sw_lro_queued = 0;
829 u64 sw_lro_flushed = 0;
830 u64 rx_csum_none = 0;
831 u64 rx_wqe_err = 0;
832 u64 rx_packets = 0;
833 u64 rx_bytes = 0;
834 u64 rx_decrypted_error = 0;
835 u64 rx_decrypted_ok = 0;
836 u32 rx_out_of_buffer = 0;
837 int error;
838 int i;
839 int j;
840
841 out = mlx5_vzalloc(outlen);
842 if (out == NULL)
843 goto free_out;
844
845 /* Collect firts the SW counters and then HW for consistency */
846 for (i = 0; i < priv->params.num_channels; i++) {
847 struct mlx5e_channel *pch = priv->channel + i;
848 struct mlx5e_rq *rq = &pch->rq;
849 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
850
851 /* collect stats from LRO */
852 rq_stats->sw_lro_queued = rq->lro.lro_queued;
853 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
854 sw_lro_queued += rq_stats->sw_lro_queued;
855 sw_lro_flushed += rq_stats->sw_lro_flushed;
856 lro_packets += rq_stats->lro_packets;
857 lro_bytes += rq_stats->lro_bytes;
858 rx_csum_none += rq_stats->csum_none;
859 rx_wqe_err += rq_stats->wqe_err;
860 rx_packets += rq_stats->packets;
861 rx_bytes += rq_stats->bytes;
862 rx_decrypted_error += rq_stats->decrypted_error_packets;
863 rx_decrypted_ok += rq_stats->decrypted_ok_packets;
864
865 for (j = 0; j < priv->num_tc; j++) {
866 sq_stats = &pch->sq[j].stats;
867
868 tso_packets += sq_stats->tso_packets;
869 tso_bytes += sq_stats->tso_bytes;
870 tx_queue_dropped += sq_stats->dropped;
871 tx_queue_dropped += sq_stats->enobuf;
872 tx_defragged += sq_stats->defragged;
873 tx_offload_none += sq_stats->csum_offload_none;
874 }
875 }
876
877 #ifdef RATELIMIT
878 /* Collect statistics from all rate-limit queues */
879 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) {
880 struct mlx5e_rl_worker *rlw = priv->rl.workers + j;
881
882 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) {
883 struct mlx5e_rl_channel *channel = rlw->channels + i;
884 struct mlx5e_sq *sq = channel->sq;
885
886 if (sq == NULL)
887 continue;
888
889 sq_stats = &sq->stats;
890
891 tso_packets += sq_stats->tso_packets;
892 tso_bytes += sq_stats->tso_bytes;
893 tx_queue_dropped += sq_stats->dropped;
894 tx_queue_dropped += sq_stats->enobuf;
895 tx_defragged += sq_stats->defragged;
896 tx_offload_none += sq_stats->csum_offload_none;
897 }
898 }
899 #endif
900
901 /* update counters */
902 s->tso_packets = tso_packets;
903 s->tso_bytes = tso_bytes;
904 s->tx_queue_dropped = tx_queue_dropped;
905 s->tx_defragged = tx_defragged;
906 s->lro_packets = lro_packets;
907 s->lro_bytes = lro_bytes;
908 s->sw_lro_queued = sw_lro_queued;
909 s->sw_lro_flushed = sw_lro_flushed;
910 s->rx_csum_none = rx_csum_none;
911 s->rx_wqe_err = rx_wqe_err;
912 s->rx_packets = rx_packets;
913 s->rx_bytes = rx_bytes;
914 s->rx_decrypted_error_packets = rx_decrypted_error;
915 s->rx_decrypted_ok_packets = rx_decrypted_ok;
916
917 mlx5e_grp_vnic_env_update_stats(priv);
918
919 /* HW counters */
920 memset(in, 0, sizeof(in));
921
922 MLX5_SET(query_vport_counter_in, in, opcode,
923 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
924 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
925 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
926
927 memset(out, 0, outlen);
928
929 /* get number of out-of-buffer drops first */
930 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
931 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
932 &rx_out_of_buffer) == 0) {
933 s->rx_out_of_buffer = rx_out_of_buffer;
934 }
935
936 /* get port statistics */
937 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
938 #define MLX5_GET_CTR(out, x) \
939 MLX5_GET64(query_vport_counter_out, out, x)
940
941 s->rx_error_packets =
942 MLX5_GET_CTR(out, received_errors.packets);
943 s->rx_error_bytes =
944 MLX5_GET_CTR(out, received_errors.octets);
945 s->tx_error_packets =
946 MLX5_GET_CTR(out, transmit_errors.packets);
947 s->tx_error_bytes =
948 MLX5_GET_CTR(out, transmit_errors.octets);
949
950 s->rx_unicast_packets =
951 MLX5_GET_CTR(out, received_eth_unicast.packets);
952 s->rx_unicast_bytes =
953 MLX5_GET_CTR(out, received_eth_unicast.octets);
954 s->tx_unicast_packets =
955 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
956 s->tx_unicast_bytes =
957 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
958
959 s->rx_multicast_packets =
960 MLX5_GET_CTR(out, received_eth_multicast.packets);
961 s->rx_multicast_bytes =
962 MLX5_GET_CTR(out, received_eth_multicast.octets);
963 s->tx_multicast_packets =
964 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
965 s->tx_multicast_bytes =
966 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
967
968 s->rx_broadcast_packets =
969 MLX5_GET_CTR(out, received_eth_broadcast.packets);
970 s->rx_broadcast_bytes =
971 MLX5_GET_CTR(out, received_eth_broadcast.octets);
972 s->tx_broadcast_packets =
973 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
974 s->tx_broadcast_bytes =
975 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
976
977 s->tx_packets = s->tx_unicast_packets +
978 s->tx_multicast_packets + s->tx_broadcast_packets;
979 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
980 s->tx_broadcast_bytes;
981
982 /* Update calculated offload counters */
983 s->tx_csum_offload = s->tx_packets - tx_offload_none;
984 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
985 }
986
987 /* Get physical port counters */
988 mlx5e_update_pport_counters(priv);
989
990 s->tx_jumbo_packets =
991 priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
992 priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
993 priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
994 priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
995
996 free_out:
997 kvfree(out);
998
999 /* Update diagnostics, if any */
1000 if (priv->params_ethtool.diag_pci_enable ||
1001 priv->params_ethtool.diag_general_enable) {
1002 error = mlx5_core_get_diagnostics_full(mdev,
1003 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1004 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1005 if (error != 0)
1006 mlx5_en_err(priv->ifp,
1007 "Failed reading diagnostics: %d\n", error);
1008 }
1009
1010 /* Update FEC, if any */
1011 error = mlx5e_fec_update(priv);
1012 if (error != 0 && error != EOPNOTSUPP) {
1013 mlx5_en_err(priv->ifp,
1014 "Updating FEC failed: %d\n", error);
1015 }
1016
1017 /* Update temperature, if any */
1018 if (priv->params_ethtool.hw_num_temp != 0) {
1019 error = mlx5e_hw_temperature_update(priv);
1020 if (error != 0 && error != EOPNOTSUPP) {
1021 mlx5_en_err(priv->ifp,
1022 "Updating temperature failed: %d\n", error);
1023 }
1024 }
1025 }
1026
1027 static void
mlx5e_update_stats_work(struct work_struct * work)1028 mlx5e_update_stats_work(struct work_struct *work)
1029 {
1030 struct mlx5e_priv *priv;
1031
1032 priv = container_of(work, struct mlx5e_priv, update_stats_work);
1033 PRIV_LOCK(priv);
1034 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1035 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1036 mlx5e_update_stats_locked(priv);
1037 PRIV_UNLOCK(priv);
1038 }
1039
1040 static void
mlx5e_update_stats(void * arg)1041 mlx5e_update_stats(void *arg)
1042 {
1043 struct mlx5e_priv *priv = arg;
1044
1045 queue_work(priv->wq, &priv->update_stats_work);
1046
1047 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv);
1048 }
1049
1050 static void
mlx5e_async_event_sub(struct mlx5e_priv * priv,enum mlx5_dev_event event)1051 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1052 enum mlx5_dev_event event)
1053 {
1054 switch (event) {
1055 case MLX5_DEV_EVENT_PORT_UP:
1056 case MLX5_DEV_EVENT_PORT_DOWN:
1057 queue_work(priv->wq, &priv->update_carrier_work);
1058 break;
1059
1060 default:
1061 break;
1062 }
1063 }
1064
1065 static void
mlx5e_async_event(struct mlx5_core_dev * mdev,void * vpriv,enum mlx5_dev_event event,unsigned long param)1066 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1067 enum mlx5_dev_event event, unsigned long param)
1068 {
1069 struct mlx5e_priv *priv = vpriv;
1070
1071 mtx_lock(&priv->async_events_mtx);
1072 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1073 mlx5e_async_event_sub(priv, event);
1074 mtx_unlock(&priv->async_events_mtx);
1075 }
1076
1077 static void
mlx5e_enable_async_events(struct mlx5e_priv * priv)1078 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1079 {
1080 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1081 }
1082
1083 static void
mlx5e_disable_async_events(struct mlx5e_priv * priv)1084 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1085 {
1086 mtx_lock(&priv->async_events_mtx);
1087 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1088 mtx_unlock(&priv->async_events_mtx);
1089 }
1090
1091 static void mlx5e_calibration_callout(void *arg);
1092 static int mlx5e_calibration_duration = 20;
1093 static int mlx5e_fast_calibration = 1;
1094 static int mlx5e_normal_calibration = 30;
1095
1096 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1097 "MLX5 timestamp calibration parameters");
1098
1099 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1100 &mlx5e_calibration_duration, 0,
1101 "Duration of initial calibration");
1102 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1103 &mlx5e_fast_calibration, 0,
1104 "Recalibration interval during initial calibration");
1105 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1106 &mlx5e_normal_calibration, 0,
1107 "Recalibration interval during normal operations");
1108
1109 /*
1110 * Ignites the calibration process.
1111 */
1112 static void
mlx5e_reset_calibration_callout(struct mlx5e_priv * priv)1113 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1114 {
1115
1116 if (priv->clbr_done == 0)
1117 mlx5e_calibration_callout(priv);
1118 else
1119 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1120 mlx5e_calibration_duration ? mlx5e_fast_calibration :
1121 mlx5e_normal_calibration) * SBT_1S, 0,
1122 mlx5e_calibration_callout, priv, C_DIRECT_EXEC);
1123 }
1124
1125 static uint64_t
mlx5e_timespec2usec(const struct timespec * ts)1126 mlx5e_timespec2usec(const struct timespec *ts)
1127 {
1128
1129 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1130 }
1131
1132 static uint64_t
mlx5e_hw_clock(struct mlx5e_priv * priv)1133 mlx5e_hw_clock(struct mlx5e_priv *priv)
1134 {
1135 struct mlx5_init_seg *iseg;
1136 uint32_t hw_h, hw_h1, hw_l;
1137
1138 iseg = priv->mdev->iseg;
1139 do {
1140 hw_h = ioread32be(&iseg->internal_timer_h);
1141 hw_l = ioread32be(&iseg->internal_timer_l);
1142 hw_h1 = ioread32be(&iseg->internal_timer_h);
1143 } while (hw_h1 != hw_h);
1144 return (((uint64_t)hw_h << 32) | hw_l);
1145 }
1146
1147 /*
1148 * The calibration callout, it runs either in the context of the
1149 * thread which enables calibration, or in callout. It takes the
1150 * snapshot of system and adapter clocks, then advances the pointers to
1151 * the calibration point to allow rx path to read the consistent data
1152 * lockless.
1153 */
1154 static void
mlx5e_calibration_callout(void * arg)1155 mlx5e_calibration_callout(void *arg)
1156 {
1157 struct mlx5e_priv *priv;
1158 struct mlx5e_clbr_point *next, *curr;
1159 struct timespec ts;
1160 int clbr_curr_next;
1161
1162 priv = arg;
1163 curr = &priv->clbr_points[priv->clbr_curr];
1164 clbr_curr_next = priv->clbr_curr + 1;
1165 if (clbr_curr_next >= nitems(priv->clbr_points))
1166 clbr_curr_next = 0;
1167 next = &priv->clbr_points[clbr_curr_next];
1168
1169 next->base_prev = curr->base_curr;
1170 next->clbr_hw_prev = curr->clbr_hw_curr;
1171
1172 next->clbr_hw_curr = mlx5e_hw_clock(priv);
1173 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1174 0) {
1175 if (priv->clbr_done != 0) {
1176 mlx5_en_err(priv->ifp,
1177 "HW failed tstmp frozen %#jx %#jx, disabling\n",
1178 next->clbr_hw_curr, curr->clbr_hw_prev);
1179 priv->clbr_done = 0;
1180 }
1181 atomic_store_rel_int(&curr->clbr_gen, 0);
1182 return;
1183 }
1184
1185 nanouptime(&ts);
1186 next->base_curr = mlx5e_timespec2usec(&ts);
1187
1188 curr->clbr_gen = 0;
1189 atomic_thread_fence_rel();
1190 priv->clbr_curr = clbr_curr_next;
1191 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1192
1193 if (priv->clbr_done < mlx5e_calibration_duration)
1194 priv->clbr_done++;
1195 mlx5e_reset_calibration_callout(priv);
1196 }
1197
1198 static const char *mlx5e_rq_stats_desc[] = {
1199 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1200 };
1201
1202 static int
mlx5e_create_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1203 mlx5e_create_rq(struct mlx5e_channel *c,
1204 struct mlx5e_rq_param *param,
1205 struct mlx5e_rq *rq)
1206 {
1207 struct mlx5e_priv *priv = c->priv;
1208 struct mlx5_core_dev *mdev = priv->mdev;
1209 char buffer[16];
1210 void *rqc = param->rqc;
1211 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1212 int wq_sz;
1213 int err;
1214 int i;
1215 u32 nsegs, wqe_sz;
1216
1217 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1218 if (err != 0)
1219 goto done;
1220
1221 /* Create DMA descriptor TAG */
1222 if ((err = -bus_dma_tag_create(
1223 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1224 1, /* any alignment */
1225 0, /* no boundary */
1226 BUS_SPACE_MAXADDR, /* lowaddr */
1227 BUS_SPACE_MAXADDR, /* highaddr */
1228 NULL, NULL, /* filter, filterarg */
1229 nsegs * wqe_sz, /* maxsize */
1230 nsegs, /* nsegments */
1231 nsegs * wqe_sz, /* maxsegsize */
1232 0, /* flags */
1233 NULL, NULL, /* lockfunc, lockfuncarg */
1234 &rq->dma_tag)))
1235 goto done;
1236
1237 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1238 &rq->wq_ctrl);
1239 if (err)
1240 goto err_free_dma_tag;
1241
1242 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1243
1244 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1245 if (err != 0)
1246 goto err_rq_wq_destroy;
1247
1248 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1249
1250 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1251 if (err)
1252 goto err_rq_wq_destroy;
1253
1254 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN,
1255 mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO);
1256 for (i = 0; i != wq_sz; i++) {
1257 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1258 int j;
1259
1260 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1261 if (err != 0) {
1262 while (i--)
1263 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1264 goto err_rq_mbuf_free;
1265 }
1266
1267 /* set value for constant fields */
1268 for (j = 0; j < rq->nsegs; j++)
1269 wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1270 }
1271
1272 INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1273 if (priv->params.rx_cq_moderation_mode < 2) {
1274 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1275 } else {
1276 void *cqc = container_of(param,
1277 struct mlx5e_channel_param, rq)->rx_cq.cqc;
1278
1279 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1280 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1281 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1282 break;
1283 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1284 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1285 break;
1286 default:
1287 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1288 break;
1289 }
1290 }
1291
1292 rq->ifp = priv->ifp;
1293 rq->channel = c;
1294 rq->ix = c->ix;
1295
1296 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1297 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1298 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1299 rq->stats.arg);
1300 return (0);
1301
1302 err_rq_mbuf_free:
1303 free(rq->mbuf, M_MLX5EN);
1304 tcp_lro_free(&rq->lro);
1305 err_rq_wq_destroy:
1306 mlx5_wq_destroy(&rq->wq_ctrl);
1307 err_free_dma_tag:
1308 bus_dma_tag_destroy(rq->dma_tag);
1309 done:
1310 return (err);
1311 }
1312
1313 static void
mlx5e_destroy_rq(struct mlx5e_rq * rq)1314 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1315 {
1316 int wq_sz;
1317 int i;
1318
1319 /* destroy all sysctl nodes */
1320 sysctl_ctx_free(&rq->stats.ctx);
1321
1322 /* free leftover LRO packets, if any */
1323 tcp_lro_free(&rq->lro);
1324
1325 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1326 for (i = 0; i != wq_sz; i++) {
1327 if (rq->mbuf[i].mbuf != NULL) {
1328 if (rq->mbuf[i].ipsec_mtag != NULL)
1329 m_tag_free(&rq->mbuf[i].ipsec_mtag->tag);
1330 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1331 m_freem(rq->mbuf[i].mbuf);
1332 }
1333 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1334 }
1335 free(rq->mbuf, M_MLX5EN);
1336 mlx5_wq_destroy(&rq->wq_ctrl);
1337 bus_dma_tag_destroy(rq->dma_tag);
1338 }
1339
1340 static int
mlx5e_enable_rq(struct mlx5e_rq * rq,struct mlx5e_rq_param * param)1341 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1342 {
1343 struct mlx5e_channel *c = rq->channel;
1344 struct mlx5e_priv *priv = c->priv;
1345 struct mlx5_core_dev *mdev = priv->mdev;
1346 void *in;
1347 void *rqc;
1348 void *wq;
1349 int inlen;
1350 int err;
1351 u8 ts_format;
1352
1353 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1354 sizeof(u64) * rq->wq_ctrl.buf.npages;
1355 in = mlx5_vzalloc(inlen);
1356 if (in == NULL)
1357 return (-ENOMEM);
1358
1359 ts_format = mlx5_get_rq_default_ts(mdev);
1360 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1361 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1362
1363 memcpy(rqc, param->rqc, sizeof(param->rqc));
1364
1365 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1366 MLX5_SET(rqc, rqc, ts_format, ts_format);
1367 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1368 if (priv->counter_set_id >= 0)
1369 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1370 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1371 MLX5_ADAPTER_PAGE_SHIFT);
1372 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1373
1374 mlx5_fill_page_array(&rq->wq_ctrl.buf,
1375 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1376
1377 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1378
1379 kvfree(in);
1380
1381 return (err);
1382 }
1383
1384 static int
mlx5e_modify_rq(struct mlx5e_rq * rq,int curr_state,int next_state)1385 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1386 {
1387 struct mlx5e_channel *c = rq->channel;
1388 struct mlx5e_priv *priv = c->priv;
1389 struct mlx5_core_dev *mdev = priv->mdev;
1390
1391 void *in;
1392 void *rqc;
1393 int inlen;
1394 int err;
1395
1396 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1397 in = mlx5_vzalloc(inlen);
1398 if (in == NULL)
1399 return (-ENOMEM);
1400
1401 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1402
1403 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1404 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1405 MLX5_SET(rqc, rqc, state, next_state);
1406
1407 err = mlx5_core_modify_rq(mdev, in, inlen);
1408
1409 kvfree(in);
1410
1411 return (err);
1412 }
1413
1414 static void
mlx5e_disable_rq(struct mlx5e_rq * rq)1415 mlx5e_disable_rq(struct mlx5e_rq *rq)
1416 {
1417 struct mlx5e_channel *c = rq->channel;
1418 struct mlx5e_priv *priv = c->priv;
1419 struct mlx5_core_dev *mdev = priv->mdev;
1420
1421 mlx5_core_destroy_rq(mdev, rq->rqn);
1422 }
1423
1424 static int
mlx5e_open_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1425 mlx5e_open_rq(struct mlx5e_channel *c,
1426 struct mlx5e_rq_param *param,
1427 struct mlx5e_rq *rq)
1428 {
1429 int err;
1430
1431 err = mlx5e_create_rq(c, param, rq);
1432 if (err)
1433 return (err);
1434
1435 /* set CQN in RQ parameters */
1436 MLX5_SET(rqc, param->rqc, cqn, c->rq.cq.mcq.cqn);
1437
1438 err = mlx5e_enable_rq(rq, param);
1439 if (err)
1440 goto err_destroy_rq;
1441
1442 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1443 if (err)
1444 goto err_disable_rq;
1445
1446 c->rq.enabled = 1;
1447
1448 return (0);
1449
1450 err_disable_rq:
1451 mlx5e_disable_rq(rq);
1452 err_destroy_rq:
1453 mlx5e_destroy_rq(rq);
1454
1455 return (err);
1456 }
1457
1458 static void
mlx5e_close_rq(struct mlx5e_rq * rq)1459 mlx5e_close_rq(struct mlx5e_rq *rq)
1460 {
1461 mtx_lock(&rq->mtx);
1462 rq->enabled = 0;
1463 callout_stop(&rq->watchdog);
1464 mtx_unlock(&rq->mtx);
1465
1466 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1467 }
1468
1469 static void
mlx5e_close_rq_wait(struct mlx5e_rq * rq)1470 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1471 {
1472
1473 mtx_lock(&rq->mtx);
1474 MPASS(rq->enabled == 0);
1475 while (rq->processing > 0) {
1476 /*
1477 * No wakeup, relying on timeout.
1478 * Use msleep_sbt() since msleep() conflicts with linuxkpi.
1479 */
1480 msleep_sbt(&rq->processing, &rq->mtx, 0, "mlx5ecrq",
1481 tick_sbt * hz, 0, C_HARDCLOCK);
1482 }
1483 mtx_unlock(&rq->mtx);
1484 mlx5e_disable_rq(rq);
1485 mlx5e_close_cq(&rq->cq);
1486 cancel_work_sync(&rq->dim.work);
1487 mlx5e_destroy_rq(rq);
1488 }
1489
1490 /*
1491 * What is a drop RQ and why is it needed?
1492 *
1493 * The RSS indirection table, also called the RQT, selects the
1494 * destination RQ based on the receive queue number, RQN. The RQT is
1495 * frequently referred to by flow steering rules to distribute traffic
1496 * among multiple RQs. The problem is that the RQs cannot be destroyed
1497 * before the RQT referring them is destroyed too. Further, TLS RX
1498 * rules may still be referring to the RQT even if the link went
1499 * down. Because there is no magic RQN for dropping packets, we create
1500 * a dummy RQ, also called drop RQ, which sole purpose is to drop all
1501 * received packets. When the link goes down this RQN is filled in all
1502 * RQT entries, of the main RQT, so the real RQs which are about to be
1503 * destroyed can be released and the TLS RX rules can be sustained.
1504 */
1505 static void
mlx5e_open_drop_rq_comp(struct mlx5_core_cq * mcq __unused,struct mlx5_eqe * eqe __unused)1506 mlx5e_open_drop_rq_comp(struct mlx5_core_cq *mcq __unused, struct mlx5_eqe *eqe __unused)
1507 {
1508 }
1509
1510 static int
mlx5e_open_drop_rq(struct mlx5e_priv * priv,struct mlx5e_rq * drop_rq)1511 mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1512 struct mlx5e_rq *drop_rq)
1513 {
1514 struct mlx5e_cq_param param_cq = {};
1515 struct mlx5e_rq_param param_rq = {};
1516 void *rqc_wq = MLX5_ADDR_OF(rqc, param_rq.rqc, wq);
1517 int err;
1518
1519 /* set channel pointer */
1520 drop_rq->channel = priv->channel;
1521
1522 /* set basic CQ parameters needed */
1523 MLX5_SET(cqc, param_cq.cqc, log_cq_size, 0);
1524 MLX5_SET(cqc, param_cq.cqc, uar_page, priv->mdev->priv.uar->index);
1525
1526 /* open receive completion queue */
1527 err = mlx5e_open_cq(priv, ¶m_cq, &drop_rq->cq,
1528 &mlx5e_open_drop_rq_comp, 0);
1529 if (err)
1530 goto err_done;
1531
1532 /* set basic WQ parameters needed */
1533 MLX5_SET(wq, rqc_wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1534 MLX5_SET(wq, rqc_wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1535 MLX5_SET(wq, rqc_wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + sizeof(struct mlx5_wqe_data_seg)));
1536 MLX5_SET(wq, rqc_wq, log_wq_sz, 0);
1537 MLX5_SET(wq, rqc_wq, pd, priv->pdn);
1538
1539 param_rq.wq.linear = 1;
1540
1541 err = mlx5_wq_ll_create(priv->mdev, ¶m_rq.wq, rqc_wq, &drop_rq->wq,
1542 &drop_rq->wq_ctrl);
1543 if (err)
1544 goto err_close_cq;
1545
1546 /* set CQN in RQ parameters */
1547 MLX5_SET(rqc, param_rq.rqc, cqn, drop_rq->cq.mcq.cqn);
1548
1549 err = mlx5e_enable_rq(drop_rq, ¶m_rq);
1550 if (err)
1551 goto err_wq_destroy;
1552
1553 err = mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1554 if (err)
1555 goto err_disable_rq;
1556
1557 return (err);
1558
1559 err_disable_rq:
1560 mlx5e_disable_rq(drop_rq);
1561 err_wq_destroy:
1562 mlx5_wq_destroy(&drop_rq->wq_ctrl);
1563 err_close_cq:
1564 mlx5e_close_cq(&drop_rq->cq);
1565 err_done:
1566 return (err);
1567 }
1568
1569 static void
mlx5e_close_drop_rq(struct mlx5e_rq * drop_rq)1570 mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
1571 {
1572 mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1573 mlx5e_disable_rq(drop_rq);
1574 mlx5_wq_destroy(&drop_rq->wq_ctrl);
1575 mlx5e_close_cq(&drop_rq->cq);
1576 }
1577
1578 void
mlx5e_free_sq_db(struct mlx5e_sq * sq)1579 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1580 {
1581 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1582 int x;
1583
1584 for (x = 0; x != wq_sz; x++) {
1585 if (sq->mbuf[x].mbuf != NULL) {
1586 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1587 m_freem(sq->mbuf[x].mbuf);
1588 }
1589 if (sq->mbuf[x].mst != NULL) {
1590 m_snd_tag_rele(sq->mbuf[x].mst);
1591 sq->mbuf[x].mst = NULL;
1592 }
1593 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1594 }
1595 free(sq->mbuf, M_MLX5EN);
1596 }
1597
1598 int
mlx5e_alloc_sq_db(struct mlx5e_sq * sq)1599 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1600 {
1601 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1602 int err;
1603 int x;
1604
1605 sq->mbuf = malloc_domainset(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN,
1606 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO);
1607
1608 /* Create DMA descriptor MAPs */
1609 for (x = 0; x != wq_sz; x++) {
1610 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1611 if (err != 0) {
1612 while (x--)
1613 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1614 free(sq->mbuf, M_MLX5EN);
1615 return (err);
1616 }
1617 }
1618 return (0);
1619 }
1620
1621 static const char *mlx5e_sq_stats_desc[] = {
1622 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1623 };
1624
1625 void
mlx5e_update_sq_inline(struct mlx5e_sq * sq)1626 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1627 {
1628 sq->max_inline = sq->priv->params.tx_max_inline;
1629 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1630
1631 /*
1632 * Check if trust state is DSCP or if inline mode is NONE which
1633 * indicates CX-5 or newer hardware.
1634 */
1635 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1636 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1637 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1638 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1639 else
1640 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1641 } else {
1642 sq->min_insert_caps = 0;
1643 }
1644 }
1645
1646 static void
mlx5e_refresh_sq_inline_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)1647 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1648 {
1649 int i;
1650
1651 for (i = 0; i != priv->num_tc; i++) {
1652 mtx_lock(&c->sq[i].lock);
1653 mlx5e_update_sq_inline(&c->sq[i]);
1654 mtx_unlock(&c->sq[i].lock);
1655 }
1656 }
1657
1658 void
mlx5e_refresh_sq_inline(struct mlx5e_priv * priv)1659 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1660 {
1661 int i;
1662
1663 /* check if channels are closed */
1664 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1665 return;
1666
1667 for (i = 0; i < priv->params.num_channels; i++)
1668 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1669 }
1670
1671 static int
mlx5e_create_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1672 mlx5e_create_sq(struct mlx5e_channel *c,
1673 int tc,
1674 struct mlx5e_sq_param *param,
1675 struct mlx5e_sq *sq)
1676 {
1677 struct mlx5e_priv *priv = c->priv;
1678 struct mlx5_core_dev *mdev = priv->mdev;
1679 char buffer[16];
1680 void *sqc = param->sqc;
1681 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1682 int err;
1683
1684 /* Create DMA descriptor TAG */
1685 if ((err = -bus_dma_tag_create(
1686 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1687 1, /* any alignment */
1688 0, /* no boundary */
1689 BUS_SPACE_MAXADDR, /* lowaddr */
1690 BUS_SPACE_MAXADDR, /* highaddr */
1691 NULL, NULL, /* filter, filterarg */
1692 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1693 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1694 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1695 0, /* flags */
1696 NULL, NULL, /* lockfunc, lockfuncarg */
1697 &sq->dma_tag)))
1698 goto done;
1699
1700 sq->mkey_be = cpu_to_be32(priv->mr.key);
1701 sq->ifp = priv->ifp;
1702 sq->priv = priv;
1703 sq->tc = tc;
1704
1705 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1706 &sq->wq_ctrl);
1707 if (err)
1708 goto err_free_dma_tag;
1709
1710 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1711
1712 err = mlx5e_alloc_sq_db(sq);
1713 if (err)
1714 goto err_sq_wq_destroy;
1715
1716 mlx5e_update_sq_inline(sq);
1717
1718 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1719 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1720 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1721 sq->stats.arg);
1722
1723 return (0);
1724
1725 err_sq_wq_destroy:
1726 mlx5_wq_destroy(&sq->wq_ctrl);
1727
1728 err_free_dma_tag:
1729 bus_dma_tag_destroy(sq->dma_tag);
1730 done:
1731 return (err);
1732 }
1733
1734 static void
mlx5e_destroy_sq(struct mlx5e_sq * sq)1735 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1736 {
1737 /* destroy all sysctl nodes */
1738 sysctl_ctx_free(&sq->stats.ctx);
1739
1740 mlx5e_free_sq_db(sq);
1741 mlx5_wq_destroy(&sq->wq_ctrl);
1742 bus_dma_tag_destroy(sq->dma_tag);
1743 }
1744
1745 int
mlx5e_enable_sq(struct mlx5e_sq * sq,struct mlx5e_sq_param * param,const struct mlx5_sq_bfreg * bfreg,int tis_num)1746 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1747 const struct mlx5_sq_bfreg *bfreg, int tis_num)
1748 {
1749 void *in;
1750 void *sqc;
1751 void *wq;
1752 int inlen;
1753 int err;
1754 u8 ts_format;
1755
1756 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1757 sizeof(u64) * sq->wq_ctrl.buf.npages;
1758 in = mlx5_vzalloc(inlen);
1759 if (in == NULL)
1760 return (-ENOMEM);
1761
1762 sq->uar_map = bfreg->map;
1763
1764 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev);
1765 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1766 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1767
1768 memcpy(sqc, param->sqc, sizeof(param->sqc));
1769
1770 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1771 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1772 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1773 MLX5_SET(sqc, sqc, ts_format, ts_format);
1774 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1775 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1776 MLX5_SET(sqc, sqc, allow_swp, 1);
1777
1778 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1779 MLX5_SET(wq, wq, uar_page, bfreg->index);
1780 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1781 MLX5_ADAPTER_PAGE_SHIFT);
1782 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1783
1784 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1785 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1786
1787 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1788
1789 kvfree(in);
1790
1791 return (err);
1792 }
1793
1794 int
mlx5e_modify_sq(struct mlx5e_sq * sq,int curr_state,int next_state)1795 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1796 {
1797 void *in;
1798 void *sqc;
1799 int inlen;
1800 int err;
1801
1802 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1803 in = mlx5_vzalloc(inlen);
1804 if (in == NULL)
1805 return (-ENOMEM);
1806
1807 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1808
1809 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1810 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1811 MLX5_SET(sqc, sqc, state, next_state);
1812
1813 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1814
1815 kvfree(in);
1816
1817 return (err);
1818 }
1819
1820 void
mlx5e_disable_sq(struct mlx5e_sq * sq)1821 mlx5e_disable_sq(struct mlx5e_sq *sq)
1822 {
1823
1824 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1825 }
1826
1827 static int
mlx5e_open_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1828 mlx5e_open_sq(struct mlx5e_channel *c,
1829 int tc,
1830 struct mlx5e_sq_param *param,
1831 struct mlx5e_sq *sq)
1832 {
1833 int err;
1834
1835 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1836
1837 /* ensure the TX completion event factor is not zero */
1838 if (sq->cev_factor == 0)
1839 sq->cev_factor = 1;
1840
1841 err = mlx5e_create_sq(c, tc, param, sq);
1842 if (err)
1843 return (err);
1844
1845 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]);
1846 if (err)
1847 goto err_destroy_sq;
1848
1849 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1850 if (err)
1851 goto err_disable_sq;
1852
1853 WRITE_ONCE(sq->running, 1);
1854
1855 return (0);
1856
1857 err_disable_sq:
1858 mlx5e_disable_sq(sq);
1859 err_destroy_sq:
1860 mlx5e_destroy_sq(sq);
1861
1862 return (err);
1863 }
1864
1865 static void
mlx5e_sq_send_nops_locked(struct mlx5e_sq * sq,int can_sleep)1866 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1867 {
1868 /* fill up remainder with NOPs */
1869 while (sq->cev_counter != 0) {
1870 while (!mlx5e_sq_has_room_for(sq, 1)) {
1871 if (can_sleep != 0) {
1872 mtx_unlock(&sq->lock);
1873 msleep(4);
1874 mtx_lock(&sq->lock);
1875 } else {
1876 goto done;
1877 }
1878 }
1879 /* send a single NOP */
1880 mlx5e_send_nop(sq, 1);
1881 atomic_thread_fence_rel();
1882 }
1883 done:
1884 mlx5e_tx_notify_hw(sq, false);
1885 }
1886
1887 void
mlx5e_sq_cev_timeout(void * arg)1888 mlx5e_sq_cev_timeout(void *arg)
1889 {
1890 struct mlx5e_sq *sq = arg;
1891
1892 mtx_assert(&sq->lock, MA_OWNED);
1893
1894 /* check next state */
1895 switch (sq->cev_next_state) {
1896 case MLX5E_CEV_STATE_SEND_NOPS:
1897 /* fill TX ring with NOPs, if any */
1898 mlx5e_sq_send_nops_locked(sq, 0);
1899
1900 /* check if completed */
1901 if (sq->cev_counter == 0) {
1902 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1903 return;
1904 }
1905 break;
1906 default:
1907 /* send NOPs on next timeout */
1908 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1909 break;
1910 }
1911
1912 /* restart timer */
1913 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1914 }
1915
1916 void
mlx5e_drain_sq(struct mlx5e_sq * sq)1917 mlx5e_drain_sq(struct mlx5e_sq *sq)
1918 {
1919 int error;
1920 struct mlx5_core_dev *mdev= sq->priv->mdev;
1921
1922 /*
1923 * Check if already stopped.
1924 *
1925 * NOTE: Serialization of this function is managed by the
1926 * caller ensuring the priv's state lock is locked or in case
1927 * of rate limit support, a single thread manages drain and
1928 * resume of SQs. The "running" variable can therefore safely
1929 * be read without any locks.
1930 */
1931 if (READ_ONCE(sq->running) == 0)
1932 return;
1933
1934 /* don't put more packets into the SQ */
1935 WRITE_ONCE(sq->running, 0);
1936
1937 /* serialize access to DMA rings */
1938 mtx_lock(&sq->lock);
1939
1940 /* teardown event factor timer, if any */
1941 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1942 callout_stop(&sq->cev_callout);
1943
1944 /* send dummy NOPs in order to flush the transmit ring */
1945 mlx5e_sq_send_nops_locked(sq, 1);
1946 mtx_unlock(&sq->lock);
1947
1948 /* wait till SQ is empty or link is down */
1949 mtx_lock(&sq->lock);
1950 while (sq->cc != sq->pc &&
1951 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1952 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR &&
1953 pci_channel_offline(mdev->pdev) == 0) {
1954 mtx_unlock(&sq->lock);
1955 msleep(1);
1956 sq->cq.mcq.comp(&sq->cq.mcq, NULL);
1957 mtx_lock(&sq->lock);
1958 }
1959 mtx_unlock(&sq->lock);
1960
1961 /* error out remaining requests */
1962 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1963 if (error != 0) {
1964 mlx5_en_err(sq->ifp,
1965 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1966 }
1967
1968 /* wait till SQ is empty */
1969 mtx_lock(&sq->lock);
1970 while (sq->cc != sq->pc &&
1971 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR &&
1972 pci_channel_offline(mdev->pdev) == 0) {
1973 mtx_unlock(&sq->lock);
1974 msleep(1);
1975 sq->cq.mcq.comp(&sq->cq.mcq, NULL);
1976 mtx_lock(&sq->lock);
1977 }
1978 mtx_unlock(&sq->lock);
1979 }
1980
1981 static void
mlx5e_close_sq_wait(struct mlx5e_sq * sq)1982 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1983 {
1984
1985 mlx5e_drain_sq(sq);
1986 mlx5e_disable_sq(sq);
1987 mlx5e_destroy_sq(sq);
1988 }
1989
1990 static int
mlx5e_create_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)1991 mlx5e_create_cq(struct mlx5e_priv *priv,
1992 struct mlx5e_cq_param *param,
1993 struct mlx5e_cq *cq,
1994 mlx5e_cq_comp_t *comp,
1995 int eq_ix)
1996 {
1997 struct mlx5_core_dev *mdev = priv->mdev;
1998 struct mlx5_core_cq *mcq = &cq->mcq;
1999 int eqn_not_used;
2000 int irqn;
2001 int err;
2002 u32 i;
2003
2004 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
2005 if (err)
2006 return (err);
2007
2008 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
2009 &cq->wq_ctrl);
2010 if (err)
2011 return (err);
2012
2013 mcq->cqe_sz = 64;
2014 mcq->set_ci_db = cq->wq_ctrl.db.db;
2015 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2016 *mcq->set_ci_db = 0;
2017 *mcq->arm_db = 0;
2018 mcq->vector = eq_ix;
2019 mcq->comp = comp;
2020 mcq->event = mlx5e_cq_error_event;
2021 mcq->irqn = irqn;
2022
2023 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
2024 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
2025
2026 cqe->op_own = 0xf1;
2027 }
2028
2029 cq->priv = priv;
2030
2031 return (0);
2032 }
2033
2034 static void
mlx5e_destroy_cq(struct mlx5e_cq * cq)2035 mlx5e_destroy_cq(struct mlx5e_cq *cq)
2036 {
2037 mlx5_wq_destroy(&cq->wq_ctrl);
2038 }
2039
2040 static int
mlx5e_enable_cq(struct mlx5e_cq * cq,struct mlx5e_cq_param * param,int eq_ix)2041 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
2042 {
2043 struct mlx5_core_cq *mcq = &cq->mcq;
2044 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
2045 void *in;
2046 void *cqc;
2047 int inlen;
2048 int irqn_not_used;
2049 int eqn;
2050 int err;
2051
2052 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2053 sizeof(u64) * cq->wq_ctrl.buf.npages;
2054 in = mlx5_vzalloc(inlen);
2055 if (in == NULL)
2056 return (-ENOMEM);
2057
2058 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2059
2060 memcpy(cqc, param->cqc, sizeof(param->cqc));
2061
2062 mlx5_fill_page_array(&cq->wq_ctrl.buf,
2063 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
2064
2065 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
2066
2067 MLX5_SET(cqc, cqc, c_eqn, eqn);
2068 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2069 MLX5_ADAPTER_PAGE_SHIFT);
2070 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2071
2072 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out));
2073
2074 kvfree(in);
2075
2076 if (err)
2077 return (err);
2078
2079 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2080
2081 return (0);
2082 }
2083
2084 static void
mlx5e_disable_cq(struct mlx5e_cq * cq)2085 mlx5e_disable_cq(struct mlx5e_cq *cq)
2086 {
2087
2088 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2089 }
2090
2091 int
mlx5e_open_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)2092 mlx5e_open_cq(struct mlx5e_priv *priv,
2093 struct mlx5e_cq_param *param,
2094 struct mlx5e_cq *cq,
2095 mlx5e_cq_comp_t *comp,
2096 int eq_ix)
2097 {
2098 int err;
2099
2100 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2101 if (err)
2102 return (err);
2103
2104 err = mlx5e_enable_cq(cq, param, eq_ix);
2105 if (err)
2106 goto err_destroy_cq;
2107
2108 return (0);
2109
2110 err_destroy_cq:
2111 mlx5e_destroy_cq(cq);
2112
2113 return (err);
2114 }
2115
2116 void
mlx5e_close_cq(struct mlx5e_cq * cq)2117 mlx5e_close_cq(struct mlx5e_cq *cq)
2118 {
2119 mlx5e_disable_cq(cq);
2120 mlx5e_destroy_cq(cq);
2121 }
2122
2123 static int
mlx5e_open_tx_cqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)2124 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2125 struct mlx5e_channel_param *cparam)
2126 {
2127 int err;
2128 int tc;
2129
2130 for (tc = 0; tc < c->priv->num_tc; tc++) {
2131 /* open completion queue */
2132 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2133 &mlx5e_tx_cq_comp, c->ix);
2134 if (err)
2135 goto err_close_tx_cqs;
2136 }
2137 return (0);
2138
2139 err_close_tx_cqs:
2140 for (tc--; tc >= 0; tc--)
2141 mlx5e_close_cq(&c->sq[tc].cq);
2142
2143 return (err);
2144 }
2145
2146 static void
mlx5e_close_tx_cqs(struct mlx5e_channel * c)2147 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2148 {
2149 int tc;
2150
2151 for (tc = 0; tc < c->priv->num_tc; tc++)
2152 mlx5e_close_cq(&c->sq[tc].cq);
2153 }
2154
2155 static int
mlx5e_open_sqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)2156 mlx5e_open_sqs(struct mlx5e_channel *c,
2157 struct mlx5e_channel_param *cparam)
2158 {
2159 int err;
2160 int tc;
2161
2162 for (tc = 0; tc < c->priv->num_tc; tc++) {
2163 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2164 if (err)
2165 goto err_close_sqs;
2166 }
2167
2168 return (0);
2169
2170 err_close_sqs:
2171 for (tc--; tc >= 0; tc--)
2172 mlx5e_close_sq_wait(&c->sq[tc]);
2173
2174 return (err);
2175 }
2176
2177 static void
mlx5e_close_sqs_wait(struct mlx5e_channel * c)2178 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2179 {
2180 int tc;
2181
2182 for (tc = 0; tc < c->priv->num_tc; tc++)
2183 mlx5e_close_sq_wait(&c->sq[tc]);
2184 }
2185
2186 static void
mlx5e_chan_static_init(struct mlx5e_priv * priv,struct mlx5e_channel * c,int ix)2187 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2188 {
2189 int tc;
2190
2191 /* setup priv and channel number */
2192 c->priv = priv;
2193 c->ix = ix;
2194
2195 /* setup send tag */
2196 m_snd_tag_init(&c->tag, c->priv->ifp, &mlx5e_ul_snd_tag_sw);
2197
2198 init_completion(&c->completion);
2199
2200 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2201
2202 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2203
2204 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2205 struct mlx5e_sq *sq = c->sq + tc;
2206
2207 mtx_init(&sq->lock, "mlx5tx",
2208 MTX_NETWORK_LOCK " TX", MTX_DEF);
2209 mtx_init(&sq->comp_lock, "mlx5comp",
2210 MTX_NETWORK_LOCK " TX", MTX_DEF);
2211
2212 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2213 }
2214
2215 mlx5e_iq_static_init(&c->iq);
2216 }
2217
2218 static void
mlx5e_chan_wait_for_completion(struct mlx5e_channel * c)2219 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2220 {
2221
2222 m_snd_tag_rele(&c->tag);
2223 wait_for_completion(&c->completion);
2224 }
2225
2226 static void
mlx5e_priv_wait_for_completion(struct mlx5e_priv * priv,const uint32_t channels)2227 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2228 {
2229 uint32_t x;
2230
2231 for (x = 0; x != channels; x++)
2232 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2233 }
2234
2235 static void
mlx5e_chan_static_destroy(struct mlx5e_channel * c)2236 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2237 {
2238 int tc;
2239
2240 callout_drain(&c->rq.watchdog);
2241
2242 mtx_destroy(&c->rq.mtx);
2243
2244 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2245 callout_drain(&c->sq[tc].cev_callout);
2246 mtx_destroy(&c->sq[tc].lock);
2247 mtx_destroy(&c->sq[tc].comp_lock);
2248 }
2249
2250 mlx5e_iq_static_destroy(&c->iq);
2251 }
2252
2253 static int
mlx5e_open_channel(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam,struct mlx5e_channel * c)2254 mlx5e_open_channel(struct mlx5e_priv *priv,
2255 struct mlx5e_channel_param *cparam,
2256 struct mlx5e_channel *c)
2257 {
2258 struct epoch_tracker et;
2259 int i, err;
2260
2261 /* zero non-persistent data */
2262 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2263 for (i = 0; i != priv->num_tc; i++)
2264 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2265 MLX5E_ZERO(&c->iq, mlx5e_iq_zero_start);
2266
2267 /* open transmit completion queue */
2268 err = mlx5e_open_tx_cqs(c, cparam);
2269 if (err)
2270 goto err_free;
2271
2272 /* open receive completion queue */
2273 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2274 &mlx5e_rx_cq_comp, c->ix);
2275 if (err)
2276 goto err_close_tx_cqs;
2277
2278 err = mlx5e_open_sqs(c, cparam);
2279 if (err)
2280 goto err_close_rx_cq;
2281
2282 err = mlx5e_iq_open(c, &cparam->sq, &cparam->tx_cq, &c->iq);
2283 if (err)
2284 goto err_close_sqs;
2285
2286 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2287 if (err)
2288 goto err_close_iq;
2289
2290 /* poll receive queue initially */
2291 NET_EPOCH_ENTER(et);
2292 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL);
2293 NET_EPOCH_EXIT(et);
2294
2295 return (0);
2296
2297 err_close_iq:
2298 mlx5e_iq_close(&c->iq);
2299
2300 err_close_sqs:
2301 mlx5e_close_sqs_wait(c);
2302
2303 err_close_rx_cq:
2304 mlx5e_close_cq(&c->rq.cq);
2305
2306 err_close_tx_cqs:
2307 mlx5e_close_tx_cqs(c);
2308
2309 err_free:
2310 return (err);
2311 }
2312
2313 static void
mlx5e_close_channel(struct mlx5e_channel * c)2314 mlx5e_close_channel(struct mlx5e_channel *c)
2315 {
2316 mlx5e_close_rq(&c->rq);
2317 }
2318
2319 static void
mlx5e_close_channel_wait(struct mlx5e_channel * c)2320 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2321 {
2322 mlx5e_close_rq_wait(&c->rq);
2323 mlx5e_iq_close(&c->iq);
2324 mlx5e_close_sqs_wait(c);
2325 mlx5e_close_tx_cqs(c);
2326 }
2327
2328 static int
mlx5e_get_wqe_sz(struct mlx5e_priv * priv,u32 * wqe_sz,u32 * nsegs)2329 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2330 {
2331 u32 r, n, maxs;
2332
2333 maxs = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2334 MLX5E_SW2MB_MTU(if_getmtu(priv->ifp));
2335 r = maxs > MCLBYTES ? MJUMPAGESIZE : MCLBYTES;
2336
2337 /*
2338 * n + 1 must be a power of two, because stride size must be.
2339 * Stride size is 16 * (n + 1), as the first segment is
2340 * control.
2341 */
2342 n = roundup_pow_of_two(1 + howmany(maxs, r)) - 1;
2343 if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2344 return (-ENOMEM);
2345
2346 *wqe_sz = r;
2347 *nsegs = n;
2348 return (0);
2349 }
2350
2351 static void
mlx5e_build_rq_param(struct mlx5e_priv * priv,struct mlx5e_rq_param * param)2352 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2353 struct mlx5e_rq_param *param)
2354 {
2355 void *rqc = param->rqc;
2356 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2357 u32 wqe_sz, nsegs;
2358
2359 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2360 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2361 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2362 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2363 nsegs * sizeof(struct mlx5_wqe_data_seg)));
2364 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2365 MLX5_SET(wq, wq, pd, priv->pdn);
2366
2367 param->wq.linear = 1;
2368 }
2369
2370 static void
mlx5e_build_sq_param(struct mlx5e_priv * priv,struct mlx5e_sq_param * param)2371 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2372 struct mlx5e_sq_param *param)
2373 {
2374 void *sqc = param->sqc;
2375 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2376
2377 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2378 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2379 MLX5_SET(wq, wq, pd, priv->pdn);
2380
2381 param->wq.linear = 1;
2382 }
2383
2384 static void
mlx5e_build_common_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2385 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2386 struct mlx5e_cq_param *param)
2387 {
2388 void *cqc = param->cqc;
2389
2390 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2391 }
2392
2393 static void
mlx5e_get_default_profile(struct mlx5e_priv * priv,int mode,struct net_dim_cq_moder * ptr)2394 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2395 {
2396
2397 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2398
2399 /* apply LRO restrictions */
2400 if (priv->params.hw_lro_en &&
2401 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2402 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2403 }
2404 }
2405
2406 static void
mlx5e_build_rx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2407 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2408 struct mlx5e_cq_param *param)
2409 {
2410 struct net_dim_cq_moder curr;
2411 void *cqc = param->cqc;
2412
2413 /*
2414 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2415 * format is more beneficial for FreeBSD use case.
2416 *
2417 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2418 * in mlx5e_decompress_cqe.
2419 */
2420 if (priv->params.cqe_zipping_en) {
2421 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2422 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2423 }
2424
2425 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2426
2427 switch (priv->params.rx_cq_moderation_mode) {
2428 case 0:
2429 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2430 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2431 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2432 break;
2433 case 1:
2434 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2435 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2436 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2437 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2438 else
2439 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2440 break;
2441 case 2:
2442 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2443 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2444 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2445 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2446 break;
2447 case 3:
2448 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2449 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2450 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2451 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2452 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2453 else
2454 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2455 break;
2456 default:
2457 break;
2458 }
2459
2460 mlx5e_dim_build_cq_param(priv, param);
2461
2462 mlx5e_build_common_cq_param(priv, param);
2463 }
2464
2465 static void
mlx5e_build_tx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2466 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2467 struct mlx5e_cq_param *param)
2468 {
2469 void *cqc = param->cqc;
2470
2471 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2472 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2473 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2474
2475 switch (priv->params.tx_cq_moderation_mode) {
2476 case 0:
2477 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2478 break;
2479 default:
2480 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2481 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2482 else
2483 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2484 break;
2485 }
2486
2487 mlx5e_build_common_cq_param(priv, param);
2488 }
2489
2490 static void
mlx5e_build_channel_param(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam)2491 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2492 struct mlx5e_channel_param *cparam)
2493 {
2494 memset(cparam, 0, sizeof(*cparam));
2495
2496 mlx5e_build_rq_param(priv, &cparam->rq);
2497 mlx5e_build_sq_param(priv, &cparam->sq);
2498 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2499 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2500 }
2501
2502 static int
mlx5e_open_channels(struct mlx5e_priv * priv)2503 mlx5e_open_channels(struct mlx5e_priv *priv)
2504 {
2505 struct mlx5e_channel_param *cparam;
2506 int err;
2507 int i;
2508
2509 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2510
2511 mlx5e_build_channel_param(priv, cparam);
2512 for (i = 0; i < priv->params.num_channels; i++) {
2513 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2514 if (err)
2515 goto err_close_channels;
2516
2517 /* Bind interrupt vectors, if any. */
2518 if (priv->params_ethtool.irq_cpu_base > -1) {
2519 cpuset_t cpuset;
2520 int cpu;
2521 int irq;
2522 int eqn;
2523 int nirq;
2524
2525 err = mlx5_vector2eqn(priv->mdev, i,
2526 &eqn, &nirq);
2527
2528 /* error here is non-fatal */
2529 if (err != 0)
2530 continue;
2531
2532 irq = priv->mdev->priv.msix_arr[nirq].vector;
2533 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base +
2534 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus;
2535
2536 CPU_ZERO(&cpuset);
2537 CPU_SET(cpu, &cpuset);
2538 intr_setaffinity(irq, CPU_WHICH_INTRHANDLER, &cpuset);
2539 }
2540 }
2541 free(cparam, M_MLX5EN);
2542 return (0);
2543
2544 err_close_channels:
2545 while (i--) {
2546 mlx5e_close_channel(&priv->channel[i]);
2547 mlx5e_close_channel_wait(&priv->channel[i]);
2548 }
2549 free(cparam, M_MLX5EN);
2550 return (err);
2551 }
2552
2553 static void
mlx5e_close_channels(struct mlx5e_priv * priv)2554 mlx5e_close_channels(struct mlx5e_priv *priv)
2555 {
2556 int i;
2557
2558 for (i = 0; i < priv->params.num_channels; i++)
2559 mlx5e_close_channel(&priv->channel[i]);
2560 for (i = 0; i < priv->params.num_channels; i++)
2561 mlx5e_close_channel_wait(&priv->channel[i]);
2562 }
2563
2564 static int
mlx5e_refresh_sq_params(struct mlx5e_priv * priv,struct mlx5e_sq * sq)2565 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2566 {
2567
2568 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2569 uint8_t cq_mode;
2570
2571 switch (priv->params.tx_cq_moderation_mode) {
2572 case 0:
2573 case 2:
2574 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2575 break;
2576 default:
2577 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2578 break;
2579 }
2580
2581 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2582 priv->params.tx_cq_moderation_usec,
2583 priv->params.tx_cq_moderation_pkts,
2584 cq_mode));
2585 }
2586
2587 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2588 priv->params.tx_cq_moderation_usec,
2589 priv->params.tx_cq_moderation_pkts));
2590 }
2591
2592 static int
mlx5e_refresh_rq_params(struct mlx5e_priv * priv,struct mlx5e_rq * rq)2593 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2594 {
2595
2596 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2597 uint8_t cq_mode;
2598 uint8_t dim_mode;
2599 int retval;
2600
2601 switch (priv->params.rx_cq_moderation_mode) {
2602 case 0:
2603 case 2:
2604 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2605 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2606 break;
2607 default:
2608 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2609 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2610 break;
2611 }
2612
2613 /* tear down dynamic interrupt moderation */
2614 mtx_lock(&rq->mtx);
2615 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2616 mtx_unlock(&rq->mtx);
2617
2618 /* wait for dynamic interrupt moderation work task, if any */
2619 cancel_work_sync(&rq->dim.work);
2620
2621 if (priv->params.rx_cq_moderation_mode >= 2) {
2622 struct net_dim_cq_moder curr;
2623
2624 mlx5e_get_default_profile(priv, dim_mode, &curr);
2625
2626 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2627 curr.usec, curr.pkts, cq_mode);
2628
2629 /* set dynamic interrupt moderation mode and zero defaults */
2630 mtx_lock(&rq->mtx);
2631 rq->dim.mode = dim_mode;
2632 rq->dim.state = 0;
2633 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2634 mtx_unlock(&rq->mtx);
2635 } else {
2636 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2637 priv->params.rx_cq_moderation_usec,
2638 priv->params.rx_cq_moderation_pkts,
2639 cq_mode);
2640 }
2641 return (retval);
2642 }
2643
2644 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2645 priv->params.rx_cq_moderation_usec,
2646 priv->params.rx_cq_moderation_pkts));
2647 }
2648
2649 static int
mlx5e_refresh_channel_params_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)2650 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2651 {
2652 int err;
2653 int i;
2654
2655 err = mlx5e_refresh_rq_params(priv, &c->rq);
2656 if (err)
2657 goto done;
2658
2659 for (i = 0; i != priv->num_tc; i++) {
2660 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2661 if (err)
2662 goto done;
2663 }
2664 done:
2665 return (err);
2666 }
2667
2668 int
mlx5e_refresh_channel_params(struct mlx5e_priv * priv)2669 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2670 {
2671 int i;
2672
2673 /* check if channels are closed */
2674 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2675 return (EINVAL);
2676
2677 for (i = 0; i < priv->params.num_channels; i++) {
2678 int err;
2679
2680 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2681 if (err)
2682 return (err);
2683 }
2684 return (0);
2685 }
2686
2687 static int
mlx5e_open_tis(struct mlx5e_priv * priv,int tc)2688 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2689 {
2690 struct mlx5_core_dev *mdev = priv->mdev;
2691 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2692 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2693
2694 memset(in, 0, sizeof(in));
2695
2696 MLX5_SET(tisc, tisc, prio, tc);
2697 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2698
2699 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2700 }
2701
2702 static void
mlx5e_close_tis(struct mlx5e_priv * priv,int tc)2703 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2704 {
2705 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc], 0);
2706 }
2707
2708 static int
mlx5e_open_tises(struct mlx5e_priv * priv)2709 mlx5e_open_tises(struct mlx5e_priv *priv)
2710 {
2711 int num_tc = priv->num_tc;
2712 int err;
2713 int tc;
2714
2715 for (tc = 0; tc < num_tc; tc++) {
2716 err = mlx5e_open_tis(priv, tc);
2717 if (err)
2718 goto err_close_tises;
2719 }
2720
2721 return (0);
2722
2723 err_close_tises:
2724 for (tc--; tc >= 0; tc--)
2725 mlx5e_close_tis(priv, tc);
2726
2727 return (err);
2728 }
2729
2730 static void
mlx5e_close_tises(struct mlx5e_priv * priv)2731 mlx5e_close_tises(struct mlx5e_priv *priv)
2732 {
2733 int num_tc = priv->num_tc;
2734 int tc;
2735
2736 for (tc = 0; tc < num_tc; tc++)
2737 mlx5e_close_tis(priv, tc);
2738 }
2739
2740 static int
mlx5e_open_default_rqt(struct mlx5e_priv * priv,u32 * prqtn,int sz)2741 mlx5e_open_default_rqt(struct mlx5e_priv *priv, u32 *prqtn, int sz)
2742 {
2743 u32 *in;
2744 void *rqtc;
2745 int inlen;
2746 int err;
2747 int i;
2748
2749 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2750 in = mlx5_vzalloc(inlen);
2751 if (in == NULL)
2752 return (-ENOMEM);
2753 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2754
2755 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2756 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2757
2758 for (i = 0; i != sz; i++)
2759 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2760
2761 err = mlx5_core_create_rqt(priv->mdev, in, inlen, prqtn);
2762 kvfree(in);
2763
2764 return (err);
2765 }
2766
2767 static int
mlx5e_open_rqts(struct mlx5e_priv * priv)2768 mlx5e_open_rqts(struct mlx5e_priv *priv)
2769 {
2770 int err;
2771 int i;
2772
2773 err = mlx5e_open_default_rqt(priv, &priv->rqtn,
2774 1 << priv->params.rx_hash_log_tbl_sz);
2775 if (err)
2776 goto err_default;
2777
2778 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2779 err = mlx5e_open_default_rqt(priv, &priv->channel[i].rqtn, 1);
2780 if (err)
2781 goto err_channel;
2782 }
2783 return (0);
2784
2785 err_channel:
2786 while (i--)
2787 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0);
2788
2789 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0);
2790
2791 err_default:
2792 return (err);
2793 }
2794
2795 static void
mlx5e_close_rqts(struct mlx5e_priv * priv)2796 mlx5e_close_rqts(struct mlx5e_priv *priv)
2797 {
2798 int i;
2799
2800 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++)
2801 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0);
2802
2803 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0);
2804 }
2805
2806 static int
mlx5e_activate_rqt(struct mlx5e_priv * priv)2807 mlx5e_activate_rqt(struct mlx5e_priv *priv)
2808 {
2809 u32 *in;
2810 void *rqtc;
2811 int inlen;
2812 int err;
2813 int sz;
2814 int i;
2815
2816 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2817
2818 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2819 in = mlx5_vzalloc(inlen);
2820 if (in == NULL)
2821 return (-ENOMEM);
2822
2823 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2824
2825 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2826 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2827
2828 for (i = 0; i != sz; i++) {
2829 int ix;
2830 #ifdef RSS
2831 ix = rss_get_indirection_to_bucket(i);
2832 #else
2833 ix = i;
2834 #endif
2835 /* ensure we don't overflow */
2836 ix %= priv->params.num_channels;
2837
2838 /* apply receive side scaling stride, if any */
2839 ix -= ix % (int)priv->params.channels_rsss;
2840
2841 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2842 }
2843
2844 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen);
2845 if (err)
2846 goto err_modify;
2847
2848 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32);
2849
2850 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1);
2851
2852 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2853 int ix;
2854 #ifdef RSS
2855 ix = rss_get_indirection_to_bucket(i);
2856 #else
2857 ix = i;
2858 #endif
2859 /* ensure we don't overflow */
2860 ix %= priv->params.num_channels;
2861
2862 /* apply receive side scaling stride, if any */
2863 ix -= ix % (int)priv->params.channels_rsss;
2864
2865 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn);
2866
2867 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen);
2868 if (err)
2869 goto err_modify;
2870 }
2871
2872 err_modify:
2873 kvfree(in);
2874 return (err);
2875 }
2876
2877 static int
mlx5e_deactivate_rqt(struct mlx5e_priv * priv)2878 mlx5e_deactivate_rqt(struct mlx5e_priv *priv)
2879 {
2880 u32 *in;
2881 void *rqtc;
2882 int inlen;
2883 int err;
2884 int sz;
2885 int i;
2886
2887 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2888
2889 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2890 in = mlx5_vzalloc(inlen);
2891 if (in == NULL)
2892 return (-ENOMEM);
2893
2894 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2895
2896 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2897 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2898
2899 for (i = 0; i != sz; i++)
2900 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2901
2902 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen);
2903 if (err)
2904 goto err_modify;
2905
2906 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32);
2907
2908 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1);
2909
2910 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2911 MLX5_SET(rqtc, rqtc, rq_num[0], priv->drop_rq.rqn);
2912
2913 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen);
2914 if (err)
2915 goto err_modify;
2916 }
2917
2918 err_modify:
2919 kvfree(in);
2920 return (err);
2921 }
2922
2923 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */
2924
2925 static void
mlx5e_get_rss_key(void * key_ptr)2926 mlx5e_get_rss_key(void *key_ptr)
2927 {
2928 #ifdef RSS
2929 rss_getkey(key_ptr);
2930 #else
2931 static const u32 rsskey[] = {
2932 cpu_to_be32(0xD181C62C),
2933 cpu_to_be32(0xF7F4DB5B),
2934 cpu_to_be32(0x1983A2FC),
2935 cpu_to_be32(0x943E1ADB),
2936 cpu_to_be32(0xD9389E6B),
2937 cpu_to_be32(0xD1039C2C),
2938 cpu_to_be32(0xA74499AD),
2939 cpu_to_be32(0x593D56D9),
2940 cpu_to_be32(0xF3253C06),
2941 cpu_to_be32(0x2ADC1FFC),
2942 };
2943 CTASSERT(sizeof(rsskey) == MLX5E_RSS_KEY_SIZE);
2944 memcpy(key_ptr, rsskey, MLX5E_RSS_KEY_SIZE);
2945 #endif
2946 }
2947
2948 static void
mlx5e_hw_lro_set_tir_ctx_lro_max_msg_sz(struct mlx5e_priv * priv,u32 * tirc)2949 mlx5e_hw_lro_set_tir_ctx_lro_max_msg_sz(struct mlx5e_priv *priv, u32 *tirc)
2950 {
2951 MLX5_SET(tirc, tirc, lro_max_msg_sz, (priv->params.lro_wqe_sz >> 8) -
2952 (MLX5_CAP_ETH(priv->mdev, lro_max_msg_sz_mode) == 0 ? 1 : 0));
2953 }
2954
2955 static void
mlx5e_hw_lro_set_tir_ctx(struct mlx5e_priv * priv,u32 * tirc)2956 mlx5e_hw_lro_set_tir_ctx(struct mlx5e_priv *priv, u32 *tirc)
2957 {
2958 MLX5_SET(tirc, tirc, lro_enable_mask,
2959 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2960 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2961 /* TODO: add the option to choose timer value dynamically */
2962 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2963 MLX5_CAP_ETH(priv->mdev, lro_timer_supported_periods[2]));
2964 mlx5e_hw_lro_set_tir_ctx_lro_max_msg_sz(priv, tirc);
2965 }
2966
2967 static int
mlx5e_hw_lro_update_tir(struct mlx5e_priv * priv,int tt,bool inner_vxlan)2968 mlx5e_hw_lro_update_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
2969 {
2970 struct mlx5_core_dev *mdev = priv->mdev;
2971 u32 *in;
2972 void *tirc;
2973 int inlen;
2974 int err;
2975
2976 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2977 in = mlx5_vzalloc(inlen);
2978 if (in == NULL)
2979 return (-ENOMEM);
2980 tirc = MLX5_ADDR_OF(modify_tir_in, in, tir_context);
2981
2982 /* fill the command part */
2983 MLX5_SET(modify_tir_in, in, tirn, inner_vxlan ?
2984 priv->tirn_inner_vxlan[tt] : priv->tirn[tt]);
2985 MLX5_SET64(modify_tir_in, in, modify_bitmask,
2986 (1 << MLX5_MODIFY_TIR_BITMASK_LRO));
2987
2988 /* fill the context */
2989 if (priv->params.hw_lro_en)
2990 mlx5e_hw_lro_set_tir_ctx(priv, tirc);
2991
2992 err = mlx5_core_modify_tir(mdev, in, inlen);
2993
2994 kvfree(in);
2995 return (err);
2996 }
2997
2998 int
mlx5e_hw_lro_update_tirs(struct mlx5e_priv * priv)2999 mlx5e_hw_lro_update_tirs(struct mlx5e_priv *priv)
3000 {
3001 int err, err1, i;
3002
3003 err = 0;
3004 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) {
3005 err1 = mlx5e_hw_lro_update_tir(priv, i / 2, (i % 2) ? true :
3006 false);
3007 if (err1 != 0 && err == 0)
3008 err = err1;
3009 }
3010 return (-err);
3011 }
3012
3013 static void
mlx5e_build_tir_ctx(struct mlx5e_priv * priv,u32 * tirc,int tt,bool inner_vxlan)3014 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan)
3015 {
3016 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
3017 void *hfsi = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
3018 void *hfs = inner_vxlan ? hfsi : hfso;
3019 __be32 *hkey;
3020
3021 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
3022
3023 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
3024 MLX5_HASH_FIELD_SEL_DST_IP)
3025
3026 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
3027 MLX5_HASH_FIELD_SEL_DST_IP |\
3028 MLX5_HASH_FIELD_SEL_L4_SPORT |\
3029 MLX5_HASH_FIELD_SEL_L4_DPORT)
3030
3031 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
3032 MLX5_HASH_FIELD_SEL_DST_IP |\
3033 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
3034
3035 if (priv->params.hw_lro_en)
3036 mlx5e_hw_lro_set_tir_ctx(priv, tirc);
3037
3038 if (inner_vxlan)
3039 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
3040
3041 /*
3042 * All packets must go through the indirection table, RQT,
3043 * because it is not possible to modify the RQN of the TIR
3044 * for direct dispatchment after it is created, typically
3045 * when the link goes up and down.
3046 */
3047 MLX5_SET(tirc, tirc, disp_type,
3048 MLX5_TIRC_DISP_TYPE_INDIRECT);
3049 MLX5_SET(tirc, tirc, indirect_table,
3050 priv->rqtn);
3051 MLX5_SET(tirc, tirc, rx_hash_fn,
3052 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
3053 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
3054
3055 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >=
3056 MLX5E_RSS_KEY_SIZE);
3057 #ifdef RSS
3058 /*
3059 * The FreeBSD RSS implementation does currently not
3060 * support symmetric Toeplitz hashes:
3061 */
3062 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
3063 #else
3064 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
3065 #endif
3066 mlx5e_get_rss_key(hkey);
3067
3068 switch (tt) {
3069 case MLX5E_TT_IPV4_TCP:
3070 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3071 MLX5_L3_PROT_TYPE_IPV4);
3072 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3073 MLX5_L4_PROT_TYPE_TCP);
3074 #ifdef RSS
3075 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
3076 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3077 MLX5_HASH_IP);
3078 } else
3079 #endif
3080 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3081 MLX5_HASH_ALL);
3082 break;
3083
3084 case MLX5E_TT_IPV6_TCP:
3085 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3086 MLX5_L3_PROT_TYPE_IPV6);
3087 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3088 MLX5_L4_PROT_TYPE_TCP);
3089 #ifdef RSS
3090 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
3091 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3092 MLX5_HASH_IP);
3093 } else
3094 #endif
3095 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3096 MLX5_HASH_ALL);
3097 break;
3098
3099 case MLX5E_TT_IPV4_UDP:
3100 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3101 MLX5_L3_PROT_TYPE_IPV4);
3102 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3103 MLX5_L4_PROT_TYPE_UDP);
3104 #ifdef RSS
3105 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
3106 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3107 MLX5_HASH_IP);
3108 } else
3109 #endif
3110 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3111 MLX5_HASH_ALL);
3112 break;
3113
3114 case MLX5E_TT_IPV6_UDP:
3115 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3116 MLX5_L3_PROT_TYPE_IPV6);
3117 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3118 MLX5_L4_PROT_TYPE_UDP);
3119 #ifdef RSS
3120 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
3121 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3122 MLX5_HASH_IP);
3123 } else
3124 #endif
3125 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3126 MLX5_HASH_ALL);
3127 break;
3128
3129 case MLX5E_TT_IPV4_IPSEC_AH:
3130 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3131 MLX5_L3_PROT_TYPE_IPV4);
3132 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3133 MLX5_HASH_IP_IPSEC_SPI);
3134 break;
3135
3136 case MLX5E_TT_IPV6_IPSEC_AH:
3137 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3138 MLX5_L3_PROT_TYPE_IPV6);
3139 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3140 MLX5_HASH_IP_IPSEC_SPI);
3141 break;
3142
3143 case MLX5E_TT_IPV4_IPSEC_ESP:
3144 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3145 MLX5_L3_PROT_TYPE_IPV4);
3146 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3147 MLX5_HASH_IP_IPSEC_SPI);
3148 break;
3149
3150 case MLX5E_TT_IPV6_IPSEC_ESP:
3151 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3152 MLX5_L3_PROT_TYPE_IPV6);
3153 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3154 MLX5_HASH_IP_IPSEC_SPI);
3155 break;
3156
3157 case MLX5E_TT_IPV4:
3158 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3159 MLX5_L3_PROT_TYPE_IPV4);
3160 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3161 MLX5_HASH_IP);
3162 break;
3163
3164 case MLX5E_TT_IPV6:
3165 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3166 MLX5_L3_PROT_TYPE_IPV6);
3167 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3168 MLX5_HASH_IP);
3169 break;
3170
3171 default:
3172 break;
3173 }
3174 }
3175
3176 static int
mlx5e_open_tir(struct mlx5e_priv * priv,int tt,bool inner_vxlan)3177 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
3178 {
3179 struct mlx5_core_dev *mdev = priv->mdev;
3180 u32 *in;
3181 void *tirc;
3182 int inlen;
3183 int err;
3184
3185 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3186 in = mlx5_vzalloc(inlen);
3187 if (in == NULL)
3188 return (-ENOMEM);
3189 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
3190
3191 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan);
3192
3193 err = mlx5_core_create_tir(mdev, in, inlen, inner_vxlan ?
3194 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]);
3195
3196 kvfree(in);
3197
3198 return (err);
3199 }
3200
3201 static void
mlx5e_close_tir(struct mlx5e_priv * priv,int tt,bool inner_vxlan)3202 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
3203 {
3204 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ?
3205 priv->tirn_inner_vxlan[tt] : priv->tirn[tt], 0);
3206 }
3207
3208 static int
mlx5e_open_tirs(struct mlx5e_priv * priv)3209 mlx5e_open_tirs(struct mlx5e_priv *priv)
3210 {
3211 int err;
3212 int i;
3213
3214 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) {
3215 err = mlx5e_open_tir(priv, i / 2, (i % 2) ? true : false);
3216 if (err)
3217 goto err_close_tirs;
3218 }
3219
3220 return (0);
3221
3222 err_close_tirs:
3223 for (i--; i >= 0; i--)
3224 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false);
3225
3226 return (err);
3227 }
3228
3229 static void
mlx5e_close_tirs(struct mlx5e_priv * priv)3230 mlx5e_close_tirs(struct mlx5e_priv *priv)
3231 {
3232 int i;
3233
3234 for (i = 0; i != 2 * MLX5E_NUM_TT; i++)
3235 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false);
3236 }
3237
3238 /*
3239 * SW MTU does not include headers,
3240 * HW MTU includes all headers and checksums.
3241 */
3242 static int
mlx5e_set_dev_port_mtu(if_t ifp,int sw_mtu)3243 mlx5e_set_dev_port_mtu(if_t ifp, int sw_mtu)
3244 {
3245 struct mlx5e_priv *priv = if_getsoftc(ifp);
3246 struct mlx5_core_dev *mdev = priv->mdev;
3247 int hw_mtu;
3248 int err;
3249
3250 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
3251
3252 err = mlx5_set_port_mtu(mdev, hw_mtu);
3253 if (err) {
3254 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
3255 sw_mtu, err);
3256 return (err);
3257 }
3258
3259 /* Update vport context MTU */
3260 err = mlx5_set_vport_mtu(mdev, hw_mtu);
3261 if (err) {
3262 mlx5_en_err(ifp,
3263 "Failed updating vport context with MTU size, err=%d\n",
3264 err);
3265 }
3266
3267 if_setmtu(ifp, sw_mtu);
3268
3269 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
3270 if (err || !hw_mtu) {
3271 /* fallback to port oper mtu */
3272 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
3273 }
3274 if (err) {
3275 mlx5_en_err(ifp,
3276 "Query port MTU, after setting new MTU value, failed\n");
3277 return (err);
3278 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
3279 err = -E2BIG,
3280 mlx5_en_err(ifp,
3281 "Port MTU %d is smaller than ifp mtu %d\n",
3282 hw_mtu, sw_mtu);
3283 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
3284 err = -EINVAL;
3285 mlx5_en_err(ifp,
3286 "Port MTU %d is bigger than ifp mtu %d\n",
3287 hw_mtu, sw_mtu);
3288 }
3289 priv->params_ethtool.hw_mtu = hw_mtu;
3290
3291 /* compute MSB */
3292 while (hw_mtu & (hw_mtu - 1))
3293 hw_mtu &= (hw_mtu - 1);
3294 priv->params_ethtool.hw_mtu_msb = hw_mtu;
3295
3296 return (err);
3297 }
3298
3299 int
mlx5e_open_locked(if_t ifp)3300 mlx5e_open_locked(if_t ifp)
3301 {
3302 struct mlx5e_priv *priv = if_getsoftc(ifp);
3303 int err;
3304 u16 set_id;
3305
3306 /* check if already opened */
3307 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3308 return (0);
3309
3310 #ifdef RSS
3311 if (rss_getnumbuckets() > priv->params.num_channels) {
3312 mlx5_en_info(ifp,
3313 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3314 rss_getnumbuckets(), priv->params.num_channels);
3315 }
3316 #endif
3317 err = mlx5e_open_tises(priv);
3318 if (err) {
3319 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3320 return (err);
3321 }
3322 err = mlx5_vport_alloc_q_counter(priv->mdev,
3323 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3324 if (err) {
3325 mlx5_en_err(priv->ifp,
3326 "mlx5_vport_alloc_q_counter failed: %d\n", err);
3327 goto err_close_tises;
3328 }
3329 /* store counter set ID */
3330 priv->counter_set_id = set_id;
3331
3332 err = mlx5e_open_channels(priv);
3333 if (err) {
3334 mlx5_en_err(ifp,
3335 "mlx5e_open_channels failed, %d\n", err);
3336 goto err_dalloc_q_counter;
3337 }
3338 err = mlx5e_activate_rqt(priv);
3339 if (err) {
3340 mlx5_en_err(ifp, "mlx5e_activate_rqt failed, %d\n", err);
3341 goto err_close_channels;
3342 }
3343
3344 set_bit(MLX5E_STATE_OPENED, &priv->state);
3345
3346 mlx5e_update_carrier(priv);
3347
3348 return (0);
3349
3350 err_close_channels:
3351 mlx5e_close_channels(priv);
3352
3353 err_dalloc_q_counter:
3354 mlx5_vport_dealloc_q_counter(priv->mdev,
3355 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3356
3357 err_close_tises:
3358 mlx5e_close_tises(priv);
3359
3360 return (err);
3361 }
3362
3363 static void
mlx5e_open(void * arg)3364 mlx5e_open(void *arg)
3365 {
3366 struct mlx5e_priv *priv = arg;
3367
3368 PRIV_LOCK(priv);
3369 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3370 mlx5_en_err(priv->ifp,
3371 "Setting port status to up failed\n");
3372
3373 mlx5e_open_locked(priv->ifp);
3374 if_setdrvflagbits(priv->ifp, IFF_DRV_RUNNING, 0);
3375 PRIV_UNLOCK(priv);
3376 }
3377
3378 int
mlx5e_close_locked(if_t ifp)3379 mlx5e_close_locked(if_t ifp)
3380 {
3381 struct mlx5e_priv *priv = if_getsoftc(ifp);
3382
3383 /* check if already closed */
3384 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3385 return (0);
3386
3387 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3388
3389 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3390
3391 mlx5e_deactivate_rqt(priv);
3392 mlx5e_close_channels(priv);
3393 mlx5_vport_dealloc_q_counter(priv->mdev,
3394 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3395 mlx5e_close_tises(priv);
3396
3397 return (0);
3398 }
3399
3400 static uint64_t
mlx5e_get_counter(if_t ifp,ift_counter cnt)3401 mlx5e_get_counter(if_t ifp, ift_counter cnt)
3402 {
3403 struct mlx5e_priv *priv = if_getsoftc(ifp);
3404 u64 retval;
3405
3406 /* PRIV_LOCK(priv); XXX not allowed */
3407 switch (cnt) {
3408 case IFCOUNTER_IPACKETS:
3409 retval = priv->stats.vport.rx_packets;
3410 break;
3411 case IFCOUNTER_IERRORS:
3412 retval = priv->stats.pport.in_range_len_errors +
3413 priv->stats.pport.out_of_range_len +
3414 priv->stats.pport.too_long_errors +
3415 priv->stats.pport.check_seq_err +
3416 priv->stats.pport.alignment_err;
3417 break;
3418 case IFCOUNTER_IQDROPS:
3419 retval = priv->stats.vport.rx_out_of_buffer;
3420 break;
3421 case IFCOUNTER_OPACKETS:
3422 retval = priv->stats.vport.tx_packets;
3423 break;
3424 case IFCOUNTER_OERRORS:
3425 retval = priv->stats.port_stats_debug.out_discards;
3426 break;
3427 case IFCOUNTER_IBYTES:
3428 retval = priv->stats.vport.rx_bytes;
3429 break;
3430 case IFCOUNTER_OBYTES:
3431 retval = priv->stats.vport.tx_bytes;
3432 break;
3433 case IFCOUNTER_IMCASTS:
3434 retval = priv->stats.vport.rx_multicast_packets;
3435 break;
3436 case IFCOUNTER_OMCASTS:
3437 retval = priv->stats.vport.tx_multicast_packets;
3438 break;
3439 case IFCOUNTER_OQDROPS:
3440 retval = priv->stats.vport.tx_queue_dropped;
3441 break;
3442 case IFCOUNTER_COLLISIONS:
3443 retval = priv->stats.pport.collisions;
3444 break;
3445 default:
3446 retval = if_get_counter_default(ifp, cnt);
3447 break;
3448 }
3449 /* PRIV_UNLOCK(priv); XXX not allowed */
3450 return (retval);
3451 }
3452
3453 static void
mlx5e_set_rx_mode(if_t ifp)3454 mlx5e_set_rx_mode(if_t ifp)
3455 {
3456 struct mlx5e_priv *priv = if_getsoftc(ifp);
3457
3458 queue_work(priv->wq, &priv->set_rx_mode_work);
3459 }
3460
3461 static bool
mlx5e_is_ipsec_capable(struct mlx5_core_dev * mdev)3462 mlx5e_is_ipsec_capable(struct mlx5_core_dev *mdev)
3463 {
3464 #ifdef IPSEC_OFFLOAD
3465 if ((mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_PACKET_OFFLOAD) != 0)
3466 return (true);
3467 #endif
3468 return (false);
3469 }
3470
3471 static bool
mlx5e_is_ratelimit_capable(struct mlx5_core_dev * mdev)3472 mlx5e_is_ratelimit_capable(struct mlx5_core_dev *mdev)
3473 {
3474 #ifdef RATELIMIT
3475 if (MLX5_CAP_GEN(mdev, qos) &&
3476 MLX5_CAP_QOS(mdev, packet_pacing))
3477 return (true);
3478 #endif
3479 return (false);
3480 }
3481
3482 static bool
mlx5e_is_tlstx_capable(struct mlx5_core_dev * mdev)3483 mlx5e_is_tlstx_capable(struct mlx5_core_dev *mdev)
3484 {
3485 #ifdef KERN_TLS
3486 if (MLX5_CAP_GEN(mdev, tls_tx) != 0 &&
3487 MLX5_CAP_GEN(mdev, log_max_dek) != 0)
3488 return (true);
3489 #endif
3490 return (false);
3491 }
3492
3493 static bool
mlx5e_is_tlsrx_capable(struct mlx5_core_dev * mdev)3494 mlx5e_is_tlsrx_capable(struct mlx5_core_dev *mdev)
3495 {
3496 #ifdef KERN_TLS
3497 if (MLX5_CAP_GEN(mdev, tls_rx) != 0 &&
3498 MLX5_CAP_GEN(mdev, log_max_dek) != 0 &&
3499 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3500 ft_field_support.outer_ip_version) != 0)
3501 return (true);
3502 #endif
3503 return (false);
3504 }
3505
3506 static int
mlx5e_ioctl(if_t ifp,u_long command,caddr_t data)3507 mlx5e_ioctl(if_t ifp, u_long command, caddr_t data)
3508 {
3509 struct mlx5e_priv *priv;
3510 struct ifreq *ifr;
3511 struct ifdownreason *ifdr;
3512 struct ifi2creq i2c;
3513 struct ifrsskey *ifrk;
3514 struct ifrsshash *ifrh;
3515 struct siocsifcapnv_driver_data *drv_ioctl_data, drv_ioctl_data_d;
3516 int error = 0;
3517 int mask;
3518 int size_read = 0;
3519 int module_status;
3520 int module_num;
3521 int max_mtu;
3522 uint8_t read_addr;
3523
3524 priv = if_getsoftc(ifp);
3525
3526 /* check if detaching */
3527 if (priv == NULL || priv->gone != 0)
3528 return (ENXIO);
3529
3530 switch (command) {
3531 case SIOCSIFMTU:
3532 ifr = (struct ifreq *)data;
3533
3534 PRIV_LOCK(priv);
3535 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3536
3537 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3538 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3539 int was_opened;
3540
3541 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3542 if (was_opened)
3543 mlx5e_close_locked(ifp);
3544
3545 /* set new MTU */
3546 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3547
3548 if (was_opened)
3549 mlx5e_open_locked(ifp);
3550 } else {
3551 error = EINVAL;
3552 mlx5_en_err(ifp,
3553 "Invalid MTU value. Min val: %d, Max val: %d\n",
3554 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3555 }
3556 PRIV_UNLOCK(priv);
3557 break;
3558 case SIOCSIFFLAGS:
3559 if ((if_getflags(ifp) & IFF_UP) &&
3560 (if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
3561 mlx5e_set_rx_mode(ifp);
3562 break;
3563 }
3564 PRIV_LOCK(priv);
3565 if (if_getflags(ifp) & IFF_UP) {
3566 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
3567 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3568 mlx5e_open_locked(ifp);
3569 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
3570 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3571 }
3572 } else {
3573 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3574 mlx5_set_port_status(priv->mdev,
3575 MLX5_PORT_DOWN);
3576 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3577 mlx5e_close_locked(ifp);
3578 mlx5e_update_carrier(priv);
3579 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3580 }
3581 }
3582 PRIV_UNLOCK(priv);
3583 break;
3584 case SIOCADDMULTI:
3585 case SIOCDELMULTI:
3586 mlx5e_set_rx_mode(ifp);
3587 break;
3588 case SIOCSIFMEDIA:
3589 case SIOCGIFMEDIA:
3590 case SIOCGIFXMEDIA:
3591 ifr = (struct ifreq *)data;
3592 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3593 break;
3594 case SIOCGIFCAPNV:
3595 error = 0;
3596 break;
3597 case SIOCSIFCAP:
3598 ifr = (struct ifreq *)data;
3599 drv_ioctl_data = &drv_ioctl_data_d;
3600 drv_ioctl_data->reqcap = ifr->ifr_reqcap;
3601 PRIV_LOCK(priv);
3602 drv_ioctl_data->reqcap2 = if_getcapenable2(ifp);
3603 drv_ioctl_data->nvcap = NULL;
3604 goto siocsifcap_driver;
3605 case SIOCSIFCAPNV:
3606 drv_ioctl_data = (struct siocsifcapnv_driver_data *)data;
3607 PRIV_LOCK(priv);
3608 siocsifcap_driver:
3609 if (!mlx5e_is_tlstx_capable(priv->mdev)) {
3610 drv_ioctl_data->reqcap &= ~(IFCAP_TXTLS4 |
3611 IFCAP_TXTLS6);
3612 }
3613 if (!mlx5e_is_tlsrx_capable(priv->mdev)) {
3614 drv_ioctl_data->reqcap2 &= ~(
3615 IFCAP2_BIT(IFCAP2_RXTLS4) |
3616 IFCAP2_BIT(IFCAP2_RXTLS6));
3617 }
3618 if (!mlx5e_is_ipsec_capable(priv->mdev)) {
3619 drv_ioctl_data->reqcap2 &=
3620 ~IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD);
3621 }
3622 if (!mlx5e_is_ratelimit_capable(priv->mdev)) {
3623 drv_ioctl_data->reqcap &= ~(IFCAP_TXTLS_RTLMT |
3624 IFCAP_TXRTLMT);
3625 }
3626
3627 mask = drv_ioctl_data->reqcap ^ if_getcapenable(ifp);
3628
3629 if (mask & IFCAP_TXCSUM) {
3630 if_togglecapenable(ifp, IFCAP_TXCSUM);
3631 if_togglehwassist(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP));
3632
3633 if (IFCAP_TSO4 & if_getcapenable(ifp) &&
3634 !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3635 mask &= ~IFCAP_TSO4;
3636 if_setcapenablebit(ifp, 0, IFCAP_TSO4);
3637 if_sethwassistbits(ifp, 0, CSUM_IP_TSO);
3638 mlx5_en_err(ifp,
3639 "tso4 disabled due to -txcsum.\n");
3640 }
3641 }
3642 if (mask & IFCAP_TXCSUM_IPV6) {
3643 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
3644 if_togglehwassist(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6));
3645
3646 if (IFCAP_TSO6 & if_getcapenable(ifp) &&
3647 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3648 mask &= ~IFCAP_TSO6;
3649 if_setcapenablebit(ifp, 0, IFCAP_TSO6);
3650 if_sethwassistbits(ifp, 0, CSUM_IP6_TSO);
3651 mlx5_en_err(ifp,
3652 "tso6 disabled due to -txcsum6.\n");
3653 }
3654 }
3655 if (mask & IFCAP_MEXTPG)
3656 if_togglecapenable(ifp, IFCAP_MEXTPG);
3657 if (mask & IFCAP_TXTLS4)
3658 if_togglecapenable(ifp, IFCAP_TXTLS4);
3659 if (mask & IFCAP_TXTLS6)
3660 if_togglecapenable(ifp, IFCAP_TXTLS6);
3661 #ifdef RATELIMIT
3662 if (mask & IFCAP_TXTLS_RTLMT)
3663 if_togglecapenable(ifp, IFCAP_TXTLS_RTLMT);
3664 #endif
3665 if (mask & IFCAP_RXCSUM)
3666 if_togglecapenable(ifp, IFCAP_RXCSUM);
3667 if (mask & IFCAP_RXCSUM_IPV6)
3668 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
3669 if (mask & IFCAP_TSO4) {
3670 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) &&
3671 !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3672 mlx5_en_err(ifp, "enable txcsum first.\n");
3673 error = EAGAIN;
3674 goto out;
3675 }
3676 if_togglecapenable(ifp, IFCAP_TSO4);
3677 if_togglehwassist(ifp, CSUM_IP_TSO);
3678 }
3679 if (mask & IFCAP_TSO6) {
3680 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) &&
3681 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3682 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3683 error = EAGAIN;
3684 goto out;
3685 }
3686 if_togglecapenable(ifp, IFCAP_TSO6);
3687 if_togglehwassist(ifp, CSUM_IP6_TSO);
3688 }
3689 if (mask & IFCAP_VLAN_HWTSO)
3690 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
3691 if (mask & IFCAP_VLAN_HWFILTER) {
3692 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3693 mlx5e_disable_vlan_filter(priv);
3694 else
3695 mlx5e_enable_vlan_filter(priv);
3696
3697 if_togglecapenable(ifp, IFCAP_VLAN_HWFILTER);
3698 }
3699 if (mask & IFCAP_VLAN_HWTAGGING)
3700 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
3701 if (mask & IFCAP_WOL_MAGIC)
3702 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
3703 if (mask & IFCAP_VXLAN_HWCSUM) {
3704 const bool was_enabled =
3705 (if_getcapenable(ifp) & IFCAP_VXLAN_HWCSUM) != 0;
3706 if (was_enabled)
3707 mlx5e_del_all_vxlan_rules(priv);
3708 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM);
3709 if_togglehwassist(ifp, CSUM_INNER_IP | CSUM_INNER_IP_UDP |
3710 CSUM_INNER_IP_TCP | CSUM_INNER_IP6_UDP |
3711 CSUM_INNER_IP6_TCP);
3712 if (!was_enabled) {
3713 int err = mlx5e_add_all_vxlan_rules(priv);
3714 if (err != 0) {
3715 mlx5_en_err(ifp,
3716 "mlx5e_add_all_vxlan_rules() failed, %d (ignored)\n", err);
3717 }
3718 }
3719 }
3720 if (mask & IFCAP_VXLAN_HWTSO) {
3721 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO);
3722 if_togglehwassist(ifp, CSUM_INNER_IP_TSO |
3723 CSUM_INNER_IP6_TSO);
3724 }
3725
3726 VLAN_CAPABILITIES(ifp);
3727
3728 /* hw_lro and IFCAP_LRO are divorsed, only toggle sw LRO. */
3729 if (mask & IFCAP_LRO)
3730 if_togglecapenable(ifp, IFCAP_LRO);
3731
3732 if (mask & IFCAP_HWRXTSTMP) {
3733 if_togglecapenable(ifp, IFCAP_HWRXTSTMP);
3734 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) {
3735 if (priv->clbr_done == 0)
3736 mlx5e_reset_calibration_callout(priv);
3737 } else {
3738 callout_drain(&priv->tstmp_clbr);
3739 priv->clbr_done = 0;
3740 }
3741 }
3742 mask = drv_ioctl_data->reqcap2 ^ if_getcapenable2(ifp);
3743 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS4)) != 0)
3744 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS4));
3745 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS6)) != 0)
3746 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS6));
3747 #ifdef IPSEC_OFFLOAD
3748 if ((mask & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) {
3749 bool was_enabled = (if_getcapenable2(ifp) &
3750 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0;
3751 mlx5e_close_locked(ifp);
3752 if (was_enabled)
3753 ipsec_accel_on_ifdown(priv->ifp);
3754 if_togglecapenable2(ifp,
3755 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD));
3756 mlx5e_open_locked(ifp);
3757 }
3758 #endif
3759 out:
3760 PRIV_UNLOCK(priv);
3761 break;
3762
3763 case SIOCGI2C:
3764 ifr = (struct ifreq *)data;
3765
3766 /*
3767 * Copy from the user-space address ifr_data to the
3768 * kernel-space address i2c
3769 */
3770 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3771 if (error)
3772 break;
3773
3774 if (i2c.len > sizeof(i2c.data)) {
3775 error = EINVAL;
3776 break;
3777 }
3778
3779 PRIV_LOCK(priv);
3780 /* Get module_num which is required for the query_eeprom */
3781 error = mlx5_query_module_num(priv->mdev, &module_num);
3782 if (error) {
3783 mlx5_en_err(ifp,
3784 "Query module num failed, eeprom reading is not supported\n");
3785 error = EINVAL;
3786 goto err_i2c;
3787 }
3788 /* Check if module is present before doing an access */
3789 module_status = mlx5_query_module_status(priv->mdev, module_num);
3790 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3791 if (bootverbose)
3792 mlx5_en_err(ifp,
3793 "Query module %d status: not plugged (%d), "
3794 "eeprom reading is not supported\n",
3795 module_num, module_status);
3796 error = EINVAL;
3797 goto err_i2c;
3798 }
3799 /*
3800 * Currently 0XA0 and 0xA2 are the only addresses permitted.
3801 * The internal conversion is as follows:
3802 */
3803 if (i2c.dev_addr == 0xA0)
3804 read_addr = MLX5_I2C_ADDR_LOW;
3805 else if (i2c.dev_addr == 0xA2)
3806 read_addr = MLX5_I2C_ADDR_HIGH;
3807 else {
3808 mlx5_en_err(ifp,
3809 "Query eeprom failed, Invalid Address: %X\n",
3810 i2c.dev_addr);
3811 error = EINVAL;
3812 goto err_i2c;
3813 }
3814 error = mlx5_query_eeprom(priv->mdev,
3815 read_addr, MLX5_EEPROM_LOW_PAGE,
3816 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3817 (uint32_t *)i2c.data, &size_read);
3818 if (error) {
3819 mlx5_en_err(ifp,
3820 "Query eeprom failed, eeprom reading is not supported\n");
3821 error = EINVAL;
3822 goto err_i2c;
3823 }
3824
3825 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3826 error = mlx5_query_eeprom(priv->mdev,
3827 read_addr, MLX5_EEPROM_LOW_PAGE,
3828 (uint32_t)(i2c.offset + size_read),
3829 (uint32_t)(i2c.len - size_read), module_num,
3830 (uint32_t *)(i2c.data + size_read), &size_read);
3831 }
3832 if (error) {
3833 mlx5_en_err(ifp,
3834 "Query eeprom failed, eeprom reading is not supported\n");
3835 error = EINVAL;
3836 goto err_i2c;
3837 }
3838
3839 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3840 err_i2c:
3841 PRIV_UNLOCK(priv);
3842 break;
3843 case SIOCGIFDOWNREASON:
3844 ifdr = (struct ifdownreason *)data;
3845 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3846 PRIV_LOCK(priv);
3847 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL,
3848 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3849 PRIV_UNLOCK(priv);
3850 if (error == 0)
3851 ifdr->ifdr_reason = IFDR_REASON_MSG;
3852 break;
3853
3854 case SIOCGIFRSSKEY:
3855 ifrk = (struct ifrsskey *)data;
3856 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ;
3857 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE;
3858 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE);
3859 mlx5e_get_rss_key(ifrk->ifrk_key);
3860 break;
3861
3862 case SIOCGIFRSSHASH:
3863 ifrh = (struct ifrsshash *)data;
3864 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ;
3865 ifrh->ifrh_types =
3866 RSS_TYPE_IPV4 |
3867 RSS_TYPE_TCP_IPV4 |
3868 RSS_TYPE_UDP_IPV4 |
3869 RSS_TYPE_IPV6 |
3870 RSS_TYPE_TCP_IPV6 |
3871 RSS_TYPE_UDP_IPV6;
3872 break;
3873
3874 default:
3875 error = ether_ioctl(ifp, command, data);
3876 break;
3877 }
3878 return (error);
3879 }
3880
3881 static int
mlx5e_check_required_hca_cap(struct mlx5_core_dev * mdev)3882 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3883 {
3884 /*
3885 * TODO: uncoment once FW really sets all these bits if
3886 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3887 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3888 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3889 * -ENOTSUPP;
3890 */
3891
3892 /* TODO: add more must-to-have features */
3893
3894 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3895 return (-ENODEV);
3896
3897 return (0);
3898 }
3899
3900 static u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev * mdev)3901 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3902 {
3903 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN;
3904 const int max_size = MLX5E_MAX_TX_INLINE;
3905 const int bf_buf_size =
3906 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) -
3907 (sizeof(struct mlx5e_tx_wqe) - 2);
3908
3909 /* verify against driver limits */
3910 if (bf_buf_size > max_size)
3911 return (max_size);
3912 else if (bf_buf_size < min_size)
3913 return (min_size);
3914 else
3915 return (bf_buf_size);
3916 }
3917
3918 static int
mlx5e_build_ifp_priv(struct mlx5_core_dev * mdev,struct mlx5e_priv * priv,int num_comp_vectors)3919 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3920 struct mlx5e_priv *priv,
3921 int num_comp_vectors)
3922 {
3923 int err;
3924
3925 /*
3926 * TODO: Consider link speed for setting "log_sq_size",
3927 * "log_rq_size" and "cq_moderation_xxx":
3928 */
3929 priv->params.log_sq_size =
3930 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3931 priv->params.log_rq_size =
3932 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3933 priv->params.rx_cq_moderation_usec =
3934 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3935 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3936 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3937 priv->params.rx_cq_moderation_mode =
3938 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3939 priv->params.rx_cq_moderation_pkts =
3940 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3941 priv->params.tx_cq_moderation_usec =
3942 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3943 priv->params.tx_cq_moderation_pkts =
3944 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3945 priv->params.rx_hash_log_tbl_sz =
3946 (order_base_2(num_comp_vectors) >
3947 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3948 order_base_2(num_comp_vectors) :
3949 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3950 priv->params.num_tc = 1;
3951 priv->params.default_vlan_prio = 0;
3952 priv->counter_set_id = -1;
3953 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3954
3955 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3956 if (err)
3957 return (err);
3958
3959 /*
3960 * hw lro is currently defaulted to off. when it won't anymore we
3961 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3962 */
3963 priv->params.hw_lro_en = false;
3964 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3965
3966 /*
3967 * CQE zipping is off, because the per-packet 32-bit Toeplitz hash
3968 * is then not supported. The 32-bit Toeplitz hash is needed to
3969 * correctly demultiplex incoming traffic into the expected
3970 * network queues.
3971 */
3972 priv->params.cqe_zipping_en = false;
3973
3974 priv->mdev = mdev;
3975 priv->params.num_channels = num_comp_vectors;
3976 priv->params.channels_rsss = 1;
3977 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3978 priv->queue_mapping_channel_mask =
3979 roundup_pow_of_two(num_comp_vectors) - 1;
3980 priv->num_tc = priv->params.num_tc;
3981 priv->default_vlan_prio = priv->params.default_vlan_prio;
3982
3983 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3984 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3985 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3986
3987 return (0);
3988 }
3989
3990 static void
mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev * mdev,void * mkc)3991 mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
3992 {
3993 bool ro_pci_enable =
3994 pci_get_relaxed_ordering_enabled(mdev->pdev->dev.bsddev);
3995 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
3996 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read);
3997
3998 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read);
3999 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write);
4000 }
4001
4002 static int
mlx5e_create_mkey(struct mlx5e_priv * priv,u32 pdn,struct mlx5_core_mkey * mkey)4003 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
4004 struct mlx5_core_mkey *mkey)
4005 {
4006 if_t ifp = priv->ifp;
4007 struct mlx5_core_dev *mdev = priv->mdev;
4008 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
4009 void *mkc;
4010 u32 *in;
4011 int err;
4012
4013 in = mlx5_vzalloc(inlen);
4014 if (in == NULL) {
4015 mlx5_en_err(ifp, "failed to allocate inbox\n");
4016 return (-ENOMEM);
4017 }
4018
4019 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
4020 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
4021 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */
4022 MLX5_SET(mkc, mkc, lw, 1);
4023 MLX5_SET(mkc, mkc, lr, 1);
4024 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
4025 MLX5_SET(mkc, mkc, pd, pdn);
4026 MLX5_SET(mkc, mkc, length64, 1);
4027 MLX5_SET(mkc, mkc, qpn, 0xffffff);
4028
4029 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
4030 if (err)
4031 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
4032 err);
4033
4034 kvfree(in);
4035 return (err);
4036 }
4037
4038 static const char *mlx5e_vport_stats_desc[] = {
4039 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
4040 };
4041
4042 static const char *mlx5e_pport_stats_desc[] = {
4043 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
4044 };
4045
4046 static int
mlx5e_priv_static_init(struct mlx5e_priv * priv,struct mlx5_core_dev * mdev,const uint32_t channels)4047 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev,
4048 const uint32_t channels)
4049 {
4050 uint32_t x;
4051 int err;
4052
4053 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
4054 sx_init(&priv->state_lock, "mlx5state");
4055 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
4056 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
4057 for (x = 0; x != channels; x++)
4058 mlx5e_chan_static_init(priv, &priv->channel[x], x);
4059
4060 for (x = 0; x != channels; x++) {
4061 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false);
4062 if (err)
4063 goto err_alloc_bfreg;
4064 }
4065 return (0);
4066
4067 err_alloc_bfreg:
4068 while (x--)
4069 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg);
4070
4071 for (x = 0; x != channels; x++)
4072 mlx5e_chan_static_destroy(&priv->channel[x]);
4073 callout_drain(&priv->watchdog);
4074 mtx_destroy(&priv->async_events_mtx);
4075 sx_destroy(&priv->state_lock);
4076 return (err);
4077 }
4078
4079 static void
mlx5e_priv_static_destroy(struct mlx5e_priv * priv,struct mlx5_core_dev * mdev,const uint32_t channels)4080 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev,
4081 const uint32_t channels)
4082 {
4083 uint32_t x;
4084
4085 for (x = 0; x != channels; x++)
4086 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg);
4087 for (x = 0; x != channels; x++)
4088 mlx5e_chan_static_destroy(&priv->channel[x]);
4089 callout_drain(&priv->watchdog);
4090 mtx_destroy(&priv->async_events_mtx);
4091 sx_destroy(&priv->state_lock);
4092 }
4093
4094 static int
sysctl_firmware(SYSCTL_HANDLER_ARGS)4095 sysctl_firmware(SYSCTL_HANDLER_ARGS)
4096 {
4097 /*
4098 * %d.%d%.d the string format.
4099 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
4100 * We need at most 5 chars to store that.
4101 * It also has: two "." and NULL at the end, which means we need 18
4102 * (5*3 + 3) chars at most.
4103 */
4104 char fw[18];
4105 struct mlx5e_priv *priv = arg1;
4106 int error;
4107
4108 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
4109 fw_rev_sub(priv->mdev));
4110 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
4111 return (error);
4112 }
4113
4114 static void
mlx5e_disable_tx_dma(struct mlx5e_channel * ch)4115 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
4116 {
4117 int i;
4118
4119 for (i = 0; i < ch->priv->num_tc; i++)
4120 mlx5e_drain_sq(&ch->sq[i]);
4121 }
4122
4123 static void
mlx5e_reset_sq_doorbell_record(struct mlx5e_sq * sq)4124 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
4125 {
4126
4127 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
4128 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
4129 mlx5e_tx_notify_hw(sq, true);
4130 }
4131
4132 void
mlx5e_resume_sq(struct mlx5e_sq * sq)4133 mlx5e_resume_sq(struct mlx5e_sq *sq)
4134 {
4135 int err;
4136
4137 /* check if already enabled */
4138 if (READ_ONCE(sq->running) != 0)
4139 return;
4140
4141 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
4142 MLX5_SQC_STATE_RST);
4143 if (err != 0) {
4144 mlx5_en_err(sq->ifp,
4145 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
4146 }
4147
4148 sq->cc = 0;
4149 sq->pc = 0;
4150
4151 /* reset doorbell prior to moving from RST to RDY */
4152 mlx5e_reset_sq_doorbell_record(sq);
4153
4154 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
4155 MLX5_SQC_STATE_RDY);
4156 if (err != 0) {
4157 mlx5_en_err(sq->ifp,
4158 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
4159 }
4160
4161 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
4162 WRITE_ONCE(sq->running, 1);
4163 }
4164
4165 static void
mlx5e_enable_tx_dma(struct mlx5e_channel * ch)4166 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
4167 {
4168 int i;
4169
4170 for (i = 0; i < ch->priv->num_tc; i++)
4171 mlx5e_resume_sq(&ch->sq[i]);
4172 }
4173
4174 static void
mlx5e_disable_rx_dma(struct mlx5e_channel * ch)4175 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
4176 {
4177 struct mlx5e_rq *rq = &ch->rq;
4178 struct epoch_tracker et;
4179 int err;
4180
4181 mtx_lock(&rq->mtx);
4182 rq->enabled = 0;
4183 callout_stop(&rq->watchdog);
4184 mtx_unlock(&rq->mtx);
4185
4186 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
4187 if (err != 0) {
4188 mlx5_en_err(rq->ifp,
4189 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
4190 }
4191
4192 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
4193 msleep(1);
4194 NET_EPOCH_ENTER(et);
4195 rq->cq.mcq.comp(&rq->cq.mcq, NULL);
4196 NET_EPOCH_EXIT(et);
4197 }
4198
4199 /*
4200 * Transitioning into RST state will allow the FW to track less ERR state queues,
4201 * thus reducing the recv queue flushing time
4202 */
4203 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
4204 if (err != 0) {
4205 mlx5_en_err(rq->ifp,
4206 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
4207 }
4208 }
4209
4210 static void
mlx5e_enable_rx_dma(struct mlx5e_channel * ch)4211 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
4212 {
4213 struct mlx5e_rq *rq = &ch->rq;
4214 struct epoch_tracker et;
4215 int err;
4216
4217 rq->wq.wqe_ctr = 0;
4218 mlx5_wq_ll_update_db_record(&rq->wq);
4219 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
4220 if (err != 0) {
4221 mlx5_en_err(rq->ifp,
4222 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
4223 }
4224
4225 rq->enabled = 1;
4226
4227 NET_EPOCH_ENTER(et);
4228 rq->cq.mcq.comp(&rq->cq.mcq, NULL);
4229 NET_EPOCH_EXIT(et);
4230 }
4231
4232 void
mlx5e_modify_tx_dma(struct mlx5e_priv * priv,uint8_t value)4233 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
4234 {
4235 int i;
4236
4237 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
4238 return;
4239
4240 for (i = 0; i < priv->params.num_channels; i++) {
4241 if (value)
4242 mlx5e_disable_tx_dma(&priv->channel[i]);
4243 else
4244 mlx5e_enable_tx_dma(&priv->channel[i]);
4245 }
4246 }
4247
4248 void
mlx5e_modify_rx_dma(struct mlx5e_priv * priv,uint8_t value)4249 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
4250 {
4251 int i;
4252
4253 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
4254 return;
4255
4256 for (i = 0; i < priv->params.num_channels; i++) {
4257 if (value)
4258 mlx5e_disable_rx_dma(&priv->channel[i]);
4259 else
4260 mlx5e_enable_rx_dma(&priv->channel[i]);
4261 }
4262 }
4263
4264 static void
mlx5e_add_hw_stats(struct mlx5e_priv * priv)4265 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
4266 {
4267 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
4268 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
4269 priv, 0, sysctl_firmware, "A", "HCA firmware version");
4270
4271 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
4272 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
4273 "Board ID");
4274 }
4275
4276 static int
mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)4277 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
4278 {
4279 struct mlx5e_priv *priv = arg1;
4280 uint8_t temp[MLX5E_MAX_PRIORITY];
4281 uint32_t tx_pfc;
4282 int err;
4283 int i;
4284
4285 PRIV_LOCK(priv);
4286
4287 tx_pfc = priv->params.tx_priority_flow_control;
4288
4289 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
4290 temp[i] = (tx_pfc >> i) & 1;
4291
4292 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
4293 if (err || !req->newptr)
4294 goto done;
4295 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
4296 if (err)
4297 goto done;
4298
4299 priv->params.tx_priority_flow_control = 0;
4300
4301 /* range check input value */
4302 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
4303 if (temp[i] > 1) {
4304 err = ERANGE;
4305 goto done;
4306 }
4307 priv->params.tx_priority_flow_control |= (temp[i] << i);
4308 }
4309
4310 /* check if update is required */
4311 if (tx_pfc != priv->params.tx_priority_flow_control)
4312 err = -mlx5e_set_port_pfc(priv);
4313 done:
4314 if (err != 0)
4315 priv->params.tx_priority_flow_control= tx_pfc;
4316 PRIV_UNLOCK(priv);
4317
4318 return (err);
4319 }
4320
4321 static int
mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)4322 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
4323 {
4324 struct mlx5e_priv *priv = arg1;
4325 uint8_t temp[MLX5E_MAX_PRIORITY];
4326 uint32_t rx_pfc;
4327 int err;
4328 int i;
4329
4330 PRIV_LOCK(priv);
4331
4332 rx_pfc = priv->params.rx_priority_flow_control;
4333
4334 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
4335 temp[i] = (rx_pfc >> i) & 1;
4336
4337 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
4338 if (err || !req->newptr)
4339 goto done;
4340 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
4341 if (err)
4342 goto done;
4343
4344 priv->params.rx_priority_flow_control = 0;
4345
4346 /* range check input value */
4347 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
4348 if (temp[i] > 1) {
4349 err = ERANGE;
4350 goto done;
4351 }
4352 priv->params.rx_priority_flow_control |= (temp[i] << i);
4353 }
4354
4355 /* check if update is required */
4356 if (rx_pfc != priv->params.rx_priority_flow_control) {
4357 err = -mlx5e_set_port_pfc(priv);
4358 if (err == 0 && priv->sw_is_port_buf_owner)
4359 err = mlx5e_update_buf_lossy(priv);
4360 }
4361 done:
4362 if (err != 0)
4363 priv->params.rx_priority_flow_control= rx_pfc;
4364 PRIV_UNLOCK(priv);
4365
4366 return (err);
4367 }
4368
4369 static void
mlx5e_setup_pauseframes(struct mlx5e_priv * priv)4370 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
4371 {
4372 int error;
4373
4374 /* enable pauseframes by default */
4375 priv->params.tx_pauseframe_control = 1;
4376 priv->params.rx_pauseframe_control = 1;
4377
4378 /* disable ports flow control, PFC, by default */
4379 priv->params.tx_priority_flow_control = 0;
4380 priv->params.rx_priority_flow_control = 0;
4381
4382 /* register pauseframe SYSCTLs */
4383 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4384 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
4385 &priv->params.tx_pauseframe_control, 0,
4386 "Set to enable TX pause frames. Clear to disable.");
4387
4388 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4389 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
4390 &priv->params.rx_pauseframe_control, 0,
4391 "Set to enable RX pause frames. Clear to disable.");
4392
4393 /* register priority flow control, PFC, SYSCTLs */
4394 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4395 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4396 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
4397 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
4398
4399 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4400 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4401 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
4402 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
4403
4404 PRIV_LOCK(priv);
4405
4406 /* range check */
4407 priv->params.tx_pauseframe_control =
4408 priv->params.tx_pauseframe_control ? 1 : 0;
4409 priv->params.rx_pauseframe_control =
4410 priv->params.rx_pauseframe_control ? 1 : 0;
4411
4412 /* update firmware */
4413 error = mlx5e_set_port_pause_and_pfc(priv);
4414 if (error == -EINVAL) {
4415 mlx5_en_err(priv->ifp,
4416 "Global pauseframes must be disabled before enabling PFC.\n");
4417 priv->params.rx_priority_flow_control = 0;
4418 priv->params.tx_priority_flow_control = 0;
4419
4420 /* update firmware */
4421 (void) mlx5e_set_port_pause_and_pfc(priv);
4422 }
4423 PRIV_UNLOCK(priv);
4424 }
4425
4426 static int
mlx5e_ul_snd_tag_alloc(if_t ifp,union if_snd_tag_alloc_params * params,struct m_snd_tag ** ppmt)4427 mlx5e_ul_snd_tag_alloc(if_t ifp,
4428 union if_snd_tag_alloc_params *params,
4429 struct m_snd_tag **ppmt)
4430 {
4431 struct mlx5e_priv *priv;
4432 struct mlx5e_channel *pch;
4433
4434 priv = if_getsoftc(ifp);
4435
4436 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4437 return (EOPNOTSUPP);
4438 } else {
4439 /* keep this code synced with mlx5e_select_queue() */
4440 u32 ch = priv->params.num_channels;
4441 #ifdef RSS
4442 u32 temp;
4443
4444 if (rss_hash2bucket(params->hdr.flowid,
4445 params->hdr.flowtype, &temp) == 0)
4446 ch = temp % ch;
4447 else
4448 #endif
4449 ch = (params->hdr.flowid % 128) % ch;
4450
4451 /*
4452 * NOTE: The channels array is only freed at detach
4453 * and it safe to return a pointer to the send tag
4454 * inside the channels structure as long as we
4455 * reference the priv.
4456 */
4457 pch = priv->channel + ch;
4458
4459 /* check if send queue is not running */
4460 if (unlikely(pch->sq[0].running == 0))
4461 return (ENXIO);
4462 m_snd_tag_ref(&pch->tag);
4463 *ppmt = &pch->tag;
4464 return (0);
4465 }
4466 }
4467
4468 static int
mlx5e_ul_snd_tag_query(struct m_snd_tag * pmt,union if_snd_tag_query_params * params)4469 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4470 {
4471 struct mlx5e_channel *pch =
4472 container_of(pmt, struct mlx5e_channel, tag);
4473
4474 params->unlimited.max_rate = -1ULL;
4475 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4476 return (0);
4477 }
4478
4479 static void
mlx5e_ul_snd_tag_free(struct m_snd_tag * pmt)4480 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4481 {
4482 struct mlx5e_channel *pch =
4483 container_of(pmt, struct mlx5e_channel, tag);
4484
4485 complete(&pch->completion);
4486 }
4487
4488 static int
mlx5e_snd_tag_alloc(if_t ifp,union if_snd_tag_alloc_params * params,struct m_snd_tag ** ppmt)4489 mlx5e_snd_tag_alloc(if_t ifp,
4490 union if_snd_tag_alloc_params *params,
4491 struct m_snd_tag **ppmt)
4492 {
4493
4494 switch (params->hdr.type) {
4495 #ifdef RATELIMIT
4496 case IF_SND_TAG_TYPE_RATE_LIMIT:
4497 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4498 #ifdef KERN_TLS
4499 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4500 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4501 #endif
4502 #endif
4503 case IF_SND_TAG_TYPE_UNLIMITED:
4504 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4505 #ifdef KERN_TLS
4506 case IF_SND_TAG_TYPE_TLS:
4507 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4508 case IF_SND_TAG_TYPE_TLS_RX:
4509 return (mlx5e_tls_rx_snd_tag_alloc(ifp, params, ppmt));
4510 #endif
4511 default:
4512 return (EOPNOTSUPP);
4513 }
4514 }
4515
4516 #ifdef RATELIMIT
4517 #define NUM_HDWR_RATES_MLX 13
4518 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4519 135375, /* 1,083,000 */
4520 180500, /* 1,444,000 */
4521 270750, /* 2,166,000 */
4522 361000, /* 2,888,000 */
4523 541500, /* 4,332,000 */
4524 721875, /* 5,775,000 */
4525 1082875, /* 8,663,000 */
4526 1443875, /* 11,551,000 */
4527 2165750, /* 17,326,000 */
4528 2887750, /* 23,102,000 */
4529 4331625, /* 34,653,000 */
4530 5775500, /* 46,204,000 */
4531 8663125 /* 69,305,000 */
4532 };
4533
4534 static void
mlx5e_ratelimit_query(if_t ifp __unused,struct if_ratelimit_query_results * q)4535 mlx5e_ratelimit_query(if_t ifp __unused, struct if_ratelimit_query_results *q)
4536 {
4537 /*
4538 * This function needs updating by the driver maintainer!
4539 * For the MLX card there are currently (ConectX-4?) 13
4540 * pre-set rates and others i.e. ConnectX-5, 6, 7??
4541 *
4542 * This will change based on later adapters
4543 * and this code should be updated to look at ifp
4544 * and figure out the specific adapter type
4545 * settings i.e. how many rates as well
4546 * as if they are fixed (as is shown here) or
4547 * if they are dynamic (example chelsio t4). Also if there
4548 * is a maximum number of flows that the adapter
4549 * can handle that too needs to be updated in
4550 * the max_flows field.
4551 */
4552 q->rate_table = adapter_rates_mlx;
4553 q->flags = RT_IS_FIXED_TABLE;
4554 q->max_flows = 0; /* mlx has no limit */
4555 q->number_of_rates = NUM_HDWR_RATES_MLX;
4556 q->min_segment_burst = 1;
4557 }
4558 #endif
4559
4560 static void
mlx5e_ifm_add(struct mlx5e_priv * priv,int type)4561 mlx5e_ifm_add(struct mlx5e_priv *priv, int type)
4562 {
4563 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL);
4564 ifmedia_add(&priv->media, type | IFM_ETHER |
4565 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4566 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL);
4567 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL);
4568 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL);
4569 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4570 IFM_ETH_RXPAUSE, 0, NULL);
4571 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4572 IFM_ETH_TXPAUSE, 0, NULL);
4573 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4574 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4575 }
4576
4577 static void *
mlx5e_create_ifp(struct mlx5_core_dev * mdev)4578 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4579 {
4580 if_t ifp;
4581 struct mlx5e_priv *priv;
4582 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4583 struct sysctl_oid_list *child;
4584 int ncv = mdev->priv.eq_table.num_comp_vectors;
4585 char unit[16];
4586 struct pfil_head_args pa;
4587 int err;
4588 u32 eth_proto_cap;
4589 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4590 bool ext;
4591 struct media media_entry = {};
4592
4593 if (mlx5e_check_required_hca_cap(mdev)) {
4594 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4595 return (NULL);
4596 }
4597
4598 /*
4599 * Try to allocate the priv and make room for worst-case
4600 * number of channel structures:
4601 */
4602 priv = malloc_domainset(sizeof(*priv) +
4603 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4604 M_MLX5EN, mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO);
4605
4606 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4607 /* setup all static fields */
4608 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) {
4609 mlx5_core_err(mdev, "mlx5e_priv_static_init() failed\n");
4610 goto err_free_ifp;
4611 }
4612
4613 if_setsoftc(ifp, priv);
4614 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4615 if_setmtu(ifp, ETHERMTU);
4616 if_setinitfn(ifp, mlx5e_open);
4617 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4618 if_setioctlfn(ifp, mlx5e_ioctl);
4619 if_settransmitfn(ifp, mlx5e_xmit);
4620 if_setqflushfn(ifp, if_qflush);
4621 if_setgetcounterfn(ifp, mlx5e_get_counter);
4622 if_setsendqlen(ifp, ifqmaxlen);
4623 /*
4624 * Set driver features
4625 */
4626 if_setcapabilities(ifp, IFCAP_NV);
4627 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6, 0);
4628 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0);
4629 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER, 0);
4630 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE | IFCAP_JUMBO_MTU, 0);
4631 if_setcapabilitiesbit(ifp, IFCAP_LRO, 0);
4632 if_setcapabilitiesbit(ifp, IFCAP_TSO | IFCAP_VLAN_HWTSO, 0);
4633 if_setcapabilitiesbit(ifp, IFCAP_HWSTATS | IFCAP_HWRXTSTMP, 0);
4634 if_setcapabilitiesbit(ifp, IFCAP_MEXTPG, 0);
4635 if (mlx5e_is_tlstx_capable(mdev))
4636 if_setcapabilitiesbit(ifp, IFCAP_TXTLS4 | IFCAP_TXTLS6, 0);
4637 if (mlx5e_is_tlsrx_capable(mdev))
4638 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_RXTLS4) |
4639 IFCAP2_BIT(IFCAP2_RXTLS6), 0);
4640 if (mlx5e_is_ratelimit_capable(mdev)) {
4641 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0);
4642 if (mlx5e_is_tlstx_capable(mdev))
4643 if_setcapabilitiesbit(ifp, IFCAP_TXTLS_RTLMT, 0);
4644 }
4645 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
4646 if (mlx5e_is_ipsec_capable(mdev))
4647 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD),
4648 0);
4649
4650 if_setsndtagallocfn(ifp, mlx5e_snd_tag_alloc);
4651 #ifdef RATELIMIT
4652 if_setratelimitqueryfn(ifp, mlx5e_ratelimit_query);
4653 #endif
4654 /* set TSO limits so that we don't have to drop TX packets */
4655 if_sethwtsomax(ifp, MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN));
4656 if_sethwtsomaxsegcount(ifp, MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */);
4657 if_sethwtsomaxsegsize(ifp, MLX5E_MAX_TX_MBUF_SIZE);
4658
4659 if_setcapenable(ifp, if_getcapabilities(ifp));
4660 if_setcapenable2(ifp, if_getcapabilities2(ifp));
4661 if_sethwassist(ifp, 0);
4662 if (if_getcapenable(ifp) & IFCAP_TSO)
4663 if_sethwassistbits(ifp, CSUM_TSO, 0);
4664 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
4665 if_sethwassistbits(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP), 0);
4666 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
4667 if_sethwassistbits(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6), 0);
4668 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWCSUM)
4669 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP |
4670 CSUM_INNER_IP | CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP |
4671 CSUM_ENCAP_VXLAN, 0);
4672 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWTSO)
4673 if_sethwassistbits(ifp, CSUM_INNER_IP6_TSO | CSUM_INNER_IP_TSO, 0);
4674
4675 /* ifnet sysctl tree */
4676 sysctl_ctx_init(&priv->sysctl_ctx);
4677 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4678 OID_AUTO, if_getdname(ifp), CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4679 "MLX5 ethernet - interface name");
4680 if (priv->sysctl_ifnet == NULL) {
4681 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4682 goto err_free_sysctl;
4683 }
4684 snprintf(unit, sizeof(unit), "%d", if_getdunit(ifp));
4685 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4686 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4687 "MLX5 ethernet - interface unit");
4688 if (priv->sysctl_ifnet == NULL) {
4689 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4690 goto err_free_sysctl;
4691 }
4692
4693 /* HW sysctl tree */
4694 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4695 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4696 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4697 "MLX5 ethernet dev hw");
4698 if (priv->sysctl_hw == NULL) {
4699 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4700 goto err_free_sysctl;
4701 }
4702
4703 err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4704 if (err) {
4705 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4706 goto err_free_sysctl;
4707 }
4708
4709 /* reuse mlx5core's watchdog workqueue */
4710 priv->wq = mdev->priv.health.wq_watchdog;
4711
4712 err = mlx5_core_alloc_pd(mdev, &priv->pdn, 0);
4713 if (err) {
4714 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4715 goto err_free_wq;
4716 }
4717 err = mlx5_alloc_transport_domain(mdev, &priv->tdn, 0);
4718 if (err) {
4719 mlx5_en_err(ifp,
4720 "mlx5_alloc_transport_domain failed, %d\n", err);
4721 goto err_dealloc_pd;
4722 }
4723 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4724 if (err) {
4725 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4726 goto err_dealloc_transport_domain;
4727 }
4728 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4729
4730 /* check if we should generate a random MAC address */
4731 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4732 is_zero_ether_addr(dev_addr)) {
4733 random_ether_addr(dev_addr);
4734 mlx5_en_err(ifp, "Assigned random MAC address\n");
4735 }
4736
4737 err = mlx5e_rl_init(priv);
4738 if (err) {
4739 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4740 goto err_create_mkey;
4741 }
4742
4743 err = mlx5e_tls_init(priv);
4744 if (err) {
4745 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4746 goto err_rl_init;
4747 }
4748
4749 if ((if_getcapenable2(ifp) & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) {
4750 err = mlx5e_ipsec_init(priv);
4751 if (err) {
4752 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4753 goto err_tls_init;
4754 }
4755 }
4756
4757 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4758 if (err) {
4759 if_printf(ifp, "%s: mlx5e_open_drop_rq failed (%d)\n", __func__, err);
4760 goto err_ipsec_init;
4761 }
4762
4763 err = mlx5e_open_rqts(priv);
4764 if (err) {
4765 if_printf(ifp, "%s: mlx5e_open_rqts failed (%d)\n", __func__, err);
4766 goto err_open_drop_rq;
4767 }
4768
4769 err = mlx5e_open_tirs(priv);
4770 if (err) {
4771 mlx5_en_err(ifp, "mlx5e_open_tirs() failed, %d\n", err);
4772 goto err_open_rqts;
4773 }
4774
4775 err = mlx5e_open_flow_tables(priv);
4776 if (err) {
4777 if_printf(ifp, "%s: mlx5e_open_flow_tables failed (%d)\n", __func__, err);
4778 goto err_open_tirs;
4779 }
4780
4781 err = mlx5e_tls_rx_init(priv);
4782 if (err) {
4783 if_printf(ifp, "%s: mlx5e_tls_rx_init() failed, %d\n", __func__, err);
4784 goto err_open_flow_tables;
4785 }
4786
4787 /* set default MTU */
4788 mlx5e_set_dev_port_mtu(ifp, if_getmtu(ifp));
4789
4790 /* Set default media status */
4791 priv->media_status_last = IFM_AVALID;
4792 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX;
4793
4794 /* setup default pauseframes configuration */
4795 mlx5e_setup_pauseframes(priv);
4796
4797 /* Setup supported medias */
4798 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4799 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4800 ptys_extended_ethernet);
4801 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4802 eth_proto_capability);
4803 } else {
4804 ext = false;
4805 eth_proto_cap = 0;
4806 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4807 }
4808
4809 ifmedia_init(&priv->media, IFM_IMASK,
4810 mlx5e_media_change, mlx5e_media_status);
4811
4812 if (ext) {
4813 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) {
4814 /* check if hardware has the right capability */
4815 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap)
4816 continue;
4817 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) {
4818 media_entry = mlx5e_ext_mode_table[i][j];
4819 if (media_entry.subtype == 0)
4820 continue;
4821 /* check if this subtype was already added */
4822 for (unsigned k = 0; k != i; k++) {
4823 /* check if hardware has the right capability */
4824 if (MLX5E_PROT_MASK(k) & ~eth_proto_cap)
4825 continue;
4826 for (unsigned m = 0; m != MLX5E_CABLE_TYPE_NUMBER; m++) {
4827 if (media_entry.subtype == mlx5e_ext_mode_table[k][m].subtype)
4828 goto skip_ext_media;
4829 }
4830 }
4831 mlx5e_ifm_add(priv, media_entry.subtype);
4832 skip_ext_media:;
4833 }
4834 }
4835 } else {
4836 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) {
4837 media_entry = mlx5e_mode_table[i];
4838 if (media_entry.subtype == 0)
4839 continue;
4840 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap)
4841 continue;
4842 /* check if this subtype was already added */
4843 for (unsigned k = 0; k != i; k++) {
4844 if (media_entry.subtype == mlx5e_mode_table[k].subtype)
4845 goto skip_media;
4846 }
4847 mlx5e_ifm_add(priv, media_entry.subtype);
4848
4849 /* NOTE: 10G ER and LR shares the same entry */
4850 if (media_entry.subtype == IFM_10G_ER)
4851 mlx5e_ifm_add(priv, IFM_10G_LR);
4852 skip_media:;
4853 }
4854 }
4855
4856 mlx5e_ifm_add(priv, IFM_AUTO);
4857
4858 /* Set autoselect by default */
4859 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4860 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4861
4862 DEBUGNET_SET(ifp, mlx5_en);
4863
4864 ether_ifattach(ifp, dev_addr);
4865
4866 /* Register for VLAN events */
4867 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4868 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4869 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4870 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4871
4872 /* Register for VxLAN events */
4873 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start,
4874 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY);
4875 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop,
4876 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY);
4877
4878 /* Link is down by default */
4879 if_link_state_change(ifp, LINK_STATE_DOWN);
4880
4881 mlx5e_enable_async_events(priv);
4882
4883 mlx5e_add_hw_stats(priv);
4884
4885 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4886 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4887 priv->stats.vport.arg);
4888
4889 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4890 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4891 priv->stats.pport.arg);
4892
4893 mlx5e_create_ethtool(priv);
4894
4895 mtx_lock(&priv->async_events_mtx);
4896 mlx5e_update_stats(priv);
4897 mtx_unlock(&priv->async_events_mtx);
4898
4899 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4900 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4901 &priv->clbr_done, 0,
4902 "RX timestamps calibration state");
4903 callout_init(&priv->tstmp_clbr, 1);
4904 /* Pull out the frequency of the clock in hz */
4905 priv->cclk = (uint64_t)MLX5_CAP_GEN(mdev, device_frequency_khz) * 1000ULL;
4906 mlx5e_reset_calibration_callout(priv);
4907
4908 pa.pa_version = PFIL_VERSION;
4909 pa.pa_flags = PFIL_IN;
4910 pa.pa_type = PFIL_TYPE_ETHERNET;
4911 pa.pa_headname = if_name(ifp);
4912 priv->pfil = pfil_head_register(&pa);
4913
4914 PRIV_LOCK(priv);
4915 err = mlx5e_open_flow_rules(priv);
4916 if (err) {
4917 mlx5_en_err(ifp,
4918 "mlx5e_open_flow_rules() failed, %d (ignored)\n", err);
4919 }
4920 PRIV_UNLOCK(priv);
4921
4922 return (priv);
4923
4924 err_open_flow_tables:
4925 mlx5e_close_flow_tables(priv);
4926
4927 err_open_tirs:
4928 mlx5e_close_tirs(priv);
4929
4930 err_open_rqts:
4931 mlx5e_close_rqts(priv);
4932
4933 err_open_drop_rq:
4934 mlx5e_close_drop_rq(&priv->drop_rq);
4935
4936 err_ipsec_init:
4937 mlx5e_ipsec_cleanup(priv);
4938
4939 err_tls_init:
4940 mlx5e_tls_cleanup(priv);
4941
4942 err_rl_init:
4943 mlx5e_rl_cleanup(priv);
4944
4945 err_create_mkey:
4946 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4947
4948 err_dealloc_transport_domain:
4949 mlx5_dealloc_transport_domain(mdev, priv->tdn, 0);
4950
4951 err_dealloc_pd:
4952 mlx5_core_dealloc_pd(mdev, priv->pdn, 0);
4953
4954 err_free_wq:
4955 flush_workqueue(priv->wq);
4956
4957 err_free_sysctl:
4958 sysctl_ctx_free(&priv->sysctl_ctx);
4959 if (priv->sysctl_debug)
4960 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4961 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors);
4962
4963 err_free_ifp:
4964 if_free(ifp);
4965 free(priv, M_MLX5EN);
4966 return (NULL);
4967 }
4968
4969 static void
mlx5e_destroy_ifp(struct mlx5_core_dev * mdev,void * vpriv)4970 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4971 {
4972 struct mlx5e_priv *priv = vpriv;
4973 if_t ifp = priv->ifp;
4974
4975 /* don't allow more IOCTLs */
4976 priv->gone = 1;
4977
4978 /* XXX wait a bit to allow IOCTL handlers to complete */
4979 pause("W", hz);
4980
4981 #ifdef RATELIMIT
4982 /*
4983 * Tell the TCP ratelimit code to release the rate-sets attached
4984 * to our ifnet.
4985 */
4986 tcp_rl_release_ifnet(ifp);
4987 /*
4988 * The kernel can still have reference(s) via the m_snd_tag's into
4989 * the ratelimit channels, and these must go away before
4990 * detaching:
4991 */
4992 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4993 mlx5_en_err(priv->ifp,
4994 "Waiting for all ratelimit connections to terminate\n");
4995 pause("W", hz);
4996 }
4997 #endif
4998
4999 #ifdef KERN_TLS
5000 /* wait for all TLS tags to get freed */
5001 while (priv->tls.init != 0 &&
5002 uma_zone_get_cur(priv->tls.zone) != 0) {
5003 mlx5_en_err(priv->ifp,
5004 "Waiting for all TLS connections to terminate\n");
5005 pause("W", hz);
5006 }
5007
5008 /* wait for all TLS RX tags to get freed */
5009 while (priv->tls_rx.init != 0 &&
5010 uma_zone_get_cur(priv->tls_rx.zone) != 0) {
5011 mlx5_en_err(priv->ifp,
5012 "Waiting for all TLS RX connections to terminate\n");
5013 pause("W", hz);
5014 }
5015 #endif
5016 /* wait for all unlimited send tags to complete */
5017 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
5018
5019 /* stop watchdog timer */
5020 callout_drain(&priv->watchdog);
5021
5022 callout_drain(&priv->tstmp_clbr);
5023
5024 if (priv->vlan_attach != NULL)
5025 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
5026 if (priv->vlan_detach != NULL)
5027 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
5028 if (priv->vxlan_start != NULL)
5029 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start);
5030 if (priv->vxlan_stop != NULL)
5031 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop);
5032
5033 /* make sure device gets closed */
5034 PRIV_LOCK(priv);
5035 mlx5e_close_locked(ifp);
5036 mlx5e_close_flow_rules(priv);
5037 PRIV_UNLOCK(priv);
5038
5039 /* deregister pfil */
5040 if (priv->pfil != NULL) {
5041 pfil_head_unregister(priv->pfil);
5042 priv->pfil = NULL;
5043 }
5044
5045 /* unregister device */
5046 ifmedia_removeall(&priv->media);
5047 ether_ifdetach(ifp);
5048
5049 mlx5e_tls_rx_cleanup(priv);
5050 #ifdef IPSEC_OFFLOAD
5051 ipsec_accel_on_ifdown(priv->ifp);
5052 #endif
5053 mlx5e_close_flow_tables(priv);
5054 mlx5e_close_tirs(priv);
5055 mlx5e_close_rqts(priv);
5056 mlx5e_close_drop_rq(&priv->drop_rq);
5057 mlx5e_ipsec_cleanup(priv);
5058 mlx5e_tls_cleanup(priv);
5059 mlx5e_rl_cleanup(priv);
5060
5061 /* destroy all remaining sysctl nodes */
5062 sysctl_ctx_free(&priv->stats.vport.ctx);
5063 sysctl_ctx_free(&priv->stats.pport.ctx);
5064 if (priv->sysctl_debug)
5065 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
5066 sysctl_ctx_free(&priv->sysctl_ctx);
5067
5068 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
5069 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn, 0);
5070 mlx5_core_dealloc_pd(priv->mdev, priv->pdn, 0);
5071 mlx5e_disable_async_events(priv);
5072 flush_workqueue(priv->wq);
5073 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors);
5074 if_free(ifp);
5075 free(priv, M_MLX5EN);
5076 }
5077
5078 #ifdef DEBUGNET
5079 static void
mlx5_en_debugnet_init(if_t dev,int * nrxr,int * ncl,int * clsize)5080 mlx5_en_debugnet_init(if_t dev, int *nrxr, int *ncl, int *clsize)
5081 {
5082 struct mlx5e_priv *priv = if_getsoftc(dev);
5083
5084 PRIV_LOCK(priv);
5085 *nrxr = priv->params.num_channels;
5086 *ncl = DEBUGNET_MAX_IN_FLIGHT;
5087 *clsize = MLX5E_MAX_RX_BYTES;
5088 PRIV_UNLOCK(priv);
5089 }
5090
5091 static void
mlx5_en_debugnet_event(if_t dev,enum debugnet_ev event)5092 mlx5_en_debugnet_event(if_t dev, enum debugnet_ev event)
5093 {
5094 }
5095
5096 static int
mlx5_en_debugnet_transmit(if_t dev,struct mbuf * m)5097 mlx5_en_debugnet_transmit(if_t dev, struct mbuf *m)
5098 {
5099 struct mlx5e_priv *priv = if_getsoftc(dev);
5100 struct mlx5e_sq *sq;
5101 int err;
5102
5103 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5104 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0)
5105 return (ENOENT);
5106
5107 sq = &priv->channel[0].sq[0];
5108
5109 if (sq->running == 0) {
5110 m_freem(m);
5111 return (ENOENT);
5112 }
5113
5114 if (mlx5e_sq_xmit(sq, &m) != 0) {
5115 m_freem(m);
5116 err = ENOBUFS;
5117 } else {
5118 err = 0;
5119 }
5120
5121 mlx5e_tx_notify_hw(sq, true);
5122
5123 return (err);
5124 }
5125
5126 static int
mlx5_en_debugnet_poll(if_t dev,int count)5127 mlx5_en_debugnet_poll(if_t dev, int count)
5128 {
5129 struct mlx5e_priv *priv = if_getsoftc(dev);
5130
5131 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 ||
5132 (priv->media_status_last & IFM_ACTIVE) == 0)
5133 return (ENOENT);
5134
5135 mlx5_poll_interrupts(priv->mdev);
5136
5137 return (0);
5138 }
5139 #endif /* DEBUGNET */
5140
5141 static void *
mlx5e_get_ifp(void * vpriv)5142 mlx5e_get_ifp(void *vpriv)
5143 {
5144 struct mlx5e_priv *priv = vpriv;
5145
5146 return (priv->ifp);
5147 }
5148
5149 static struct mlx5_interface mlx5e_interface = {
5150 .add = mlx5e_create_ifp,
5151 .remove = mlx5e_destroy_ifp,
5152 .event = mlx5e_async_event,
5153 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5154 .get_dev = mlx5e_get_ifp,
5155 };
5156
5157 void
mlx5e_init(void)5158 mlx5e_init(void)
5159 {
5160 mlx5_register_interface(&mlx5e_interface);
5161 }
5162
5163 void
mlx5e_cleanup(void)5164 mlx5e_cleanup(void)
5165 {
5166 mlx5_unregister_interface(&mlx5e_interface);
5167 }
5168
5169 module_init_order(mlx5e_init, SI_ORDER_SIXTH);
5170 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH);
5171
5172 MODULE_DEPEND(mlx5en, ipsec, 1, 1, 1);
5173 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
5174 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
5175 MODULE_VERSION(mlx5en, 1);
5176