Home
last modified time | relevance | path

Searched refs:memories (Results 1 – 25 of 38) sorted by relevance

12

/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt35 power-down idle period in which memories are
40 self-refresh idle period in which memories are
53 period in which memories are placed into
59 memories are placed into self-refresh mode.
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam57-pruss.dtsi36 pruss1_mem: memories@0 {
145 pruss2_mem: memories@0 {
H A Dam4372.dtsi447 pruss1_mem: memories@0 {
535 pruss0_mem: memories@40000 {
/freebsd/sys/contrib/device-tree/Bindings/arm/freescale/
H A Dfsl,imx7ulp-pm.txt7 controlling the power, clocks, and memories of the MCU to achieve the
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Datmel,ebi.txt4 asynchronous (NAND, NOR, SRAM, ....) and synchronous memories (SDR/DDR SDRAMs).
5 The EBI provides a glue-less interface to asynchronous memories through the SMC
H A Dti-aemif.txt5 ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
7 per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Dlpddr3-timings.txt1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
H A Dlpddr2-timings.txt1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
H A Dlpddr3.txt1 * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
/freebsd/sys/contrib/device-tree/Bindings/ddr/
H A Dlpddr3-timings.txt1 * AC timing parameters of LPDDR3 memories for a given speed-bin.
H A Dlpddr2-timings.txt1 * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
H A Dlpddr2.txt1 * LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
H A Dlpddr3.txt1 * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Datmel,lcdc.txt14 for fixed framebuffer memory. Useful for dedicated memories.
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Datmel-sysregs.txt50 embeds secure memories that can be scrambled.
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dqcom,ebi2.txt10 NOR flash memories), WE (write enable). This on top of 6 different chip selects
39 flag somewhere for 8bit memories.
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssembly.td46 "Enable multiple memories">;
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am642-tqma64xxl.dtsi82 rtos_ipc_memory_region: ipc-memories@a5000000 {
H A Dk3-am68-sk-som.dtsi126 rtos_ipc_memory_region: ipc-memories@a8000000 {
H A Dk3-j7200-som-p0.dtsi80 rtos_ipc_memory_region: ipc-memories@a4000000 {
H A Dk3-j721s2-som-p0.dtsi130 rtos_ipc_memory_region: ipc-memories@a8000000 {
H A Dk3-j721e-som-p0.dtsi140 rtos_ipc_memory_region: ipc-memories@aa000000 {
/freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/
H A DWasmDumper.cpp198 for (const wasm::WasmLimits &Memory : Obj->memories()) { in printSectionHeaders()
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dbrcm,iproc-pcie.txt47 an event queue based MSI support. The iProc MSI uses host memories to store
/freebsd/contrib/llvm-project/llvm/include/llvm/Object/
H A DWasm.h147 ArrayRef<wasm::WasmLimits> memories() const { return Memories; } in memories() function

12